From 70f633de02777501eba552b2a46df48f37dab136 Mon Sep 17 00:00:00 2001 From: michael Date: Tue, 20 Mar 2007 23:32:26 +0000 Subject: [PATCH] eth_cop --- ethernet/source/top.vhd | 84 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index 8c90690..d181c52 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -154,6 +154,49 @@ PORT( ); END COMPONENT; +COMPONENT eth_cop +PORT( + wb_clk_i : IN std_logic; + wb_rst_i : IN std_logic; + m1_wb_adr_i : IN std_logic_vector(31 downto 0); + m1_wb_sel_i : IN std_logic_vector(3 downto 0); + m1_wb_we_i : IN std_logic; + m1_wb_dat_i : IN std_logic_vector(31 downto 0); + m1_wb_cyc_i : IN std_logic; + m1_wb_stb_i : IN std_logic; + m2_wb_adr_i : IN std_logic_vector(31 downto 0); + m2_wb_sel_i : IN std_logic_vector(3 downto 0); + m2_wb_we_i : IN std_logic; + m2_wb_dat_i : IN std_logic_vector(31 downto 0); + m2_wb_cyc_i : IN std_logic; + m2_wb_stb_i : IN std_logic; + s1_wb_ack_i : IN std_logic; + s1_wb_err_i : IN std_logic; + s1_wb_dat_i : IN std_logic_vector(31 downto 0); + s2_wb_ack_i : IN std_logic; + s2_wb_err_i : IN std_logic; + s2_wb_dat_i : IN std_logic_vector(31 downto 0); + m1_wb_dat_o : OUT std_logic_vector(31 downto 0); + m1_wb_ack_o : OUT std_logic; + m1_wb_err_o : OUT std_logic; + m2_wb_dat_o : OUT std_logic_vector(31 downto 0); + m2_wb_ack_o : OUT std_logic; + m2_wb_err_o : OUT std_logic; + s1_wb_adr_o : OUT std_logic_vector(31 downto 0); + s1_wb_sel_o : OUT std_logic_vector(3 downto 0); + s1_wb_we_o : OUT std_logic; + s1_wb_cyc_o : OUT std_logic; + s1_wb_stb_o : OUT std_logic; + s1_wb_dat_o : OUT std_logic_vector(31 downto 0); + s2_wb_adr_o : OUT std_logic_vector(31 downto 0); + s2_wb_sel_o : OUT std_logic_vector(3 downto 0); + s2_wb_we_o : OUT std_logic; + s2_wb_cyc_o : OUT std_logic; + s2_wb_stb_o : OUT std_logic; + s2_wb_dat_o : OUT std_logic_vector(31 downto 0) + ); +END COMPONENT; + signal pci_rst_o : std_logic; signal pci_rst_oe_o : std_logic; signal pci_inta_o : std_logic; @@ -346,4 +389,45 @@ Inst_eth_top: eth_top PORT MAP( int_o => int_o ); +--Inst_eth_cop: eth_cop PORT MAP( +-- wb_clk_i => , +-- wb_rst_i => , +-- m1_wb_adr_i => , +-- m1_wb_sel_i => , +-- m1_wb_we_i => , +-- m1_wb_dat_o => , +-- m1_wb_dat_i => , +-- m1_wb_cyc_i => , +-- m1_wb_stb_i => , +-- m1_wb_ack_o => , +-- m1_wb_err_o => , +-- m2_wb_adr_i => , +-- m2_wb_sel_i => , +-- m2_wb_we_i => , +-- m2_wb_dat_o => , +-- m2_wb_dat_i => , +-- m2_wb_cyc_i => , +-- m2_wb_stb_i => , +-- m2_wb_ack_o => , +-- m2_wb_err_o => , +-- s1_wb_adr_o => , +-- s1_wb_sel_o => , +-- s1_wb_we_o => , +-- s1_wb_cyc_o => , +-- s1_wb_stb_o => , +-- s1_wb_ack_i => , +-- s1_wb_err_i => , +-- s1_wb_dat_i => , +-- s1_wb_dat_o => , +-- s2_wb_adr_o => , +-- s2_wb_sel_o => , +-- s2_wb_we_o => , +-- s2_wb_cyc_o => , +-- s2_wb_stb_o => , +-- s2_wb_ack_i => , +-- s2_wb_err_i => , +-- s2_wb_dat_i => , +-- s2_wb_dat_o => +--); + end architecture ethernet_arch; -- 2.39.2