From ac5b827129ac002c0b2caa0d822868383c1416f2 Mon Sep 17 00:00:00 2001 From: michael Date: Wed, 21 Mar 2007 13:51:29 +0000 Subject: [PATCH] dcm --- ethernet/ethernet.prj | 1 + ethernet/ethernet.ucf | 15 ++++ ethernet/phydcm.xaw | 3 + ethernet/source/phydcm.vhd | 145 +++++++++++++++++++++++++++++++++++++ ethernet/source/top.vhd | 20 ++++- 5 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 ethernet/phydcm.xaw create mode 100644 ethernet/source/phydcm.vhd diff --git a/ethernet/ethernet.prj b/ethernet/ethernet.prj index 9086799..869bd18 100644 --- a/ethernet/ethernet.prj +++ b/ethernet/ethernet.prj @@ -85,3 +85,4 @@ verilog work "source/pci/pci_cbe_en_crit.v" verilog work "source/pci/pci_pci_decoder.v" verilog work "source/pci/pci_in_reg.v" vhdl work "source/top.vhd" +vhdl work "source/phydcm.vhd" diff --git a/ethernet/ethernet.ucf b/ethernet/ethernet.ucf index b62ae07..e64c929 100644 --- a/ethernet/ethernet.ucf +++ b/ethernet/ethernet.ucf @@ -77,3 +77,18 @@ NET "MDC_PAD_O" LOC = "U2" | IOSTANDARD = LVCMOS33; NET "PHY_CLOCK" LOC = "L5" | IOSTANDARD = LVCMOS33; NET "LED_2" LOC = "AB5" | IOSTANDARD = LVTTL | DRIVE = 24 ; + +INST DCM_INST CLK_FEEDBACK = 1X; +INST DCM_INST CLKDV_DIVIDE = 2.0; +INST DCM_INST CLKFX_DIVIDE = 29; +INST DCM_INST CLKFX_MULTIPLY = 22; +INST DCM_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_INST CLKIN_PERIOD = 30.303; +INST DCM_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_INST FACTORY_JF = 8080; +INST DCM_INST PHASE_SHIFT = 0; +INST DCM_INST STARTUP_WAIT = FALSE; diff --git a/ethernet/phydcm.xaw b/ethernet/phydcm.xaw new file mode 100644 index 0000000..262cfc5 --- /dev/null +++ b/ethernet/phydcm.xaw @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$9cx73=(`fgn#`glh`go+Wg`olnxxb`j/scdc`bt|fdn#hzgeslfp*bde'rj{<5?4:2-437<9;1:=55>6&j;4=6538R:7?:42/046>45:282:6=?.2206>54?23%=#>=i69BVFNPAS;<7L\XZ^MMH\YDIZIJHD@H_BNH5==FZ^PTCCBV_BNHMKYBP]OYBLB>5:CQS_YHFESTOAEFN^TBHPC6j2KY[WQ@NM[\@FKX[^C_OEGAG^AOO466:CQS_YHFESTHI\PFMKSBIIW9<1J^ZTPOONZ[CDXMQ^N^COC139BVR\XGGFRSD@\T^LVI`=FZ^PTCCBV_QO@@43GPRVIGGO[ITXRF540GPRVLGCZZVPD:8ER\XXHX_h6OXZ^QZJQNSGFF?7OA[H59AQCA33JF@<55LLJ2\FP@b3JF@8178GIM>8<1H@FJYc:AOOAPXL@\BHH;4CMIEF==DDBLISD@:;BNHB]>4CMIJJZOE]OMTEC][f:AOOLHXAK_MKRAZT99@HNOIW@Dh7NBDIO]SAWOHLl1H@FGA_RP@[Q_WM880OAE@UU]SLDUBWZBBJYm4CMI\B@CCJHI@56M@MLKWP@B03JXNMYKK3:F@I==CKDUBB^Zk;EGPO@QXIM@^_Y?=;EDP[CTBY\OEOTQBOEGb?AJKWHDOSKV>2:FOHZ@UMX_NBNWPMNFF1>BT[LD:96JZTX]@]FJBWJEY^HM[INL4?AYQIE_N46KWTDPMEIg@BMMHJOFQMUG;8BLHX]GC__l5IOTV\QKOS[h1MCXZPV@NVA4=N=2CIYKI7;HLWAWHFD8;0FDZ[ES]JJUSSW]S[In5EIUVFVZVL:YAh7GG[TDP\RDJRM?1GCLJJD79OKFMBLh1GCNEJD^MVP6=KG^90AETm;L]BJAYCWZ^Y;6CPV@NVA2=IM]]D^F:4NNLF5>I?3FLOH_M_Ec9SLDUBWZBBJY74PHLKEVDR[h1[ECG\GOFF@==WAG]BHYF7;QPJIQ_WM8:0\_A__QKMMVGD\@\N96^\CMI5?UUCGGO?7]]JN99SWLHDLLI87_][6:PPPZOIj2YBKHV[ESLBH3=TAGMGIn5\T@PWQUYPI@^=7^ZNTTQ26>U^[]OFS^WACIPLJJST;2^D\95[RTG;?PUBWK_MK45ZSD]AQCAT=2\BIZ?m;YCT[SCU[@EE=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB?6V\T79[`gYNl8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`:;Z294X3>hm1;03<3`|f1;1=6`72;68 =6=?l1v_9=5848;3?74::li=70_9=5848;3?74::li=7=1=9:88jo?521:5b>pS?j0;6<4>:`yP0176?>o1i;54?:187>d}#m32=7)?48f:&4`?b5;06?!712?<0(<95759'5=<43-;26;:4$0c915=#9k09?6*;2;48 7`=?2.8:7o4$259=>"4i3?;7)=i:c9'05<3m2.?=78;;%64>21<,=n1m6*;8;7e?!2f281/:?46;%44>4=#?<0><6*8a;5a?!762j1/=k4;9:&6f?4<,;1<7*9a;:0?!0d2>307d8i:18'2d5+6884=>=n>m0;6)8n:918 3?=?010e9l50;&5e?>43-<26:74;n06>5<#>h03?6*9c;5:?!7c2;>0(54o3c94?"1i32876a=e;29 3g=0:10c?l50;&5e?>432e9o7>5$7c9<6=30(=h=m0;6)8n:918 3e=?010c;k50;&5e?>432wi?n4?:383>5}#>k0>;6g:6;29 3g=0:1/:n489:9l20<72-0e8850;&5e?>43-5<#>h03?6*9c;5:?>{e;<0;6?4?:1y'2g<5<2c>:7>5$7c9<6=#>j0<565`6483>!0f2190(;m57898yv5e2909w0:9:2;896e=><1/=n45<6s4>=6:?4$61913=z{;<1<70>:6s|3583>7}:63<5;75?xu2m3:1=v3;6;7g?!142??0q~=j:18285d2<<0(:=5579~w6>=83;p1>;5649'36<1=2wx?i4?:1y'36<1=2wx>54?:1y'36<1=2wvb?950;3xyk4?290:wp`=9;295~{i:h0;6{|l1`?6=9rwe>h4?:0y~j7`=83;pqc=?:182x{zuIJHw>l5165;b5dfuIJIw=sO@Qy~DE \ No newline at end of file diff --git a/ethernet/source/phydcm.vhd b/ethernet/source/phydcm.vhd new file mode 100644 index 0000000..efec74a --- /dev/null +++ b/ethernet/source/phydcm.vhd @@ -0,0 +1,145 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 9.1.02i +-- \ \ Application : xaw2vhdl +-- / / Filename : phydcm.vhd +-- /___/ /\ Timestamp : 03/21/2007 14:47:39 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st phydcm.xaw phydcm +--Design Name: phydcm +--Device: xc3s1500-fg456-4 +-- +-- Module phydcm +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity phydcm is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end phydcm; + +architecture BEHAVIORAL of phydcm is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component IBUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI + -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns + component DCM + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"C080"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + DSS_MODE : string := "NONE"); + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + DSSEN : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + STATUS : out std_logic_vector (7 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_INST : DCM + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 29, + CLKFX_MULTIPLY => 22, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 30.303, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"8080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index 611e9c0..480de0a 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -171,6 +171,15 @@ port ( ); end component; +component phydcm is +port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end component; + signal pci_rst_o : std_logic; signal pci_rst_oe_o : std_logic; signal pci_inta_o : std_logic; @@ -258,7 +267,6 @@ wb_adr_i(11 downto 8) <= (others => '0'); wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2); wb_clk_i <= PCI_CLOCK; -PHY_CLOCK <= PCI_CLOCK; data(31 downto 0) <= wbm_adr_o; data(40 downto 33) <= wbm_adr_o (7 downto 0); @@ -394,4 +402,14 @@ port map ( trig0 => trig0 ); +eth_dcm : phydcm +port map ( + CLKIN_IN => PCI_CLOCK, + RST_IN => not PCI_RSTn, + CLKFX_OUT => PHY_CLOCK +-- CLKIN_IBUFG_OUT +-- CLK0_OUT +-- LOCKED_OUT + ); + end architecture ethernet_arch; -- 2.39.5