From c53499b10a5c0836953dc19d662088f2d789b7c3 Mon Sep 17 00:00:00 2001
From: sithglan <sithglan>
Date: Sun, 11 Feb 2007 22:11:04 +0000
Subject: [PATCH] += interface wb <=> fifo

---
 dhwk_old/source/wb_fifo.v | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 dhwk_old/source/wb_fifo.v

diff --git a/dhwk_old/source/wb_fifo.v b/dhwk_old/source/wb_fifo.v
new file mode 100644
index 0000000..5ffd1b1
--- /dev/null
+++ b/dhwk_old/source/wb_fifo.v
@@ -0,0 +1,37 @@
+module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, 
+	wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);
+
+	input clk_i;
+	input nrst_i;
+	input [24:1] wb_adr_i;
+	output [15:0] wb_dat_o;
+   	input [15:0] wb_dat_i;
+	input [1:0] wb_sel_i;
+   	input wb_we_i;
+	input wb_stb_i;
+	input wb_cyc_i;
+	output wb_ack_o;
+	output wb_err_o;
+	output wb_int_o;
+ 	input reg [7:0] fifo_data_i;
+ 	output reg [7:0] fifo_data_o;
+        output fifo_we_i;
+        output fifo_we_o;
+
+	reg [15:0]	data_reg;
+
+	always @(posedge clk_i or negedge nrst_i)
+	begin
+		if (nrst_i == 0)
+			data_reg <= 16'hABCD;
+		else 
+			if (wb_stb_i && wb_we_i)
+				data_reg <= wb_dat_i;
+	end
+
+	assign wb_ack_o = wb_stb_i;
+	assign wb_err_o = 1'b0;
+	assign wb_int_o = 1'b0;
+	assign wb_dat_o = data_reg;
+
+endmodule
-- 
2.39.2