From c8b3e197e6ec554806e722b220010e7c03830dea Mon Sep 17 00:00:00 2001 From: michael Date: Wed, 21 Mar 2007 11:25:11 +0000 Subject: [PATCH] chipscope --- ethernet/Makefile | 10 ++++ ethernet/icon.arg | 8 +++ ethernet/ila.arg | 16 ++++++ ethernet/source/top.vhd | 119 +++++++++++++--------------------------- 4 files changed, 72 insertions(+), 81 deletions(-) create mode 100644 ethernet/icon.arg create mode 100644 ethernet/ila.arg diff --git a/ethernet/Makefile b/ethernet/Makefile index d02d65d..1569b23 100644 --- a/ethernet/Makefile +++ b/ethernet/Makefile @@ -1,3 +1,13 @@ PROJECT := ethernet +ethernet_all: ip all + +ip: icon.edn ila.edn + +icon.edn: icon.arg + $(CHIPSCOPE)/bin/lin/generate.sh icon -f=$< + +ila.edn: ila.arg + $(CHIPSCOPE)/bin/lin/generate.sh ila -f=$< + include ../common/Makefile.common diff --git a/ethernet/icon.arg b/ethernet/icon.arg new file mode 100644 index 0000000..fc56ce1 --- /dev/null +++ b/ethernet/icon.arg @@ -0,0 +1,8 @@ +# +# Usage: generate.exe icon -f= +# +-compname=icon +-numports=1 +-devicefamily=Spartan3 +-bscanchain=1 +-outputdirectory=. diff --git a/ethernet/ila.arg b/ethernet/ila.arg new file mode 100644 index 0000000..ede5832 --- /dev/null +++ b/ethernet/ila.arg @@ -0,0 +1,16 @@ +# +# Usage: generate.exe ila -f= +# +-compname=ila +-outputdirectory=. +-datadepth=4096 +-datawidth=64 +-numtrigports=1 +-trigportwidth0=32 +-nummatchunits=1 +-mtrigport0=0 +-mtype0=0 +-enablestoragequal +-devicefamily=Spartan3 +-srl16type=2 +-createcdc diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd index 184e744..6530c18 100644 --- a/ethernet/source/top.vhd +++ b/ethernet/source/top.vhd @@ -154,48 +154,20 @@ PORT( ); END COMPONENT; -COMPONENT eth_cop -PORT( - wb_clk_i : IN std_logic; - wb_rst_i : IN std_logic; - m1_wb_adr_i : IN std_logic_vector(31 downto 0); - m1_wb_sel_i : IN std_logic_vector(3 downto 0); - m1_wb_we_i : IN std_logic; - m1_wb_dat_i : IN std_logic_vector(31 downto 0); - m1_wb_cyc_i : IN std_logic; - m1_wb_stb_i : IN std_logic; - m2_wb_adr_i : IN std_logic_vector(31 downto 0); - m2_wb_sel_i : IN std_logic_vector(3 downto 0); - m2_wb_we_i : IN std_logic; - m2_wb_dat_i : IN std_logic_vector(31 downto 0); - m2_wb_cyc_i : IN std_logic; - m2_wb_stb_i : IN std_logic; - s1_wb_ack_i : IN std_logic; - s1_wb_err_i : IN std_logic; - s1_wb_dat_i : IN std_logic_vector(31 downto 0); - s2_wb_ack_i : IN std_logic; - s2_wb_err_i : IN std_logic; - s2_wb_dat_i : IN std_logic_vector(31 downto 0); - m1_wb_dat_o : OUT std_logic_vector(31 downto 0); - m1_wb_ack_o : OUT std_logic; - m1_wb_err_o : OUT std_logic; - m2_wb_dat_o : OUT std_logic_vector(31 downto 0); - m2_wb_ack_o : OUT std_logic; - m2_wb_err_o : OUT std_logic; - s1_wb_adr_o : OUT std_logic_vector(31 downto 0); - s1_wb_sel_o : OUT std_logic_vector(3 downto 0); - s1_wb_we_o : OUT std_logic; - s1_wb_cyc_o : OUT std_logic; - s1_wb_stb_o : OUT std_logic; - s1_wb_dat_o : OUT std_logic_vector(31 downto 0); - s2_wb_adr_o : OUT std_logic_vector(31 downto 0); - s2_wb_sel_o : OUT std_logic_vector(3 downto 0); - s2_wb_we_o : OUT std_logic; - s2_wb_cyc_o : OUT std_logic; - s2_wb_stb_o : OUT std_logic; - s2_wb_dat_o : OUT std_logic_vector(31 downto 0) +component icon +port ( + control0 : out std_logic_vector(35 downto 0) ); -END COMPONENT; +end component; + +component ila +port ( + control : in std_logic_vector(35 downto 0); + clk : in std_logic; + data : in std_logic_vector(63 downto 0); + trig0 : in std_logic_vector(31 downto 0) + ); +end component; signal pci_rst_o : std_logic; signal pci_rst_oe_o : std_logic; @@ -252,6 +224,11 @@ signal wbm_adr_o : std_logic_vector(31 downto 0); signal m_wb_cti_o : std_logic_vector(2 downto 0); signal m_wb_bte_o : std_logic_vector(1 downto 0); +signal control0 : std_logic_vector(35 downto 0); +signal data : std_logic_vector(63 downto 0); +signal trig0 : std_logic_vector(31 downto 0); + + BEGIN PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z'; @@ -279,6 +256,14 @@ wb_adr_i <= wbm_adr_o (11 downto 2); wb_clk_i <= PCI_CLOCK; +data(31 downto 0) <= wbm_adr_o; +data(63 downto 32) <= (others => '0'); + +trig(31 downto 0) <= ( + 0 => wb_stb_i, + others => '0' +); + Inst_pci_bridge32: pci_bridge32 PORT MAP( wb_clk_i => wb_clk_i , wb_rst_i => '0', @@ -391,45 +376,17 @@ Inst_eth_top: eth_top PORT MAP( int_o => int_o ); ---Inst_eth_cop: eth_cop PORT MAP( --- wb_clk_i => , --- wb_rst_i => , --- m1_wb_adr_i => , --- m1_wb_sel_i => , --- m1_wb_we_i => , --- m1_wb_dat_o => , --- m1_wb_dat_i => , --- m1_wb_cyc_i => , --- m1_wb_stb_i => , --- m1_wb_ack_o => , --- m1_wb_err_o => , --- m2_wb_adr_i => , --- m2_wb_sel_i => , --- m2_wb_we_i => , --- m2_wb_dat_o => , --- m2_wb_dat_i => , --- m2_wb_cyc_i => , --- m2_wb_stb_i => , --- m2_wb_ack_o => , --- m2_wb_err_o => , --- s1_wb_adr_o => , --- s1_wb_sel_o => , --- s1_wb_we_o => , --- s1_wb_cyc_o => , --- s1_wb_stb_o => , --- s1_wb_ack_i => , --- s1_wb_err_i => , --- s1_wb_dat_i => , --- s1_wb_dat_o => , --- s2_wb_adr_o => , --- s2_wb_sel_o => , --- s2_wb_we_o => , --- s2_wb_cyc_o => , --- s2_wb_stb_o => , --- s2_wb_ack_i => , --- s2_wb_err_i => , --- s2_wb_dat_i => , --- s2_wb_dat_o => ---); +i_icon : icon +port map ( + control0 => control0 + ); + +i_ila : ila +port map ( + control => control0, + clk => PCI_CLOCK, + data => data, + trig0 => trig0 + ); end architecture ethernet_arch; -- 2.39.2