From ec7a129613549addc5b0dd7d52df29f1f6c082a1 Mon Sep 17 00:00:00 2001
From: michael <michael>
Date: Sun, 11 Feb 2007 22:28:24 +0000
Subject: [PATCH] -dpram component

---
 dhwk_old/source/top_dhwk.vhd | 38 ++++++++++--------------------------
 1 file changed, 10 insertions(+), 28 deletions(-)

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 67fe5aa..0e03a31 100644
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -109,34 +109,16 @@ port (
 );
 end component;
 
-component generic_dpram
-port (
-	rclk		: in std_logic;
-	rrst		: in std_logic;
-	rce		: in std_logic;
-	oe		: in std_logic;
-	raddr		: in std_logic_vector(11 downto 0);
-	do		: out std_logic_vector(7 downto 0);
-	wclk		: in std_logic;
-	wrst		: in std_logic;
-	wce		: in std_logic;
-	we		: in std_logic;
-	waddr		: in std_logic_vector(11 downto 0);
-	di		: in std_logic_vector(7 downto 0)
-);
-end component;
-
-
-	signal 	wb_adr :		std_logic_vector(24 downto 1);   
-	signal	wb_dat_out :	std_logic_vector(15 downto 0);
- 	signal 	wb_dat_in :		std_logic_vector(15 downto 0);
-	signal	wb_sel :		std_logic_vector(1 downto 0);
- 	signal  wb_we :			std_logic;
-	signal	wb_stb :		std_logic;
-	signal	wb_cyc :		std_logic;
-	signal	wb_ack :		std_logic;
-	signal	wb_err :		std_logic;
-	signal	wb_int :		std_logic;
+signal 	wb_adr :		std_logic_vector(24 downto 1);   
+signal	wb_dat_out :	std_logic_vector(15 downto 0);
+signal 	wb_dat_in :		std_logic_vector(15 downto 0);
+signal	wb_sel :		std_logic_vector(1 downto 0);
+signal  wb_we :			std_logic;
+signal	wb_stb :		std_logic;
+signal	wb_cyc :		std_logic;
+signal	wb_ack :		std_logic;
+signal	wb_err :		std_logic;
+signal	wb_int :		std_logic;
 
 
 begin
-- 
2.39.2