0232f7698b1ec5f8ed1364b3b39f801d98200ca5
[fpga-games] / galaxian / src / mc_top.v
1 //===============================================================================
2 // FPGA GALAXIAN TOP
3 //
4 // Version : 2.50
5 //
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
7 //
8 // Important !
9 //
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
13 //
14 // 2004- 4-30 galaxian modify by K.DEGAWA
15 // 2004- 5- 6 first release.
16 // 2004- 8-23 Improvement with T80-IP.
17 // 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.
18 // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
19 //================================================================================
20
21 `include "src/mc_conf.v"
22
23 module mc_top(
24
25 // FPGA_USE
26 I_CLK_125M,
27
28 `ifdef PSPAD_USE
29 // PS_PAD interface
30 psCLK,
31 psSEL,
32 psTXD,
33 psRXD,
34 `endif
35
36 // INPORT SW IF
37 I_PSW,
38
39 // SOUND OUT
40 O_SOUND_OUT_L,
41 O_SOUND_OUT_R,
42
43 // VGA (VIDEO) IF
44 O_VGA_R,
45 O_VGA_G,
46 O_VGA_B,
47 O_VGA_H_SYNCn,
48 O_VGA_V_SYNCn
49
50 );
51
52 // FPGA_USE
53 input I_CLK_125M;
54
55 // CPU ADDRESS BUS
56 wire [15:0]W_A;
57 // CPU IF
58 wire W_CPU_RDn;
59 wire W_CPU_WRn;
60 wire W_CPU_MREQn;
61 wire W_CPU_RFSHn;
62 wire W_CPU_BUSAKn;
63 wire W_CPU_IORQn;
64 wire W_CPU_M1n;
65 wire W_CPU_CLK;
66 wire W_CPU_HRDWR_RESETn;
67 wire W_CPU_WAITn;
68 wire W_CPU_NMIn;
69
70 `ifdef PSPAD_USE
71 // PS_PAD interface
72 input psRXD;
73 output psTXD,psCLK,psSEL;
74 `endif
75
76 // INPORT SW IF
77 input [8:0]I_PSW;
78
79 // SOUND OUT
80 output O_SOUND_OUT_L;
81 output O_SOUND_OUT_R;
82
83 // VGA (VIDEO) IF
84 output [3:0]O_VGA_R;
85 output [3:0]O_VGA_G;
86 output [3:0]O_VGA_B;
87 output O_VGA_H_SYNCn;
88 output O_VGA_V_SYNCn;
89
90 wire W_RESETn = |(~I_PSW[8:5]);
91 //------ CLOCK GEN ---------------------------
92 wire W_CLK_18M;
93 wire W_CLK_36M;
94 wire W_CLK_12M,WB_CLK_12M;
95 wire W_CLK_6M,WB_CLK_6M;
96 wire W_STARS_CLK;
97
98 mc_dcm clockgen(
99 .CLKIN_IN(I_CLK_125M),
100 .RST_IN(! W_RESETn),
101 .CLKFX_OUT(W_CLK_36M)
102 );
103
104 //------ H&V COUNTER -------------------------
105 wire [8:0]W_H_CNT;
106 wire [7:0]W_V_CNT;
107 wire W_H_BL;
108 wire W_V_BLn;
109 wire W_C_BLn;
110 wire W_H_SYNC;
111 wire W_V_SYNC;
112
113 //------ CPU RAM ----------------------------
114 wire [7:0]W_CPU_RAM_DO;
115
116 //------ ADDRESS DECDER ----------------------
117 wire W_CPU_ROM_CSn;
118 wire W_CPU_RAM_RDn;
119 wire W_CPU_RAM_WRn;
120 wire W_CPU_RAM_CSn;
121 wire W_OBJ_RAM_RDn;
122 wire W_OBJ_RAM_WRn;
123 wire W_OBJ_RAM_RQn;
124 wire W_VID_RAM_RDn;
125 wire W_VID_RAM_WRn;
126 wire W_SW0_OEn;
127 wire W_SW1_OEn;
128 wire W_DIP_OEn;
129 wire W_WDR_OEn;
130 wire W_LAMP_WEn;
131 wire W_SOUND_WEn;
132 wire W_PITCHn;
133 wire W_H_FLIP;
134 wire W_V_FLIP;
135 wire W_BD_G;
136 wire W_STARS_ON;
137
138 wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;
139 wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;
140 //------- INPORT -----------------------------
141 wire [7:0]W_SW_DO;
142 //------- VIDEO -----------------------------
143 wire [7:0]W_VID_DO;
144 //--------------------------------------------
145
146 mc_clock MC_CLK(
147
148 .I_CLK_36M(W_CLK_36M),
149 .O_CLK_18M(W_CLK_18M),
150 .O_CLK_12M(WB_CLK_12M),
151 .O_CLK_06M(WB_CLK_6M)
152
153 );
154
155 assign W_CLK_12M = WB_CLK_12M;
156 assign W_CLK_6M = WB_CLK_6M;
157 //--- DATA I/F -------------------------------------
158 reg [7:0]W_CPU_ROM_DO;
159 wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;
160
161 wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;
162 wire [7:0]W_BDI;
163
164 //--- CPU I/F -------------------------------------
165 reg [3:0]rst_count;
166 always@(posedge W_H_CNT[0] or negedge W_RESETn)
167 begin
168 if(! W_RESETn) rst_count <= 0;
169 else begin
170 if( rst_count == 15)
171 rst_count <= rst_count;
172 else
173 rst_count <= rst_count+1;
174 end
175 end
176
177 assign W_CPU_RESETn = W_RESETn;
178 assign W_CPU_CLK = W_H_CNT[0];
179
180 Z80IP CPU(
181
182 .CLK(W_CPU_CLK),
183 .RESET_N(W_CPU_RESETn),
184 .INT_N(1'b1),
185 .NMI_N(W_CPU_NMIn),
186 .ADRS(W_A),
187 .DOUT(W_BDI),
188 .DINP(W_BDO),
189 .M1_N(),
190 .MREQ_N(W_CPU_MREQn),
191 .IORQ_N(),
192 .RD_N(W_CPU_RDn ),
193 .WR_N(W_CPU_WRn ),
194 .WAIT_N(W_CPU_WAITn),
195 .BUSWO(),
196 .RFSH_N(W_CPU_RFSHn),
197 .HALT_N()
198
199 );
200
201 wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;
202
203 mc_cpu_ram MC_CPU_RAM(
204
205 .I_CLK(W_CPU_RAM_CLK),
206 .I_ADDR(W_A[9:0]),
207 .I_D(W_BDI),
208 .I_WE(~W_CPU_WRn),
209 .I_OE(~W_CPU_RAM_RDn ),
210 .O_D(W_CPU_RAM_DO)
211
212 );
213
214
215 mc_adec MC_ADEC(
216
217 .I_CLK_12M(W_CLK_12M),
218 .I_CLK_6M(W_CLK_6M),
219 .I_CPU_CLK(W_H_CNT[0]),
220 .I_RSTn(W_RESETn),
221
222 .I_CPU_A(W_A),
223 .I_CPU_D(W_BDI[0]),
224 .I_MREQn(W_CPU_MREQn),
225 .I_RFSHn(W_CPU_RFSHn),
226 .I_RDn(W_CPU_RDn),
227 .I_WRn(W_CPU_WRn),
228 .I_H_BL(W_H_BL),
229 .I_V_BLn(W_V_BLn),
230
231 .O_WAITn(W_CPU_WAITn),
232 .O_NMIn(W_CPU_NMIn),
233 .O_CPU_ROM_CSn(W_CPU_ROM_CSn),
234 .O_CPU_RAM_RDn(W_CPU_RAM_RDn),
235 .O_CPU_RAM_WRn(W_CPU_RAM_WRn),
236 .O_CPU_RAM_CSn(W_CPU_RAM_CSn),
237 .O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
238 .O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
239 .O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
240 .O_VID_RAM_RDn(W_VID_RAM_RDn),
241 .O_VID_RAM_WRn(W_VID_RAM_WRn),
242 .O_SW0_OEn(W_SW0_OEn),
243 .O_SW1_OEn(W_SW1_OEn),
244 .O_DIP_OEn(W_DIP_OEn),
245 .O_WDR_OEn(W_WDR_OEn),
246 .O_LAMP_WEn(W_LAMP_WEn),
247 .O_SOUND_WEn(W_SOUND_WEn),
248 .O_PITCHn(W_PITCHn),
249 .O_H_FLIP(W_H_FLIP),
250 .O_V_FLIP(W_V_FLIP),
251 .O_BD_G(W_BD_G),
252 .O_STARS_ON(W_STARS_ON)
253
254 );
255
256 //-------- SOUND I/F -----------------------------
257 //--- Parts 9L ---------
258 reg [7:0]W_9L_Q;
259 always@(posedge W_CLK_12M or negedge W_RESETn)
260 begin
261 if(W_RESETn == 1'b0)begin
262 W_9L_Q <= 0;
263 end
264 else begin
265 if(W_SOUND_WEn == 1'b0)begin
266 case(W_A[2:0])
267 3'h0 : W_9L_Q[0] <= W_BDI[0];
268 3'h1 : W_9L_Q[1] <= W_BDI[0];
269 3'h2 : W_9L_Q[2] <= W_BDI[0];
270 3'h3 : W_9L_Q[3] <= W_BDI[0];
271 3'h4 : W_9L_Q[4] <= W_BDI[0];
272 3'h5 : W_9L_Q[5] <= W_BDI[0];
273 3'h6 : W_9L_Q[6] <= W_BDI[0];
274 3'h7 : W_9L_Q[7] <= W_BDI[0];
275 endcase
276 end
277 end
278 end
279 wire W_VOL1 = W_9L_Q[6];
280 wire W_VOL2 = W_9L_Q[7];
281 wire W_FIRE = W_9L_Q[5];
282 wire W_HIT = W_9L_Q[3];
283 wire W_FS3 = W_9L_Q[2];
284 wire W_FS2 = W_9L_Q[1];
285 wire W_FS1 = W_9L_Q[0];
286 //---------------------------------------------------
287 //---- CPU DATA WATCH -------------------------------
288 wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;
289
290 reg [1:0]on_game;
291 always @(posedge W_CPU_CLK)
292 begin
293 if(~ZMWR)begin
294 if(W_A == 16'h4007)begin
295 if(W_BDI == 8'h00)
296 on_game[0] <= 1;
297 else
298 on_game[0] <= 0;
299 end
300 if(W_A == 16'h4005)begin
301 if(W_BDI == 8'h03 || W_BDI == 8'h04 )
302 on_game[1] <= 1;
303 else
304 on_game[1] <= 0;
305 end
306 end
307 end
308
309 `ifdef PSPAD_USE
310 reg died;
311 always @(posedge W_CPU_CLK)
312 begin
313 if(~ZMWR)begin
314 if(W_A == 16'h4206)begin
315 if(W_BDI == 8'h00)
316 died <= 0;
317 else
318 died <= 1;
319 end
320 end
321 end
322 //---- PS_PAD Interface -----------------------------
323 wire [8:0]ps_PSW;
324 wire VIB_SW = died & (&on_game[1:0]);
325
326 fpga_arcade_if pspad(
327
328 .CLK_18M432(W_CLK_18M),
329 .I_RSTn(W_RESETn),
330 .psCLK(psCLK),
331 .psSEL(psSEL),
332 .psTXD(psTXD),
333 .psRXD(psRXD),
334 .ps_PSW(ps_PSW),
335 .I_VIB_SW(VIB_SW)
336
337 );
338 `endif
339 //---- SW Interface ---------------------------------
340 `ifdef PSPAD_USE
341 wire L1 = I_PSW[2] & ps_PSW[2];
342 wire R1 = I_PSW[3] & ps_PSW[3];
343 wire U1 = I_PSW[0];
344 wire D1 = I_PSW[1];
345 wire J1 = I_PSW[4] & ps_PSW[8];
346
347 wire S1 = (U1|J1) & ps_PSW[6];
348 wire S2 = (D1|J1) & ps_PSW[7];
349
350 wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];
351 `else
352 wire L1 = ! I_PSW[2];
353 wire R1 = ! I_PSW[3];
354 wire U1 = ! I_PSW[0];
355 wire D1 = ! I_PSW[1];
356 wire J1 = ! I_PSW[4];
357
358 wire S1 = ! I_PSW[5];
359 wire S2 = ! I_PSW[7];
360
361 wire C1 = ! I_PSW[6];
362 `endif
363 wire C2 = ! I_PSW[8];
364
365 wire L2 = L1;
366 wire R2 = R1;
367 wire U2 = U1;
368 wire D2 = D1;
369 wire J2 = J1;
370
371 mc_inport MC_INPORT(
372
373 .I_COIN1(~C1), // ACTIVE HI
374 .I_COIN2(~C2), // ACTIVE HI
375 .I_1P_LE(~L1), // ACTIVE HI
376 .I_1P_RI(~R1), // ACTIVE HI
377 .I_1P_SH(~J1), // ACTIVE HI
378 .I_2P_LE(~L2), // ACTIVE HI
379 .I_2P_RI(~R2), // ACTIVE HI
380 .I_2P_SH(~J2), // ACTIVE HI
381 .I_1P_START(~S1), // ACTIVE HI
382 .I_2P_START(~S2), // ACTIVE HI
383
384 .I_SW0_OEn(W_SW0_OEn),
385 .I_SW1_OEn(W_SW1_OEn),
386 .I_DIP_OEn(W_DIP_OEn),
387
388 .O_D(W_SW_DO)
389
390 );
391
392 //-----------------------------------------------------------------------------
393 //------- ROM -------------------------------------------------------
394 reg [18:0]ROM_A;
395
396 wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;
397 reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;
398
399 wire [7:0]ROM_D;
400
401 galaxian_roms ROMS(
402 .I_ROM_CLK(W_CLK_12M),
403 .I_ADDR({3'h0,W_A[15:0]}),
404 .O_DATA(ROM_D)
405 );
406
407 always@(posedge W_CLK_12M)
408 begin
409 W_CPU_ROM_DO <= ROM_D;
410 end
411
412 //-----------------------------------------------------------------------------
413
414 wire W_V_BL2n;
415
416 mc_hv_count MC_HV(
417
418 .I_CLK(WB_CLK_6M),
419 .I_RSTn(W_RESETn),
420
421 .O_H_CNT(W_H_CNT),
422 .O_H_SYNC(W_H_SYNC),
423 .O_H_BL(W_H_BL),
424 .O_V_CNT(W_V_CNT),
425 .O_V_SYNC(W_V_SYNC),
426 .O_V_BL2n(W_V_BL2n),
427 .O_V_BLn(W_V_BLn),
428 .O_C_BLn(W_C_BLn)
429
430 );
431
432 //------ VIDEO -----------------------------
433 wire W_8HF;
434 wire W_1VF;
435 wire W_C_BLnX;
436 wire W_256HnX;
437 wire W_MISSILEn;
438 wire W_SHELLn;
439 wire [1:0]W_VID;
440 wire [2:0]W_COL;
441
442 mc_video MC_VID(
443 .I_CLK_18M(W_CLK_18M),
444 .I_CLK_12M(W_CLK_12M),
445 .I_CLK_6M(W_CLK_6M),
446 .I_H_CNT(W_H_CNT),
447 .I_V_CNT(W_V_CNT),
448 .I_H_FLIP(W_H_FLIP),
449 .I_V_FLIP(W_V_FLIP),
450 .I_V_BLn(W_V_BLn),
451 .I_C_BLn(W_C_BLn),
452
453 .I_A(W_A[9:0]),
454 .I_OBJ_SUB_A(3'b000),
455 .I_BD(W_BDI),
456 .I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
457 .I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
458 .I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
459 .I_VID_RAM_RDn(W_VID_RAM_RDn),
460 .I_VID_RAM_WRn(W_VID_RAM_WRn),
461
462 .O_C_BLnX(W_C_BLnX),
463 .O_8HF(W_8HF),
464 .O_256HnX(W_256HnX),
465 .O_1VF(W_1VF),
466 .O_MISSILEn(W_MISSILEn),
467 .O_SHELLn(W_SHELLn),
468 .O_BD(W_VID_DO),
469 .O_VID(W_VID),
470 .O_COL(W_COL)
471
472 );
473
474 wire W_C_BLX;
475 wire W_STARS_OFFn;
476 wire [2:0]W_VIDEO_R;
477 wire [2:0]W_VIDEO_G;
478 wire [1:0]W_VIDEO_B;
479
480 mc_col_pal MC_COL_PAL(
481
482 .I_CLK_12M(W_CLK_12M),
483 .I_CLK_6M(W_CLK_6M),
484 .I_VID(W_VID),
485 .I_COL(W_COL),
486 .I_C_BLnX(W_C_BLnX),
487
488 .O_C_BLX(W_C_BLX),
489 .O_STARS_OFFn(W_STARS_OFFn),
490 .O_R(W_VIDEO_R),
491 .O_G(W_VIDEO_G),
492 .O_B(W_VIDEO_B)
493
494 );
495
496 wire [2:0]W_STARS_R;
497 wire [2:0]W_STARS_G;
498 wire [1:0]W_STARS_B;
499
500 mc_stars MC_STARS(
501
502 .I_CLK_18M(W_CLK_18M),
503 `ifdef DEVICE_CYCLONE
504 .I_CLK_6M(~WB_CLK_6M),
505 `endif
506 `ifdef DEVICE_SPARTAN2E
507 .I_CLK_6M(WB_CLK_6M),
508 `endif
509 .I_H_FLIP(W_H_FLIP),
510 .I_V_SYNC(W_V_SYNC),
511 .I_8HF(W_8HF),
512 .I_256HnX(W_256HnX),
513 .I_1VF(W_1VF),
514 .I_2V(W_V_CNT[1]),
515 .I_STARS_ON(W_STARS_ON),
516 .I_STARS_OFFn(W_STARS_OFFn),
517
518 .O_R(W_STARS_R),
519 .O_G(W_STARS_G),
520 .O_B(W_STARS_B),
521 .O_NOISE()
522
523 );
524
525 wire [2:0]W_R;
526 wire [2:0]W_G;
527 wire [1:0]W_B;
528
529 mc_vedio_mix MIX(
530
531 .I_VID_R(W_VIDEO_R),
532 .I_VID_G(W_VIDEO_G),
533 .I_VID_B(W_VIDEO_B),
534 .I_STR_R(W_STARS_R),
535 .I_STR_G(W_STARS_G),
536 .I_STR_B(W_STARS_B),
537
538 .I_C_BLnXX(~W_C_BLX),
539 .I_C_BLX(W_C_BLX | ~W_V_BL2n),
540 .I_MISSILEn(W_MISSILEn),
541 .I_SHELLn(W_SHELLn),
542
543 .O_R(W_R),
544 .O_G(W_G),
545 .O_B(W_B)
546
547 );
548
549 wire [2:0]W_VGA_R;
550 wire [2:0]W_VGA_G;
551 wire [1:0]W_VGA_B;
552
553 `ifdef VGA_USE
554 mc_vga_if VGA(
555
556 // input
557 .I_CLK_1(W_CLK_6M),
558 .I_CLK_2(W_CLK_12M),
559 .I_R(W_R),
560 .I_G(W_G),
561 .I_B(W_B),
562 .I_H_SYNC(W_H_SYNC),
563 .I_V_SYNC(W_V_SYNC),
564 // output
565 .O_R(W_VGA_R),
566 .O_G(W_VGA_G),
567 .O_B(W_VGA_B),
568 .O_H_SYNCn(O_VGA_H_SYNCn),
569 .O_V_SYNCn(O_VGA_V_SYNCn)
570
571 );
572
573 `else
574
575 assign W_VGA_R[2:0] = W_R;
576
577 assign W_VGA_G[2:0] = W_G;
578
579 assign W_VGA_B[1:0] = W_B;
580
581 //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED
582 assign O_VGA_H_SYNCn = ~W_H_SYNC ;
583 assign O_VGA_V_SYNCn = ~W_V_SYNC ;
584
585 `endif
586
587 assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};
588
589 assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};
590
591 assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};
592
593 wire [7:0]W_SDAT_A;
594
595 mc_sound_a MC_SOUND_A(
596
597 .I_CLK_12M(W_CLK_12M),
598 .I_CLK_6M(W_CLK_6M),
599 .I_H_CNT1(W_H_CNT[1]),
600 .I_BD(W_BDI),
601 .I_PITCHn(W_PITCHn),
602 .I_VOL1(W_VOL1),
603 .I_VOL2(W_VOL2),
604
605 .O_SDAT(W_SDAT_A),
606 .O_DO()
607
608 );
609
610 wire [7:0]W_SDAT_B;
611
612 mc_sound_b MC_SOUND_B(
613
614 .I_CLK1(W_CLK_18M),
615 .I_CLK2(W_CLK_6M),
616 .I_RSTn(rst_count[3]),
617 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),
618
619 .O_WAV_A0(W_WAV_A0),
620 .O_WAV_A1(W_WAV_A1),
621 .O_WAV_A2(W_WAV_A2),
622 .I_WAV_D0(W_WAV_D0),
623 .I_WAV_D1(W_WAV_D1),
624 .I_WAV_D2(W_WAV_D2),
625
626 .O_SDAT(W_SDAT_B)
627
628 );
629
630 wire W_DAC_A;
631 wire W_DAC_B;
632
633 assign O_SOUND_OUT_L = W_DAC_A;
634 assign O_SOUND_OUT_R = W_DAC_B;
635
636 dac wav_dac_a(
637
638 .Clk(W_CLK_18M),
639 .Reset(~W_RESETn),
640 .DACin(W_SDAT_A),
641 .DACout(W_DAC_A)
642
643 );
644
645 dac wav_dac_b(
646
647 .Clk(W_CLK_18M),
648 .Reset(~W_RESETn),
649 .DACin(W_SDAT_B),
650 .DACout(W_DAC_B)
651
652 );
653
654
655 endmodule
656
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