cleanup rom usage
[fpga-games] / galaxian / src / mc_top.v
1 //===============================================================================
2 // FPGA GALAXIAN TOP
3 //
4 // Version : 2.50
5 //
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
7 //
8 // Important !
9 //
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
13 //
14 // 2004- 4-30 galaxian modify by K.DEGAWA
15 // 2004- 5- 6 first release.
16 // 2004- 8-23 Improvement with T80-IP.
17 // 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.
18 // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
19 //================================================================================
20
21 `include "src/mc_conf.v"
22
23 module mc_top(
24
25 // FPGA_USE
26 I_CLK_125M,
27
28 `ifdef PSPAD_USE
29 // PS_PAD interface
30 psCLK,
31 psSEL,
32 psTXD,
33 psRXD,
34 `endif
35
36 // INPORT SW IF
37 I_PSW,
38
39 // SOUND OUT
40 O_SOUND_OUT_L,
41 O_SOUND_OUT_R,
42
43 // VGA (VIDEO) IF
44 O_VGA_R,
45 O_VGA_G,
46 O_VGA_B,
47 O_VGA_H_SYNCn,
48 O_VGA_V_SYNCn
49
50 );
51
52 // FPGA_USE
53 input I_CLK_125M;
54
55 // CPU ADDRESS BUS
56 wire [15:0]W_A;
57 // CPU IF
58 wire W_CPU_RDn;
59 wire W_CPU_WRn;
60 wire W_CPU_MREQn;
61 wire W_CPU_RFSHn;
62 wire W_CPU_BUSAKn;
63 wire W_CPU_IORQn;
64 wire W_CPU_M1n;
65 wire W_CPU_CLK;
66 wire W_CPU_HRDWR_RESETn;
67 wire W_CPU_WAITn;
68 wire W_CPU_NMIn;
69
70 `ifdef PSPAD_USE
71 // PS_PAD interface
72 input psRXD;
73 output psTXD,psCLK,psSEL;
74 `endif
75
76 // INPORT SW IF
77 input [8:0]I_PSW;
78
79 // SOUND OUT
80 output O_SOUND_OUT_L;
81 output O_SOUND_OUT_R;
82
83 // VGA (VIDEO) IF
84 output [3:0]O_VGA_R;
85 output [3:0]O_VGA_G;
86 output [3:0]O_VGA_B;
87 output O_VGA_H_SYNCn;
88 output O_VGA_V_SYNCn;
89
90 wire W_RESETn = |(~I_PSW[8:5]);
91 //------ CLOCK GEN ---------------------------
92 wire I_CLK_18432M;
93 wire W_CLK_12M,WB_CLK_12M;
94 wire W_CLK_6M,WB_CLK_6M;
95 wire W_STARS_CLK;
96
97 mc_dcm clockgen(
98 .CLKIN_IN(I_CLK_125M),
99 .RST_IN(! W_RESETn),
100 .CLKFX_OUT(I_CLK_18432M)
101 );
102
103 //------ H&V COUNTER -------------------------
104 wire [8:0]W_H_CNT;
105 wire [7:0]W_V_CNT;
106 wire W_H_BL;
107 wire W_V_BLn;
108 wire W_C_BLn;
109 wire W_H_SYNC;
110 wire W_V_SYNC;
111
112 //------ CPU RAM ----------------------------
113 wire [7:0]W_CPU_RAM_DO;
114
115 //------ ADDRESS DECDER ----------------------
116 wire W_CPU_ROM_CSn;
117 wire W_CPU_RAM_RDn;
118 wire W_CPU_RAM_WRn;
119 wire W_CPU_RAM_CSn;
120 wire W_OBJ_RAM_RDn;
121 wire W_OBJ_RAM_WRn;
122 wire W_OBJ_RAM_RQn;
123 wire W_VID_RAM_RDn;
124 wire W_VID_RAM_WRn;
125 wire W_SW0_OEn;
126 wire W_SW1_OEn;
127 wire W_DIP_OEn;
128 wire W_WDR_OEn;
129 wire W_LAMP_WEn;
130 wire W_SOUND_WEn;
131 wire W_PITCHn;
132 wire W_H_FLIP;
133 wire W_V_FLIP;
134 wire W_BD_G;
135 wire W_STARS_ON;
136
137 wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;
138 wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;
139 //------- INPORT -----------------------------
140 wire [7:0]W_SW_DO;
141 //------- VIDEO -----------------------------
142 wire [7:0]W_VID_DO;
143 //--------------------------------------------
144
145 mc_clock MC_CLK(
146
147 .I_CLK_18M(I_CLK_18432M),
148 .O_CLK_12M(WB_CLK_12M),
149 .O_CLK_06M(WB_CLK_6M)
150
151 );
152
153 `ifdef DEVICE_CYCLONE
154 assign W_CLK_12M = WB_CLK_12M;
155 assign W_CLK_6M = WB_CLK_6M;
156 `endif
157 `ifdef DEVICE_SPARTAN2E
158 BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );
159 BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );
160 `endif
161 //--- DATA I/F -------------------------------------
162 reg [7:0]W_CPU_ROM_DO;
163 wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;
164
165 wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;
166 wire [7:0]W_BDI;
167
168 //--- CPU I/F -------------------------------------
169 reg [3:0]rst_count;
170 always@(posedge W_H_CNT[0] or negedge W_RESETn)
171 begin
172 if(! W_RESETn) rst_count <= 0;
173 else begin
174 if( rst_count == 15)
175 rst_count <= rst_count;
176 else
177 rst_count <= rst_count+1;
178 end
179 end
180
181 assign W_CPU_RESETn = W_RESETn;
182 assign W_CPU_CLK = W_H_CNT[0];
183
184 Z80IP CPU(
185
186 .CLK(W_CPU_CLK),
187 .RESET_N(W_CPU_RESETn),
188 .INT_N(1'b1),
189 .NMI_N(W_CPU_NMIn),
190 .ADRS(W_A),
191 .DOUT(W_BDI),
192 .DINP(W_BDO),
193 .M1_N(),
194 .MREQ_N(W_CPU_MREQn),
195 .IORQ_N(),
196 .RD_N(W_CPU_RDn ),
197 .WR_N(W_CPU_WRn ),
198 .WAIT_N(W_CPU_WAITn),
199 .BUSWO(),
200 .RFSH_N(W_CPU_RFSHn),
201 .HALT_N()
202
203 );
204
205 wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;
206
207 mc_cpu_ram MC_CPU_RAM(
208
209 .I_CLK(W_CPU_RAM_CLK),
210 .I_ADDR(W_A[9:0]),
211 .I_D(W_BDI),
212 .I_WE(~W_CPU_WRn),
213 .I_OE(~W_CPU_RAM_RDn ),
214 .O_D(W_CPU_RAM_DO)
215
216 );
217
218
219 mc_adec MC_ADEC(
220
221 .I_CLK_12M(W_CLK_12M),
222 .I_CLK_6M(W_CLK_6M),
223 .I_CPU_CLK(W_H_CNT[0]),
224 .I_RSTn(W_RESETn),
225
226 .I_CPU_A(W_A),
227 .I_CPU_D(W_BDI[0]),
228 .I_MREQn(W_CPU_MREQn),
229 .I_RFSHn(W_CPU_RFSHn),
230 .I_RDn(W_CPU_RDn),
231 .I_WRn(W_CPU_WRn),
232 .I_H_BL(W_H_BL),
233 .I_V_BLn(W_V_BLn),
234
235 .O_WAITn(W_CPU_WAITn),
236 .O_NMIn(W_CPU_NMIn),
237 .O_CPU_ROM_CSn(W_CPU_ROM_CSn),
238 .O_CPU_RAM_RDn(W_CPU_RAM_RDn),
239 .O_CPU_RAM_WRn(W_CPU_RAM_WRn),
240 .O_CPU_RAM_CSn(W_CPU_RAM_CSn),
241 .O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
242 .O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
243 .O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
244 .O_VID_RAM_RDn(W_VID_RAM_RDn),
245 .O_VID_RAM_WRn(W_VID_RAM_WRn),
246 .O_SW0_OEn(W_SW0_OEn),
247 .O_SW1_OEn(W_SW1_OEn),
248 .O_DIP_OEn(W_DIP_OEn),
249 .O_WDR_OEn(W_WDR_OEn),
250 .O_LAMP_WEn(W_LAMP_WEn),
251 .O_SOUND_WEn(W_SOUND_WEn),
252 .O_PITCHn(W_PITCHn),
253 .O_H_FLIP(W_H_FLIP),
254 .O_V_FLIP(W_V_FLIP),
255 .O_BD_G(W_BD_G),
256 .O_STARS_ON(W_STARS_ON)
257
258 );
259
260 //-------- SOUND I/F -----------------------------
261 //--- Parts 9L ---------
262 reg [7:0]W_9L_Q;
263 always@(posedge W_CLK_12M or negedge W_RESETn)
264 begin
265 if(W_RESETn == 1'b0)begin
266 W_9L_Q <= 0;
267 end
268 else begin
269 if(W_SOUND_WEn == 1'b0)begin
270 case(W_A[2:0])
271 3'h0 : W_9L_Q[0] <= W_BDI[0];
272 3'h1 : W_9L_Q[1] <= W_BDI[0];
273 3'h2 : W_9L_Q[2] <= W_BDI[0];
274 3'h3 : W_9L_Q[3] <= W_BDI[0];
275 3'h4 : W_9L_Q[4] <= W_BDI[0];
276 3'h5 : W_9L_Q[5] <= W_BDI[0];
277 3'h6 : W_9L_Q[6] <= W_BDI[0];
278 3'h7 : W_9L_Q[7] <= W_BDI[0];
279 endcase
280 end
281 end
282 end
283 wire W_VOL1 = W_9L_Q[6];
284 wire W_VOL2 = W_9L_Q[7];
285 wire W_FIRE = W_9L_Q[5];
286 wire W_HIT = W_9L_Q[3];
287 wire W_FS3 = W_9L_Q[2];
288 wire W_FS2 = W_9L_Q[1];
289 wire W_FS1 = W_9L_Q[0];
290 //---------------------------------------------------
291 //---- CPU DATA WATCH -------------------------------
292 wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;
293
294 reg [1:0]on_game;
295 always @(posedge W_CPU_CLK)
296 begin
297 if(~ZMWR)begin
298 if(W_A == 16'h4007)begin
299 if(W_BDI == 8'h00)
300 on_game[0] <= 1;
301 else
302 on_game[0] <= 0;
303 end
304 if(W_A == 16'h4005)begin
305 if(W_BDI == 8'h03 || W_BDI == 8'h04 )
306 on_game[1] <= 1;
307 else
308 on_game[1] <= 0;
309 end
310 end
311 end
312
313 `ifdef PSPAD_USE
314 reg died;
315 always @(posedge W_CPU_CLK)
316 begin
317 if(~ZMWR)begin
318 if(W_A == 16'h4206)begin
319 if(W_BDI == 8'h00)
320 died <= 0;
321 else
322 died <= 1;
323 end
324 end
325 end
326 //---- PS_PAD Interface -----------------------------
327 wire [8:0]ps_PSW;
328 wire VIB_SW = died & (&on_game[1:0]);
329
330 fpga_arcade_if pspad(
331
332 .CLK_18M432(I_CLK_18432M),
333 .I_RSTn(W_RESETn),
334 .psCLK(psCLK),
335 .psSEL(psSEL),
336 .psTXD(psTXD),
337 .psRXD(psRXD),
338 .ps_PSW(ps_PSW),
339 .I_VIB_SW(VIB_SW)
340
341 );
342 `endif
343 //---- SW Interface ---------------------------------
344 `ifdef PSPAD_USE
345 wire L1 = I_PSW[2] & ps_PSW[2];
346 wire R1 = I_PSW[3] & ps_PSW[3];
347 wire U1 = I_PSW[0];
348 wire D1 = I_PSW[1];
349 wire J1 = I_PSW[4] & ps_PSW[8];
350
351 wire S1 = (U1|J1) & ps_PSW[6];
352 wire S2 = (D1|J1) & ps_PSW[7];
353
354 wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];
355 `else
356 wire L1 = ! I_PSW[2];
357 wire R1 = ! I_PSW[3];
358 wire U1 = ! I_PSW[0];
359 wire D1 = ! I_PSW[1];
360 wire J1 = ! I_PSW[4];
361
362 wire S1 = ! I_PSW[5];
363 wire S2 = ! I_PSW[7];
364
365 wire C1 = ! I_PSW[6];
366 `endif
367 wire C2 = ! I_PSW[8];
368
369 wire L2 = L1;
370 wire R2 = R1;
371 wire U2 = U1;
372 wire D2 = D1;
373 wire J2 = J1;
374
375 mc_inport MC_INPORT(
376
377 .I_COIN1(~C1), // ACTIVE HI
378 .I_COIN2(~C2), // ACTIVE HI
379 .I_1P_LE(~L1), // ACTIVE HI
380 .I_1P_RI(~R1), // ACTIVE HI
381 .I_1P_SH(~J1), // ACTIVE HI
382 .I_2P_LE(~L2), // ACTIVE HI
383 .I_2P_RI(~R2), // ACTIVE HI
384 .I_2P_SH(~J2), // ACTIVE HI
385 .I_1P_START(~S1), // ACTIVE HI
386 .I_2P_START(~S2), // ACTIVE HI
387
388 .I_SW0_OEn(W_SW0_OEn),
389 .I_SW1_OEn(W_SW1_OEn),
390 .I_DIP_OEn(W_DIP_OEn),
391
392 .O_D(W_SW_DO)
393
394 );
395
396 //-----------------------------------------------------------------------------
397 //------- ROM -------------------------------------------------------
398 reg [18:0]ROM_A;
399
400 wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;
401 reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;
402
403 wire [7:0]ROM_D;
404
405 galaxian_roms ROMS(
406 .I_ROM_CLK(W_CLK_12M),
407 .I_ADDR({3'h0,W_A[15:0]}),
408 .O_DATA(ROM_D)
409 );
410
411 always@(posedge W_CLK_12M)
412 begin
413 W_CPU_ROM_DO <= ROM_D;
414 end
415
416 //-----------------------------------------------------------------------------
417
418 wire W_V_BL2n;
419
420 mc_hv_count MC_HV(
421
422 .I_CLK(WB_CLK_6M),
423 .I_RSTn(W_RESETn),
424
425 .O_H_CNT(W_H_CNT),
426 .O_H_SYNC(W_H_SYNC),
427 .O_H_BL(W_H_BL),
428 .O_V_CNT(W_V_CNT),
429 .O_V_SYNC(W_V_SYNC),
430 .O_V_BL2n(W_V_BL2n),
431 .O_V_BLn(W_V_BLn),
432 .O_C_BLn(W_C_BLn)
433
434 );
435
436 //------ VIDEO -----------------------------
437 wire W_8HF;
438 wire W_1VF;
439 wire W_C_BLnX;
440 wire W_256HnX;
441 wire W_MISSILEn;
442 wire W_SHELLn;
443 wire [1:0]W_VID;
444 wire [2:0]W_COL;
445
446 mc_video MC_VID(
447 .I_CLK_18M(I_CLK_18432M),
448 .I_CLK_12M(W_CLK_12M),
449 .I_CLK_6M(W_CLK_6M),
450 .I_H_CNT(W_H_CNT),
451 .I_V_CNT(W_V_CNT),
452 .I_H_FLIP(W_H_FLIP),
453 .I_V_FLIP(W_V_FLIP),
454 .I_V_BLn(W_V_BLn),
455 .I_C_BLn(W_C_BLn),
456
457 .I_A(W_A[9:0]),
458 .I_OBJ_SUB_A(3'b000),
459 .I_BD(W_BDI),
460 .I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
461 .I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
462 .I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
463 .I_VID_RAM_RDn(W_VID_RAM_RDn),
464 .I_VID_RAM_WRn(W_VID_RAM_WRn),
465
466 .O_C_BLnX(W_C_BLnX),
467 .O_8HF(W_8HF),
468 .O_256HnX(W_256HnX),
469 .O_1VF(W_1VF),
470 .O_MISSILEn(W_MISSILEn),
471 .O_SHELLn(W_SHELLn),
472 .O_BD(W_VID_DO),
473 .O_VID(W_VID),
474 .O_COL(W_COL)
475
476 );
477
478 wire W_C_BLX;
479 wire W_STARS_OFFn;
480 wire [2:0]W_VIDEO_R;
481 wire [2:0]W_VIDEO_G;
482 wire [1:0]W_VIDEO_B;
483
484 mc_col_pal MC_COL_PAL(
485
486 .I_CLK_12M(W_CLK_12M),
487 .I_CLK_6M(W_CLK_6M),
488 .I_VID(W_VID),
489 .I_COL(W_COL),
490 .I_C_BLnX(W_C_BLnX),
491
492 .O_C_BLX(W_C_BLX),
493 .O_STARS_OFFn(W_STARS_OFFn),
494 .O_R(W_VIDEO_R),
495 .O_G(W_VIDEO_G),
496 .O_B(W_VIDEO_B)
497
498 );
499
500 wire [2:0]W_STARS_R;
501 wire [2:0]W_STARS_G;
502 wire [1:0]W_STARS_B;
503
504 mc_stars MC_STARS(
505
506 .I_CLK_18M(I_CLK_18432M),
507 `ifdef DEVICE_CYCLONE
508 .I_CLK_6M(~WB_CLK_6M),
509 `endif
510 `ifdef DEVICE_SPARTAN2E
511 .I_CLK_6M(WB_CLK_6M),
512 `endif
513 .I_H_FLIP(W_H_FLIP),
514 .I_V_SYNC(W_V_SYNC),
515 .I_8HF(W_8HF),
516 .I_256HnX(W_256HnX),
517 .I_1VF(W_1VF),
518 .I_2V(W_V_CNT[1]),
519 .I_STARS_ON(W_STARS_ON),
520 .I_STARS_OFFn(W_STARS_OFFn),
521
522 .O_R(W_STARS_R),
523 .O_G(W_STARS_G),
524 .O_B(W_STARS_B),
525 .O_NOISE()
526
527 );
528
529 wire [2:0]W_R;
530 wire [2:0]W_G;
531 wire [1:0]W_B;
532
533 mc_vedio_mix MIX(
534
535 .I_VID_R(W_VIDEO_R),
536 .I_VID_G(W_VIDEO_G),
537 .I_VID_B(W_VIDEO_B),
538 .I_STR_R(W_STARS_R),
539 .I_STR_G(W_STARS_G),
540 .I_STR_B(W_STARS_B),
541
542 .I_C_BLnXX(~W_C_BLX),
543 .I_C_BLX(W_C_BLX | ~W_V_BL2n),
544 .I_MISSILEn(W_MISSILEn),
545 .I_SHELLn(W_SHELLn),
546
547 .O_R(W_R),
548 .O_G(W_G),
549 .O_B(W_B)
550
551 );
552
553 wire [2:0]W_VGA_R;
554 wire [2:0]W_VGA_G;
555 wire [1:0]W_VGA_B;
556
557 `ifdef VGA_USE
558 mc_vga_if VGA(
559
560 // input
561 .I_CLK_1(W_CLK_6M),
562 .I_CLK_2(W_CLK_12M),
563 .I_R(W_R),
564 .I_G(W_G),
565 .I_B(W_B),
566 .I_H_SYNC(W_H_SYNC),
567 .I_V_SYNC(W_V_SYNC),
568 // output
569 .O_R(W_VGA_R),
570 .O_G(W_VGA_G),
571 .O_B(W_VGA_B),
572 .O_H_SYNCn(O_VGA_H_SYNCn),
573 .O_V_SYNCn(O_VGA_V_SYNCn)
574
575 );
576
577 `else
578
579 assign W_VGA_R[2:0] = W_R;
580
581 assign W_VGA_G[2:0] = W_G;
582
583 assign W_VGA_B[1:0] = W_B;
584
585 //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED
586 assign O_VGA_H_SYNCn = ~W_H_SYNC ;
587 assign O_VGA_V_SYNCn = ~W_V_SYNC ;
588
589 `endif
590
591 assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};
592
593 assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};
594
595 assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};
596
597 wire [7:0]W_SDAT_A;
598
599 mc_sound_a MC_SOUND_A(
600
601 .I_CLK_12M(W_CLK_12M),
602 .I_CLK_6M(W_CLK_6M),
603 .I_H_CNT1(W_H_CNT[1]),
604 .I_BD(W_BDI),
605 .I_PITCHn(W_PITCHn),
606 .I_VOL1(W_VOL1),
607 .I_VOL2(W_VOL2),
608
609 .O_SDAT(W_SDAT_A),
610 .O_DO()
611
612 );
613
614 wire [7:0]W_SDAT_B;
615
616 mc_sound_b MC_SOUND_B(
617
618 .I_CLK1(I_CLK_18432M),
619 .I_CLK2(W_CLK_6M),
620 .I_RSTn(rst_count[3]),
621 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),
622
623 .O_WAV_A0(W_WAV_A0),
624 .O_WAV_A1(W_WAV_A1),
625 .O_WAV_A2(W_WAV_A2),
626 .I_WAV_D0(W_WAV_D0),
627 .I_WAV_D1(W_WAV_D1),
628 .I_WAV_D2(W_WAV_D2),
629
630 .O_SDAT(W_SDAT_B)
631
632 );
633
634 wire W_DAC_A;
635 wire W_DAC_B;
636
637 assign O_SOUND_OUT_L = W_DAC_A;
638 assign O_SOUND_OUT_R = W_DAC_B;
639
640 dac wav_dac_a(
641
642 .Clk(I_CLK_18432M),
643 .Reset(~W_RESETn),
644 .DACin(W_SDAT_A),
645 .DACout(W_DAC_A)
646
647 );
648
649 dac wav_dac_b(
650
651 .Clk(I_CLK_18432M),
652 .Reset(~W_RESETn),
653 .DACin(W_SDAT_B),
654 .DACout(W_DAC_B)
655
656 );
657
658
659 endmodule
660
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