faster clock for roms
[fpga-games] / galaxian / src / roms.v
1 module galaxian_roms(
2 I_ROM_CLK,
3 I_ADDR,
4 O_DATA
5 );
6
7 input I_ROM_CLK;
8 input [18:0]I_ADDR;
9 output [7:0]O_DATA;
10
11 //CPU-Roms
12 wire [7:0]U_ROM_D;
13
14 GALAXIAN_U U_ROM(
15 .CLK(I_ROM_CLK),
16 .ADDR(I_ADDR[10:0]),
17 .DATA(U_ROM_D),
18 .ENA(1'b1)
19 );
20
21 wire [7:0]V_ROM_D;
22
23 GALAXIAN_V V_ROM(
24 .CLK(I_ROM_CLK),
25 .ADDR(I_ADDR[10:0]),
26 .DATA(V_ROM_D),
27 .ENA(1'b1)
28 );
29
30 wire [7:0]W_ROM_D;
31
32 GALAXIAN_W W_ROM(
33 .CLK(I_ROM_CLK),
34 .ADDR(I_ADDR[10:0]),
35 .DATA(W_ROM_D),
36 .ENA(1'b1)
37 );
38
39 wire [7:0]Y_ROM_D;
40
41 GALAXIAN_Y Y_ROM(
42 .CLK(I_ROM_CLK),
43 .ADDR(I_ADDR[10:0]),
44 .DATA(Y_ROM_D),
45 .ENA(1'b1)
46 );
47
48 //7L CPU-Rom
49 wire [7:0]L_ROM_D;
50
51 GALAXIAN_7L L_ROM(
52 .CLK(I_ROM_CLK),
53 .ADDR(I_ADDR[10:0]),
54 .DATA(L_ROM_D),
55 .ENA(1'b1)
56 );
57
58 //1K VID-Rom
59 wire [7:0]K_ROM_D;
60
61 GALAXIAN_1K K_ROM(
62 .CLK(I_ROM_CLK),
63 .ADDR(I_ADDR[10:0]),
64 .DATA(K_ROM_D),
65 .ENA(1'b1)
66 );
67
68 //1H VID-Rom
69 wire [7:0]H_ROM_D;
70
71 GALAXIAN_1H H_ROM(
72 .CLK(I_ROM_CLK),
73 .ADDR(I_ADDR[10:0]),
74 .DATA(H_ROM_D),
75 .ENA(1'b1)
76 );
77
78 reg [7:0]DATA_OUT;
79 reg [7:0]DATA_OUT2;
80
81 // address map
82 //--------------------------------------------------
83 // 0x00000 - 0x007FF galmidw.u CPU-ROM
84 // 0x00800 - 0x00FFF galmidw.v CPU-ROM
85 // 0x01000 - 0x017FF galmidw.w CPU-ROM
86 // 0x01800 - 0x01FFF galmidw.y CPU-ROM
87 // 0x02000 - 0x027FF 7l CPU-ROM
88 // 0x04000 - 0x047FF 1k.bin VID-ROM
89 // 0x05000 - 0x057FF 1h.bin VID-ROM
90 // 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
91 always@(posedge I_ROM_CLK)
92 begin
93 if (I_ADDR <= 18'h7ff) begin
94 //u
95 DATA_OUT <= U_ROM_D;
96 end
97 else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
98 //v
99 DATA_OUT <= V_ROM_D;
100 end
101 else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
102 //w
103 DATA_OUT <= W_ROM_D;
104 end
105 else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
106 //y
107 DATA_OUT <= Y_ROM_D;
108 end
109 else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
110 //7l
111 DATA_OUT <= L_ROM_D;
112 end
113 else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
114 //1k
115 DATA_OUT <= K_ROM_D;
116 end
117 else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
118 //1h
119 DATA_OUT <= H_ROM_D;
120 end
121 else if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
122 //sound
123 DATA_OUT <= 8'h00;
124 end
125 else begin
126 DATA_OUT <= DATA_OUT;
127 end
128 end
129
130 assign O_DATA = DATA_OUT;
131
132 endmodule
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