58bc3c0cd9b79f69fe8ee72f9ff1e1af4617883e
[fpga-games] / galaxian / src / mc_top.v
1 //===============================================================================
2 // FPGA GALAXIAN TOP
3 //
4 // Version : 2.50
5 //
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
7 //
8 // Important !
9 //
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
13 //
14 // 2004- 4-30 galaxian modify by K.DEGAWA
15 // 2004- 5- 6 first release.
16 // 2004- 8-23 Improvement with T80-IP.
17 // 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.
18 // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
19 //================================================================================
20
21 `include "src/mc_conf.v"
22
23 module mc_top(
24
25 // FPGA_USE
26 I_CLK_125M,
27
28 `ifdef PSPAD_USE
29 // PS_PAD interface
30 psCLK,
31 psSEL,
32 psTXD,
33 psRXD,
34 `endif
35
36 // ROM IF
37 //O_ROM_AB,
38 //I_ROM_DB,
39 //O_ROM_OEn,
40 //O_ROM_CSn,
41 //O_ROM_WEn,
42
43 // INPORT SW IF
44 I_PSW,
45
46 // SOUND OUT
47 O_SOUND_OUT_L,
48 O_SOUND_OUT_R,
49
50 // VGA (VIDEO) IF
51 O_VGA_R,
52 O_VGA_G,
53 O_VGA_B,
54 O_VGA_H_SYNCn,
55 O_VGA_V_SYNCn
56
57 );
58
59 // FPGA_USE
60 input I_CLK_125M;
61
62 // CPU ADDRESS BUS
63 wire [15:0]W_A;
64 // CPU IF
65 wire W_CPU_RDn;
66 wire W_CPU_WRn;
67 wire W_CPU_MREQn;
68 wire W_CPU_RFSHn;
69 wire W_CPU_BUSAKn;
70 wire W_CPU_IORQn;
71 wire W_CPU_M1n;
72 wire W_CPU_CLK;
73 wire W_CPU_HRDWR_RESETn;
74 wire W_CPU_WAITn;
75 wire W_CPU_NMIn;
76
77 `ifdef PSPAD_USE
78 // PS_PAD interface
79 input psRXD;
80 output psTXD,psCLK,psSEL;
81 `endif
82
83 // ROM IF
84 //output [18:0]O_ROM_AB;
85 //input [7:0]I_ROM_DB;
86 //output O_ROM_OEn;
87 //output O_ROM_CSn;
88 //output O_ROM_WEn;
89
90 // INPORT SW IF
91 input [4:0]I_PSW;
92
93 // SOUND OUT
94 output O_SOUND_OUT_L;
95 output O_SOUND_OUT_R;
96
97 // VGA (VIDEO) IF
98 output [4:0]O_VGA_R;
99 output [4:0]O_VGA_G;
100 output [4:0]O_VGA_B;
101 output O_VGA_H_SYNCn;
102 output O_VGA_V_SYNCn;
103
104 wire W_RESETn = |I_PSW[3:0];
105 //------ CLOCK GEN ---------------------------
106 wire I_CLK_18432M;
107 wire W_CLK_12M,WB_CLK_12M;
108 wire W_CLK_6M,WB_CLK_6M;
109 wire W_STARS_CLK;
110
111 dcm clockgen(
112 .CLKIN_IN(I_CLK_125M),
113 .RST_IN(W_RESETn),
114 .CLKFX_OUT(I_CLK_18432M)
115 );
116
117 //------ H&V COUNTER -------------------------
118 wire [8:0]W_H_CNT;
119 wire [7:0]W_V_CNT;
120 wire W_H_BL;
121 wire W_V_BLn;
122 wire W_C_BLn;
123 wire W_H_SYNC;
124 wire W_V_SYNC;
125
126 //------ CPU RAM ----------------------------
127 wire [7:0]W_CPU_RAM_DO;
128
129 //------ ADDRESS DECDER ----------------------
130 wire W_CPU_ROM_CSn;
131 wire W_CPU_RAM_RDn;
132 wire W_CPU_RAM_WRn;
133 wire W_CPU_RAM_CSn;
134 wire W_OBJ_RAM_RDn;
135 wire W_OBJ_RAM_WRn;
136 wire W_OBJ_RAM_RQn;
137 wire W_VID_RAM_RDn;
138 wire W_VID_RAM_WRn;
139 wire W_SW0_OEn;
140 wire W_SW1_OEn;
141 wire W_DIP_OEn;
142 wire W_WDR_OEn;
143 wire W_LAMP_WEn;
144 wire W_SOUND_WEn;
145 wire W_PITCHn;
146 wire W_H_FLIP;
147 wire W_V_FLIP;
148 wire W_BD_G;
149 wire W_STARS_ON;
150
151 wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;
152 wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;
153 //------- INPORT -----------------------------
154 wire [7:0]W_SW_DO;
155 //------- VIDEO -----------------------------
156 wire [7:0]W_VID_DO;
157 //--------------------------------------------
158
159 mc_clock MC_CLK(
160
161 .I_CLK_18M(I_CLK_18432M),
162 .O_CLK_12M(WB_CLK_12M),
163 .O_CLK_06M(WB_CLK_6M)
164
165 );
166
167 `ifdef DEVICE_CYCLONE
168 assign W_CLK_12M = WB_CLK_12M;
169 assign W_CLK_6M = WB_CLK_6M;
170 `endif
171 `ifdef DEVICE_SPARTAN2E
172 BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );
173 BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );
174 `endif
175 //--- DATA I/F -------------------------------------
176 reg [7:0]W_CPU_ROM_DO;
177 wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;
178
179 wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;
180 wire [7:0]W_BDI;
181
182 //--- CPU I/F -------------------------------------
183 reg [3:0]rst_count;
184 always@(posedge W_H_CNT[0] or negedge W_RESETn)
185 begin
186 if(! W_RESETn) rst_count <= 0;
187 else begin
188 if( rst_count == 15)
189 rst_count <= rst_count;
190 else
191 rst_count <= rst_count+1;
192 end
193 end
194
195 assign W_CPU_RESETn = W_RESETn;
196 assign W_CPU_CLK = W_H_CNT[0];
197
198 Z80IP CPU(
199
200 .CLK(W_CPU_CLK),
201 .RESET_N(W_CPU_RESETn),
202 .INT_N(1'b1),
203 .NMI_N(W_CPU_NMIn),
204 .ADRS(W_A),
205 .DOUT(W_BDI),
206 .DINP(W_BDO),
207 .M1_N(),
208 .MREQ_N(W_CPU_MREQn),
209 .IORQ_N(),
210 .RD_N(W_CPU_RDn ),
211 .WR_N(W_CPU_WRn ),
212 .WAIT_N(W_CPU_WAITn),
213 .BUSWO(),
214 .RFSH_N(W_CPU_RFSHn),
215 .HALT_N()
216
217 );
218
219 wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;
220
221 mc_cpu_ram MC_CPU_RAM(
222
223 .I_CLK(W_CPU_RAM_CLK),
224 .I_ADDR(W_A[9:0]),
225 .I_D(W_BDI),
226 .I_WE(~W_CPU_WRn),
227 .I_OE(~W_CPU_RAM_RDn ),
228 .O_D(W_CPU_RAM_DO)
229
230 );
231
232
233 mc_adec MC_ADEC(
234
235 .I_CLK_12M(W_CLK_12M),
236 .I_CLK_6M(W_CLK_6M),
237 .I_CPU_CLK(W_H_CNT[0]),
238 .I_RSTn(W_RESETn),
239
240 .I_CPU_A(W_A),
241 .I_CPU_D(W_BDI[0]),
242 .I_MREQn(W_CPU_MREQn),
243 .I_RFSHn(W_CPU_RFSHn),
244 .I_RDn(W_CPU_RDn),
245 .I_WRn(W_CPU_WRn),
246 .I_H_BL(W_H_BL),
247 .I_V_BLn(W_V_BLn),
248
249 .O_WAITn(W_CPU_WAITn),
250 .O_NMIn(W_CPU_NMIn),
251 .O_CPU_ROM_CSn(W_CPU_ROM_CSn),
252 .O_CPU_RAM_RDn(W_CPU_RAM_RDn),
253 .O_CPU_RAM_WRn(W_CPU_RAM_WRn),
254 .O_CPU_RAM_CSn(W_CPU_RAM_CSn),
255 .O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
256 .O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
257 .O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
258 .O_VID_RAM_RDn(W_VID_RAM_RDn),
259 .O_VID_RAM_WRn(W_VID_RAM_WRn),
260 .O_SW0_OEn(W_SW0_OEn),
261 .O_SW1_OEn(W_SW1_OEn),
262 .O_DIP_OEn(W_DIP_OEn),
263 .O_WDR_OEn(W_WDR_OEn),
264 .O_LAMP_WEn(W_LAMP_WEn),
265 .O_SOUND_WEn(W_SOUND_WEn),
266 .O_PITCHn(W_PITCHn),
267 .O_H_FLIP(W_H_FLIP),
268 .O_V_FLIP(W_V_FLIP),
269 .O_BD_G(W_BD_G),
270 .O_STARS_ON(W_STARS_ON)
271
272 );
273
274 //-------- SOUND I/F -----------------------------
275 //--- Parts 9L ---------
276 reg [7:0]W_9L_Q;
277 always@(posedge W_CLK_12M or negedge W_RESETn)
278 begin
279 if(W_RESETn == 1'b0)begin
280 W_9L_Q <= 0;
281 end
282 else begin
283 if(W_SOUND_WEn == 1'b0)begin
284 case(W_A[2:0])
285 3'h0 : W_9L_Q[0] <= W_BDI[0];
286 3'h1 : W_9L_Q[1] <= W_BDI[0];
287 3'h2 : W_9L_Q[2] <= W_BDI[0];
288 3'h3 : W_9L_Q[3] <= W_BDI[0];
289 3'h4 : W_9L_Q[4] <= W_BDI[0];
290 3'h5 : W_9L_Q[5] <= W_BDI[0];
291 3'h6 : W_9L_Q[6] <= W_BDI[0];
292 3'h7 : W_9L_Q[7] <= W_BDI[0];
293 endcase
294 end
295 end
296 end
297 wire W_VOL1 = W_9L_Q[6];
298 wire W_VOL2 = W_9L_Q[7];
299 wire W_FIRE = W_9L_Q[5];
300 wire W_HIT = W_9L_Q[3];
301 wire W_FS3 = W_9L_Q[2];
302 wire W_FS2 = W_9L_Q[1];
303 wire W_FS1 = W_9L_Q[0];
304 //---------------------------------------------------
305 //---- CPU DATA WATCH -------------------------------
306 wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;
307
308 reg [1:0]on_game;
309 always @(posedge W_CPU_CLK)
310 begin
311 if(~ZMWR)begin
312 if(W_A == 16'h4007)begin
313 if(W_BDI == 8'h00)
314 on_game[0] <= 1;
315 else
316 on_game[0] <= 0;
317 end
318 if(W_A == 16'h4005)begin
319 if(W_BDI == 8'h03 || W_BDI == 8'h04 )
320 on_game[1] <= 1;
321 else
322 on_game[1] <= 0;
323 end
324 end
325 end
326
327 `ifdef PSPAD_USE
328 reg died;
329 always @(posedge W_CPU_CLK)
330 begin
331 if(~ZMWR)begin
332 if(W_A == 16'h4206)begin
333 if(W_BDI == 8'h00)
334 died <= 0;
335 else
336 died <= 1;
337 end
338 end
339 end
340 //---- PS_PAD Interface -----------------------------
341 wire [8:0]ps_PSW;
342 wire VIB_SW = died & (&on_game[1:0]);
343
344 fpga_arcade_if pspad(
345
346 .CLK_18M432(I_CLK_18432M),
347 .I_RSTn(W_RESETn),
348 .psCLK(psCLK),
349 .psSEL(psSEL),
350 .psTXD(psTXD),
351 .psRXD(psRXD),
352 .ps_PSW(ps_PSW),
353 .I_VIB_SW(VIB_SW)
354
355 );
356 `endif
357 //---- SW Interface ---------------------------------
358 `ifdef PSPAD_USE
359 wire L1 = I_PSW[2] & ps_PSW[2];
360 wire R1 = I_PSW[3] & ps_PSW[3];
361 wire U1 = I_PSW[0];
362 wire D1 = I_PSW[1];
363 wire J1 = I_PSW[4] & ps_PSW[8];
364
365 wire S1 = (U1|J1) & ps_PSW[6];
366 wire S2 = (D1|J1) & ps_PSW[7];
367
368 wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];
369 `else
370 wire L1 = I_PSW[2];
371 wire R1 = I_PSW[3];
372 wire U1 = I_PSW[0];
373 wire D1 = I_PSW[1];
374 wire J1 = I_PSW[4];
375
376 wire S1 = U1|J1;
377 wire S2 = D1|J1;
378
379 wire C1 = L1|R1|U1|~D1;
380 `endif
381 wire C2 = L1|R1|~U1|D1;
382
383 wire L2 = L1;
384 wire R2 = R1;
385 wire U2 = U1;
386 wire D2 = D1;
387 wire J2 = J1;
388
389 mc_inport MC_INPORT(
390
391 .I_COIN1(~C1), // ACTIVE HI
392 .I_COIN2(~C2), // ACTIVE HI
393 .I_1P_LE(~L1), // ACTIVE HI
394 .I_1P_RI(~R1), // ACTIVE HI
395 .I_1P_SH(~J1), // ACTIVE HI
396 .I_2P_LE(~L2), // ACTIVE HI
397 .I_2P_RI(~R2), // ACTIVE HI
398 .I_2P_SH(~J2), // ACTIVE HI
399 .I_1P_START(~S1), // ACTIVE HI
400 .I_2P_START(~S2), // ACTIVE HI
401
402 .I_SW0_OEn(W_SW0_OEn),
403 .I_SW1_OEn(W_SW1_OEn),
404 .I_DIP_OEn(W_DIP_OEn),
405
406 .O_D(W_SW_DO)
407
408 );
409
410 //-----------------------------------------------------------------------------
411 //------- ROM -------------------------------------------------------
412 reg [18:0]ROM_A;
413 wire [10:0]W_OBJ_ROM_A;
414 reg [7:0]W_OBJ_ROM_A_D;
415 reg [7:0]W_OBJ_ROM_B_D;
416
417 wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;
418 reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;
419
420 wire [7:0]ROM_D; // = I_ROM_DB;
421 //assign O_ROM_AB = ROM_A;
422
423 //assign O_ROM_OEn = 1'b0;
424 //assign O_ROM_CSn = 1'b0;
425 //assign O_ROM_WEn = 1'b1;
426
427 galaxian_roms ROMS(
428 .I_CLK_18432M(I_CLK_18432M),
429 .I_CLK_12M(WB_CLK_12M),
430 .I_ADDR(ROM_A),
431 .O_DATA(ROM_D)
432 );
433
434
435 reg [1:0]clk_d;
436 reg [4:0]seq;
437 always @(posedge I_CLK_18432M)
438 begin
439 // 24 phase generator
440 clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];
441 clk_d[1] <= clk_d[0];
442 seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;
443 case(seq)
444 0:begin
445 //sound
446 ROM_A <= W_WAV_A0;
447 W_CPU_ROM_DO <= ROM_D;
448 end
449 2:begin
450 //sound
451 ROM_A <= W_WAV_A1;
452 W_WAV_D0 <= ROM_D;
453 end
454 4:begin
455 //sound
456 ROM_A <= {3'h0,W_A[15:0]};
457 W_WAV_D1 <= ROM_D;
458 end
459 6:begin
460 //sound
461 ROM_A <= W_WAV_A2;
462 W_CPU_ROM_DO <= ROM_D;
463 end
464 8:W_WAV_D2 <= ROM_D; //sound
465 10:ROM_A <= {3'h0,W_A[15:0]};
466 12:W_CPU_ROM_DO <= ROM_D;
467 16:ROM_A <= {3'h0,W_A[15:0]};
468 18:begin
469 ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};
470 W_CPU_ROM_DO <= ROM_D;
471 end
472 20:begin
473 ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};
474 W_OBJ_ROM_A_D <= ROM_D;
475 end
476 22:begin
477 ROM_A <= {3'h0,W_A[15:0]};
478 W_OBJ_ROM_B_D <= ROM_D;
479 end
480 default:;
481 endcase
482 end
483 //-----------------------------------------------------------------------------
484
485 wire W_V_BL2n;
486
487 mc_hv_count MC_HV(
488
489 .I_CLK(WB_CLK_6M),
490 .I_RSTn(W_RESETn),
491
492 .O_H_CNT(W_H_CNT),
493 .O_H_SYNC(W_H_SYNC),
494 .O_H_BL(W_H_BL),
495 .O_V_CNT(W_V_CNT),
496 .O_V_SYNC(W_V_SYNC),
497 .O_V_BL2n(W_V_BL2n),
498 .O_V_BLn(W_V_BLn),
499 .O_C_BLn(W_C_BLn)
500
501 );
502
503 //------ VIDEO -----------------------------
504 wire W_8HF;
505 wire W_1VF;
506 wire W_C_BLnX;
507 wire W_256HnX;
508 wire W_MISSILEn;
509 wire W_SHELLn;
510 wire [1:0]W_VID;
511 wire [2:0]W_COL;
512
513 mc_video MC_VID(
514 .I_CLK_18M(I_CLK_18432M),
515 .I_CLK_12M(W_CLK_12M),
516 .I_CLK_6M(W_CLK_6M),
517 .I_H_CNT(W_H_CNT),
518 .I_V_CNT(W_V_CNT),
519 .I_H_FLIP(W_H_FLIP),
520 .I_V_FLIP(W_V_FLIP),
521 .I_V_BLn(W_V_BLn),
522 .I_C_BLn(W_C_BLn),
523
524 .I_A(W_A[9:0]),
525 .I_OBJ_SUB_A(3'b000),
526 .I_BD(W_BDI),
527 .I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
528 .I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
529 .I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
530 .I_VID_RAM_RDn(W_VID_RAM_RDn),
531 .I_VID_RAM_WRn(W_VID_RAM_WRn),
532
533 .O_OBJ_ROM_A(W_OBJ_ROM_A),
534 .I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),
535 .I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),
536
537 .O_C_BLnX(W_C_BLnX),
538 .O_8HF(W_8HF),
539 .O_256HnX(W_256HnX),
540 .O_1VF(W_1VF),
541 .O_MISSILEn(W_MISSILEn),
542 .O_SHELLn(W_SHELLn),
543 .O_BD(W_VID_DO),
544 .O_VID(W_VID),
545 .O_COL(W_COL)
546
547 );
548
549 wire W_C_BLX;
550 wire W_STARS_OFFn;
551 wire [2:0]W_VIDEO_R;
552 wire [2:0]W_VIDEO_G;
553 wire [1:0]W_VIDEO_B;
554
555 mc_col_pal MC_COL_PAL(
556
557 .I_CLK_12M(W_CLK_12M),
558 .I_CLK_6M(W_CLK_6M),
559 .I_VID(W_VID),
560 .I_COL(W_COL),
561 .I_C_BLnX(W_C_BLnX),
562
563 .O_C_BLX(W_C_BLX),
564 .O_STARS_OFFn(W_STARS_OFFn),
565 .O_R(W_VIDEO_R),
566 .O_G(W_VIDEO_G),
567 .O_B(W_VIDEO_B)
568
569 );
570
571 wire [2:0]W_STARS_R;
572 wire [2:0]W_STARS_G;
573 wire [1:0]W_STARS_B;
574
575 mc_stars MC_STARS(
576
577 .I_CLK_18M(I_CLK_18432M),
578 `ifdef DEVICE_CYCLONE
579 .I_CLK_6M(~WB_CLK_6M),
580 `endif
581 `ifdef DEVICE_SPARTAN2E
582 .I_CLK_6M(WB_CLK_6M),
583 `endif
584 .I_H_FLIP(W_H_FLIP),
585 .I_V_SYNC(W_V_SYNC),
586 .I_8HF(W_8HF),
587 .I_256HnX(W_256HnX),
588 .I_1VF(W_1VF),
589 .I_2V(W_V_CNT[1]),
590 .I_STARS_ON(W_STARS_ON),
591 .I_STARS_OFFn(W_STARS_OFFn),
592
593 .O_R(W_STARS_R),
594 .O_G(W_STARS_G),
595 .O_B(W_STARS_B),
596 .O_NOISE()
597
598 );
599
600 wire [2:0]W_R;
601 wire [2:0]W_G;
602 wire [1:0]W_B;
603
604 mc_vedio_mix MIX(
605
606 .I_VID_R(W_VIDEO_R),
607 .I_VID_G(W_VIDEO_G),
608 .I_VID_B(W_VIDEO_B),
609 .I_STR_R(W_STARS_R),
610 .I_STR_G(W_STARS_G),
611 .I_STR_B(W_STARS_B),
612
613 .I_C_BLnXX(~W_C_BLX),
614 .I_C_BLX(W_C_BLX | ~W_V_BL2n),
615 .I_MISSILEn(W_MISSILEn),
616 .I_SHELLn(W_SHELLn),
617
618 .O_R(W_R),
619 .O_G(W_G),
620 .O_B(W_B)
621
622 );
623
624 `ifdef VGA_USE
625 mc_vga_if VGA(
626
627 // input
628 .I_CLK_1(W_CLK_6M),
629 .I_CLK_2(W_CLK_12M),
630 .I_R(W_R),
631 .I_G(W_G),
632 .I_B(W_B),
633 .I_H_SYNC(W_H_SYNC),
634 .I_V_SYNC(W_V_SYNC),
635 // output
636 .O_R(O_VGA_R),
637 .O_G(O_VGA_G),
638 .O_B(O_VGA_B),
639 .O_H_SYNCn(O_VGA_H_SYNCn),
640 .O_V_SYNCn(O_VGA_V_SYNCn)
641
642 );
643
644 `else
645
646 assign O_VGA_R[2:0] = W_R;
647 assign O_VGA_R[4:3] = 1'b0;
648
649 assign O_VGA_G[2:0] = W_G;
650 assign O_VGA_G[4:3] = 1'b0;
651
652 assign O_VGA_B[1:0] = W_B;
653 assign O_VGA_B[4:2] = 1'b0;
654
655 //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED
656 assign O_VGA_H_SYNCn = ~W_H_SYNC ;
657 assign O_VGA_V_SYNCn = ~W_V_SYNC ;
658
659 `endif
660
661 wire [7:0]W_SDAT_A;
662
663 mc_sound_a MC_SOUND_A(
664
665 .I_CLK_12M(W_CLK_12M),
666 .I_CLK_6M(W_CLK_6M),
667 .I_H_CNT1(W_H_CNT[1]),
668 .I_BD(W_BDI),
669 .I_PITCHn(W_PITCHn),
670 .I_VOL1(W_VOL1),
671 .I_VOL2(W_VOL2),
672
673 .O_SDAT(W_SDAT_A),
674 .O_DO()
675
676 );
677
678 wire [7:0]W_SDAT_B;
679
680 mc_sound_b MC_SOUND_B(
681
682 .I_CLK1(I_CLK_18432M),
683 .I_CLK2(W_CLK_6M),
684 .I_RSTn(rst_count[3]),
685 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),
686
687 .O_WAV_A0(W_WAV_A0),
688 .O_WAV_A1(W_WAV_A1),
689 .O_WAV_A2(W_WAV_A2),
690 .I_WAV_D0(W_WAV_D0),
691 .I_WAV_D1(W_WAV_D1),
692 .I_WAV_D2(W_WAV_D2),
693
694 .O_SDAT(W_SDAT_B)
695
696 );
697
698 wire W_DAC_A;
699 wire W_DAC_B;
700
701 assign O_SOUND_OUT_L = W_DAC_A;
702 assign O_SOUND_OUT_R = W_DAC_B;
703
704 dac wav_dac_a(
705
706 .Clk(I_CLK_18432M),
707 .Reset(~W_RESETn),
708 .DACin(W_SDAT_A),
709 .DACout(W_DAC_A)
710
711 );
712
713 dac wav_dac_b(
714
715 .Clk(I_CLK_18432M),
716 .Reset(~W_RESETn),
717 .DACin(W_SDAT_B),
718 .DACout(W_DAC_B)
719
720 );
721
722
723 endmodule
724
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