update T80 ip
[fpga-games] / galaxian / t80_ip / T80_Pack.vhd
1 -- ****
2 -- T80(b) core. In an effort to merge and maintain bug fixes ....
3 --
4 --
5 -- Ver 300 started tidyup
6 -- MikeJ March 2005
7 -- Latest version from www.fpgaarcade.com (original www.opencores.org)
8 --
9 -- ****
10 --
11 -- Z80 compatible microprocessor core
12 --
13 -- Version : 0242
14 --
15 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
16 --
17 -- All rights reserved
18 --
19 -- Redistribution and use in source and synthezised forms, with or without
20 -- modification, are permitted provided that the following conditions are met:
21 --
22 -- Redistributions of source code must retain the above copyright notice,
23 -- this list of conditions and the following disclaimer.
24 --
25 -- Redistributions in synthesized form must reproduce the above copyright
26 -- notice, this list of conditions and the following disclaimer in the
27 -- documentation and/or other materials provided with the distribution.
28 --
29 -- Neither the name of the author nor the names of other contributors may
30 -- be used to endorse or promote products derived from this software without
31 -- specific prior written permission.
32 --
33 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
35 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
36 -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
37 -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
40 -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
41 -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 -- POSSIBILITY OF SUCH DAMAGE.
44 --
45 -- Please report bugs to the author, but before you do so, please
46 -- make sure that this is not a derivative work and that
47 -- you have the latest version of this file.
48 --
49 -- The latest version of this file can be found at:
50 -- http://www.opencores.org/cvsweb.shtml/t80/
51 --
52 -- Limitations :
53 --
54 -- File history :
55 --
56
57 library IEEE;
58 use IEEE.std_logic_1164.all;
59
60 package T80_Pack is
61
62 component T80
63 generic(
64 Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
65 IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
66 Flag_C : integer := 0;
67 Flag_N : integer := 1;
68 Flag_P : integer := 2;
69 Flag_X : integer := 3;
70 Flag_H : integer := 4;
71 Flag_Y : integer := 5;
72 Flag_Z : integer := 6;
73 Flag_S : integer := 7
74 );
75 port(
76 RESET_n : in std_logic;
77 CLK_n : in std_logic;
78 CEN : in std_logic;
79 WAIT_n : in std_logic;
80 INT_n : in std_logic;
81 NMI_n : in std_logic;
82 BUSRQ_n : in std_logic;
83 M1_n : out std_logic;
84 IORQ : out std_logic;
85 NoRead : out std_logic;
86 Write : out std_logic;
87 RFSH_n : out std_logic;
88 HALT_n : out std_logic;
89 BUSAK_n : out std_logic;
90 A : out std_logic_vector(15 downto 0);
91 DInst : in std_logic_vector(7 downto 0);
92 DI : in std_logic_vector(7 downto 0);
93 DO : out std_logic_vector(7 downto 0);
94 MC : out std_logic_vector(2 downto 0);
95 TS : out std_logic_vector(2 downto 0);
96 IntCycle_n : out std_logic;
97 IntE : out std_logic;
98 Stop : out std_logic
99 );
100 end component;
101
102 component T80_Reg
103 port(
104 Clk : in std_logic;
105 CEN : in std_logic;
106 WEH : in std_logic;
107 WEL : in std_logic;
108 AddrA : in std_logic_vector(2 downto 0);
109 AddrB : in std_logic_vector(2 downto 0);
110 AddrC : in std_logic_vector(2 downto 0);
111 DIH : in std_logic_vector(7 downto 0);
112 DIL : in std_logic_vector(7 downto 0);
113 DOAH : out std_logic_vector(7 downto 0);
114 DOAL : out std_logic_vector(7 downto 0);
115 DOBH : out std_logic_vector(7 downto 0);
116 DOBL : out std_logic_vector(7 downto 0);
117 DOCH : out std_logic_vector(7 downto 0);
118 DOCL : out std_logic_vector(7 downto 0)
119 );
120 end component;
121
122 component T80_MCode
123 generic(
124 Mode : integer := 0;
125 Flag_C : integer := 0;
126 Flag_N : integer := 1;
127 Flag_P : integer := 2;
128 Flag_X : integer := 3;
129 Flag_H : integer := 4;
130 Flag_Y : integer := 5;
131 Flag_Z : integer := 6;
132 Flag_S : integer := 7
133 );
134 port(
135 IR : in std_logic_vector(7 downto 0);
136 ISet : in std_logic_vector(1 downto 0);
137 MCycle : in std_logic_vector(2 downto 0);
138 F : in std_logic_vector(7 downto 0);
139 NMICycle : in std_logic;
140 IntCycle : in std_logic;
141 MCycles : out std_logic_vector(2 downto 0);
142 TStates : out std_logic_vector(2 downto 0);
143 Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
144 Inc_PC : out std_logic;
145 Inc_WZ : out std_logic;
146 IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
147 Read_To_Reg : out std_logic;
148 Read_To_Acc : out std_logic;
149 Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
150 Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
151 ALU_Op : out std_logic_vector(3 downto 0);
152 -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
153 Save_ALU : out std_logic;
154 PreserveC : out std_logic;
155 Arith16 : out std_logic;
156 Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
157 IORQ : out std_logic;
158 Jump : out std_logic;
159 JumpE : out std_logic;
160 JumpXY : out std_logic;
161 Call : out std_logic;
162 RstP : out std_logic;
163 LDZ : out std_logic;
164 LDW : out std_logic;
165 LDSPHL : out std_logic;
166 Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
167 ExchangeDH : out std_logic;
168 ExchangeRp : out std_logic;
169 ExchangeAF : out std_logic;
170 ExchangeRS : out std_logic;
171 I_DJNZ : out std_logic;
172 I_CPL : out std_logic;
173 I_CCF : out std_logic;
174 I_SCF : out std_logic;
175 I_RETN : out std_logic;
176 I_BT : out std_logic;
177 I_BC : out std_logic;
178 I_BTR : out std_logic;
179 I_RLD : out std_logic;
180 I_RRD : out std_logic;
181 I_INRC : out std_logic;
182 SetDI : out std_logic;
183 SetEI : out std_logic;
184 IMode : out std_logic_vector(1 downto 0);
185 Halt : out std_logic;
186 NoRead : out std_logic;
187 Write : out std_logic
188 );
189 end component;
190
191 component T80_ALU
192 generic(
193 Mode : integer := 0;
194 Flag_C : integer := 0;
195 Flag_N : integer := 1;
196 Flag_P : integer := 2;
197 Flag_X : integer := 3;
198 Flag_H : integer := 4;
199 Flag_Y : integer := 5;
200 Flag_Z : integer := 6;
201 Flag_S : integer := 7
202 );
203 port(
204 Arith16 : in std_logic;
205 Z16 : in std_logic;
206 ALU_Op : in std_logic_vector(3 downto 0);
207 IR : in std_logic_vector(5 downto 0);
208 ISet : in std_logic_vector(1 downto 0);
209 BusA : in std_logic_vector(7 downto 0);
210 BusB : in std_logic_vector(7 downto 0);
211 F_In : in std_logic_vector(7 downto 0);
212 Q : out std_logic_vector(7 downto 0);
213 F_Out : out std_logic_vector(7 downto 0)
214 );
215 end component;
216
217 end;
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