we have no sound rom
[fpga-games] / galaxian / src / roms.v
1 module galaxian_roms(
2 I_CLK_18432M,
3 I_CLK_12M,
4 I_ADDR,
5 O_DATA
6 );
7
8 input I_CLK_12M;
9 input I_CLK_18432M;
10 input [18:0]I_ADDR;
11 output [7:0]O_DATA;
12
13 //CPU-Roms
14 wire [7:0]U_ROM_D;
15 reg [10:0]U_ROM_A;
16
17 GALAXIAN_U U_ROM(
18 .CLK(I_CLK_12M),
19 .ADDR(U_ROM_A),
20 .DATA(U_ROM_D),
21 .ENA(1'b1)
22 );
23
24 wire [7:0]V_ROM_D;
25 reg [10:0]V_ROM_A;
26
27 GALAXIAN_V V_ROM(
28 .CLK(I_CLK_12M),
29 .ADDR(V_ROM_A),
30 .DATA(V_ROM_D),
31 .ENA(1'b1)
32 );
33
34 wire [7:0]W_ROM_D;
35 reg [10:0]W_ROM_A;
36
37 GALAXIAN_W W_ROM(
38 .CLK(I_CLK_12M),
39 .ADDR(W_ROM_A),
40 .DATA(W_ROM_D),
41 .ENA(1'b1)
42 );
43
44 wire [7:0]Y_ROM_D;
45 reg [10:0]Y_ROM_A;
46
47 GALAXIAN_Y Y_ROM(
48 .CLK(I_CLK_12M),
49 .ADDR(Y_ROM_A),
50 .DATA(Y_ROM_D),
51 .ENA(1'b1)
52 );
53
54 //7L CPU-Rom
55 wire [7:0]L_ROM_D;
56 reg [10:0]L_ROM_A;
57
58 GALAXIAN_7L L_ROM(
59 .CLK(I_CLK_12M),
60 .ADDR(L_ROM_A),
61 .DATA(L_ROM_D),
62 .ENA(1'b1)
63 );
64
65 //1K VID-Rom
66 wire [7:0]K_ROM_D;
67 reg [10:0]K_ROM_A;
68
69 GALAXIAN_1K K_ROM(
70 .CLK(I_CLK_12M),
71 .ADDR(K_ROM_A),
72 .DATA(K_ROM_D),
73 .ENA(1'b1)
74 );
75
76 //1H VID-Rom
77 wire [7:0]H_ROM_D;
78 reg [10:0]H_ROM_A;
79
80 GALAXIAN_1H H_ROM(
81 .CLK(I_CLK_12M),
82 .ADDR(H_ROM_A),
83 .DATA(H_ROM_D),
84 .ENA(1'b1)
85 );
86
87 reg [7:0]DATA_OUT;
88
89 // address map
90 //--------------------------------------------------
91 // 0x00000 - 0x007FF galmidw.u CPU-ROM
92 // 0x00800 - 0x00FFF galmidw.v CPU-ROM
93 // 0x01000 - 0x017FF galmidw.w CPU-ROM
94 // 0x01800 - 0x01FFF galmidw.y CPU-ROM
95 // 0x02000 - 0x027FF 7l CPU-ROM
96 // 0x04000 - 0x047FF 1k.bin VID-ROM
97 // 0x05000 - 0x057FF 1h.bin VID-ROM
98 // 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
99 always
100 begin
101 if (I_ADDR <= 18'h7ff) begin
102 //u
103 U_ROM_A <= I_ADDR[10:0];
104 DATA_OUT <= U_ROM_D;
105 end
106 if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
107 //v
108 V_ROM_A <= I_ADDR[10:0];
109 DATA_OUT <= V_ROM_D;
110 end
111 if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
112 //w
113 W_ROM_A <= I_ADDR[10:0];
114 DATA_OUT <= W_ROM_D;
115 end
116 if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
117 //y
118 Y_ROM_A <= I_ADDR[10:0];
119 DATA_OUT <= Y_ROM_D;
120 end
121 if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
122 //7l
123 L_ROM_A <= I_ADDR[10:0];
124 DATA_OUT <= L_ROM_D;
125 end
126 if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
127 //1k
128 K_ROM_A <= I_ADDR[10:0];
129 DATA_OUT <= K_ROM_D;
130 end
131 if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
132 //1h
133 H_ROM_A <= I_ADDR[10:0];
134 DATA_OUT <= H_ROM_D;
135 end
136 if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
137 //sound
138 DATA_OUT <= 8'h00;
139 end
140 end
141
142 assign O_DATA = DATA_OUT;
143
144 endmodule
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