I_CLK_36M,\r
O_CLK_18M,\r
O_CLK_12M,\r
-O_CLK_06M\r
+O_CLK_06M,\r
+O_CLK_06Mn\r
\r
);\r
\r
output O_CLK_18M;\r
output O_CLK_12M;\r
output O_CLK_06M;\r
+output O_CLK_06Mn;\r
\r
// 2/3 clock divider(duty 33%)\r
//I_CLK 1010101010101010101\r
\r
// 1/3 clock divider (duty 50%)\r
reg CLK_6M;\r
+reg CLK_6Mn;\r
+\r
always @(posedge O_CLK_12M)\r
begin\r
CLK_6M <= ~CLK_6M;\r
+ CLK_6Mn <= CLK_6M;\r
end\r
+\r
assign O_CLK_06M = CLK_6M;\r
+assign O_CLK_06Mn = CLK_6Mn;\r
\r
endmodule\r