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4e93cb00 MG |
1 | /* |
2 | * linux/arch/arm/mm/cache-v7.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * Copyright (C) 2005 ARM Ltd. | |
6 | * This Edition is maintained by Matthew Veety (aliasxerog) <mveety@gmail.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This is the "shell" of the ARMv7 processor support. | |
13 | */ | |
14 | #include <linux/linkage.h> | |
15 | #include <linux/init.h> | |
16 | #include <asm/assembler.h> | |
17 | ||
18 | #include "proc-macros.S" | |
19 | ||
20 | /* | |
21 | * v7_flush_dcache_all() | |
22 | * | |
23 | * Flush the whole D-cache. | |
24 | * | |
25 | * Corrupted registers: r0-r5, r7, r9-r11 | |
26 | * | |
27 | * - mm - mm_struct describing address space | |
28 | */ | |
29 | ENTRY(v7_flush_dcache_all) | |
30 | dmb @ ensure ordering with previous memory accesses | |
31 | mrc p15, 1, r0, c0, c0, 1 @ read clidr | |
32 | ands r3, r0, #0x7000000 @ extract loc from clidr | |
33 | mov r3, r3, lsr #23 @ left align loc bit field | |
34 | beq finished @ if loc is 0, then no need to clean | |
35 | mov r10, #0 @ start clean at cache level 0 | |
36 | loop1: | |
37 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | |
38 | mov r1, r0, lsr r2 @ extract cache type bits from clidr | |
39 | and r1, r1, #7 @ mask of the bits for current cache only | |
40 | cmp r1, #2 @ see what cache we have at this level | |
41 | blt skip @ skip if no cache, or just i-cache | |
42 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
43 | isb @ isb to sych the new cssr&csidr | |
44 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | |
45 | and r2, r1, #7 @ extract the length of the cache lines | |
46 | add r2, r2, #4 @ add 4 (line length offset) | |
47 | ldr r4, =0x3ff | |
48 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | |
49 | clz r5, r4 @ find bit position of way size increment | |
50 | ldr r7, =0x7fff | |
51 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | |
52 | loop2: | |
53 | mov r9, r4 @ create working copy of max way size | |
54 | loop3: | |
55 | orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 | |
56 | orr r11, r11, r7, lsl r2 @ factor index number into r11 | |
57 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way | |
58 | subs r9, r9, #1 @ decrement the way | |
59 | bge loop3 | |
60 | subs r7, r7, #1 @ decrement the index | |
61 | bge loop2 | |
62 | skip: | |
63 | add r10, r10, #2 @ increment cache number | |
64 | cmp r3, r10 | |
65 | bgt loop1 | |
66 | finished: | |
67 | mov r10, #0 @ swith back to cache level 0 | |
68 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
69 | dsb | |
70 | isb | |
71 | mov pc, lr | |
72 | ENDPROC(v7_flush_dcache_all) | |
73 | ||
74 | /* | |
75 | * v7_flush_cache_all() | |
76 | * | |
77 | * Flush the entire cache system. | |
78 | * The data cache flush is now achieved using atomic clean / invalidates | |
79 | * working outwards from L1 cache. This is done using Set/Way based cache | |
80 | * maintainance instructions. | |
81 | * The instruction cache can still be invalidated back to the point of | |
82 | * unification in a single instruction. | |
83 | * | |
84 | */ | |
85 | ENTRY(v7_flush_kern_cache_all) | |
86 | stmfd sp!, {r4-r5, r7, r9-r11, lr} | |
87 | bl v7_flush_dcache_all | |
88 | mov r0, #0 | |
89 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate | |
90 | ldmfd sp!, {r4-r5, r7, r9-r11, lr} | |
91 | mov pc, lr | |
92 | ENDPROC(v7_flush_kern_cache_all) | |
93 | ||
94 | /* | |
95 | * v7_flush_cache_all() | |
96 | * | |
97 | * Flush all TLB entries in a particular address space | |
98 | * | |
99 | * - mm - mm_struct describing address space | |
100 | */ | |
101 | ENTRY(v7_flush_user_cache_all) | |
102 | /*FALLTHROUGH*/ | |
103 | ||
104 | /* | |
105 | * v7_flush_cache_range(start, end, flags) | |
106 | * | |
107 | * Flush a range of TLB entries in the specified address space. | |
108 | * | |
109 | * - start - start address (may not be aligned) | |
110 | * - end - end address (exclusive, may not be aligned) | |
111 | * - flags - vm_area_struct flags describing address space | |
112 | * | |
113 | * It is assumed that: | |
114 | * - we have a VIPT cache. | |
115 | */ | |
116 | ENTRY(v7_flush_user_cache_range) | |
117 | mov pc, lr | |
118 | ENDPROC(v7_flush_user_cache_all) | |
119 | ENDPROC(v7_flush_user_cache_range) | |
120 | ||
121 | /* | |
122 | * v7_coherent_kern_range(start,end) | |
123 | * | |
124 | * Ensure that the I and D caches are coherent within specified | |
125 | * region. This is typically used when code has been written to | |
126 | * a memory region, and will be executed. | |
127 | * | |
128 | * - start - virtual start address of region | |
129 | * - end - virtual end address of region | |
130 | * | |
131 | * It is assumed that: | |
132 | * - the Icache does not read data from the write buffer | |
133 | */ | |
134 | ENTRY(v7_coherent_kern_range) | |
135 | /* FALLTHROUGH */ | |
136 | ||
137 | /* | |
138 | * v7_coherent_user_range(start,end) | |
139 | * | |
140 | * Ensure that the I and D caches are coherent within specified | |
141 | * region. This is typically used when code has been written to | |
142 | * a memory region, and will be executed. | |
143 | * | |
144 | * - start - virtual start address of region | |
145 | * - end - virtual end address of region | |
146 | * | |
147 | * It is assumed that: | |
148 | * - the Icache does not read data from the write buffer | |
149 | */ | |
150 | ENTRY(v7_coherent_user_range) | |
151 | dcache_line_size r2, r3 | |
152 | sub r3, r2, #1 | |
153 | bic r0, r0, r3 | |
154 | 1: mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification | |
155 | dsb | |
156 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I line | |
157 | add r0, r0, r2 | |
158 | cmp r0, r1 | |
159 | blo 1b | |
160 | mov r0, #0 | |
161 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB | |
162 | dsb | |
163 | isb | |
164 | mov pc, lr | |
165 | ENDPROC(v7_coherent_kern_range) | |
166 | ENDPROC(v7_coherent_user_range) | |
167 | ||
168 | /* | |
169 | * v7_flush_kern_dcache_page(kaddr) | |
170 | * | |
171 | * Ensure that the data held in the page kaddr is written back | |
172 | * to the page in question. | |
173 | * | |
174 | * - kaddr - kernel address (guaranteed to be page aligned) | |
175 | */ | |
176 | ENTRY(v7_flush_kern_dcache_page) | |
177 | dcache_line_size r2, r3 | |
178 | add r1, r0, #PAGE_SZ | |
179 | 1: | |
180 | mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line | |
181 | add r0, r0, r2 | |
182 | cmp r0, r1 | |
183 | blo 1b | |
184 | dsb | |
185 | mov pc, lr | |
186 | ENDPROC(v7_flush_kern_dcache_page) | |
187 | ||
188 | /* | |
189 | * v7_dma_inv_range(start,end) | |
190 | * | |
191 | * Invalidate the data cache within the specified region; we will | |
192 | * be performing a DMA operation in this region and we want to | |
193 | * purge old data in the cache. | |
194 | * | |
195 | * - start - virtual start address of region | |
196 | * - end - virtual end address of region | |
197 | */ | |
198 | ENTRY(v7_dma_inv_range) | |
199 | dcache_line_size r2, r3 | |
200 | sub r3, r2, #1 | |
201 | tst r0, r3 | |
202 | bic r0, r0, r3 | |
203 | mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line | |
204 | ||
205 | tst r1, r3 | |
206 | bic r1, r1, r3 | |
207 | mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line | |
208 | 1: | |
209 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line | |
210 | add r0, r0, r2 | |
211 | cmp r0, r1 | |
212 | blo 1b | |
213 | dsb | |
214 | mov pc, lr | |
215 | ENDPROC(v7_dma_inv_range) | |
216 | ||
217 | /* | |
218 | * v7_dma_clean_range(start,end) | |
219 | * - start - virtual start address of region | |
220 | * - end - virtual end address of region | |
221 | */ | |
222 | ENTRY(v7_dma_clean_range) | |
223 | dcache_line_size r2, r3 | |
224 | sub r3, r2, #1 | |
225 | bic r0, r0, r3 | |
226 | 1: | |
227 | mcr p15, 0, r0, c7, c10, 1 @ clean D / U line | |
228 | add r0, r0, r2 | |
229 | cmp r0, r1 | |
230 | blo 1b | |
231 | dsb | |
232 | mov pc, lr | |
233 | ENDPROC(v7_dma_clean_range) | |
234 | ||
235 | /* | |
236 | * v7_dma_flush_range(start,end) | |
237 | * - start - virtual start address of region | |
238 | * - end - virtual end address of region | |
239 | */ | |
240 | ENTRY(v7_dma_flush_range) | |
241 | dcache_line_size r2, r3 | |
242 | sub r3, r2, #1 | |
243 | bic r0, r0, r3 | |
244 | 1: | |
245 | mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line | |
246 | add r0, r0, r2 | |
247 | cmp r0, r1 | |
248 | blo 1b | |
249 | dsb | |
250 | mov pc, lr | |
251 | ENDPROC(v7_dma_flush_range) | |
252 | ||
253 | __INITDATA | |
254 | ||
255 | .type v7_cache_fns, #object | |
256 | ENTRY(v7_cache_fns) | |
257 | .long v7_flush_kern_cache_all | |
258 | .long v7_flush_user_cache_all | |
259 | .long v7_flush_user_cache_range | |
260 | .long v7_coherent_kern_range | |
261 | .long v7_coherent_user_range | |
262 | .long v7_flush_kern_dcache_page | |
263 | .long v7_dma_inv_range | |
264 | .long v7_dma_clean_range | |
265 | .long v7_dma_flush_range | |
266 | .size v7_cache_fns, . - v7_cache_fns |