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Added UID reading to SRI512, and reordered the output to reflect the
[proxmark3-svn] / fpga / lo_read.v
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6658905f 1//-----------------------------------------------------------------------------\r
2// The way that we connect things in low-frequency read mode. In this case\r
30f2a7d3 3// we are generating the 134 kHz or 125 kHz carrier, and running the\r
6658905f 4// unmodulated carrier at that frequency. The A/D samples at that same rate,\r
5// and the result is serialized.\r
6//\r
7// Jonathan Westhues, April 2006\r
8//-----------------------------------------------------------------------------\r
9\r
10module lo_read(\r
11 pck0, ck_1356meg, ck_1356megb,\r
12 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
13 adc_d, adc_clk,\r
14 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
15 cross_hi, cross_lo,\r
16 dbg,\r
30f2a7d3 17 lo_is_125khz, divisor\r
6658905f 18);\r
19 input pck0, ck_1356meg, ck_1356megb;\r
20 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
21 input [7:0] adc_d;\r
22 output adc_clk;\r
23 input ssp_dout;\r
24 output ssp_frame, ssp_din, ssp_clk;\r
25 input cross_hi, cross_lo;\r
26 output dbg;\r
27 input lo_is_125khz;\r
30f2a7d3 28 input [7:0] divisor;\r
6658905f 29\r
30// The low-frequency RFID stuff. This is relatively simple, because most\r
31// of the work happens on the ARM, and we just pass samples through. The\r
32// PCK0 must be divided down to generate the A/D clock, and from there by\r
33// a factor of 8 to generate the carrier (that we apply to the coil drivers).\r
34//\r
35// This is also where we decode the received synchronous serial port words,\r
36// to determine how to drive the output enables.\r
37\r
38// PCK0 will run at (PLL clock) / 4, or 24 MHz. That means that we can do\r
39// 125 kHz by dividing by a further factor of (8*12*2), or ~134 kHz by\r
40// dividing by a factor of (8*11*2) (for 136 kHz, ~2% error, tolerable).\r
41\r
6658905f 42reg [7:0] to_arm_shiftreg;\r
30f2a7d3 43reg [7:0] pck_divider;\r
44reg [6:0] ssp_divider;\r
45reg ant_lo;\r
6658905f 46\r
30f2a7d3 47always @(posedge pck0)\r
6658905f 48begin\r
30f2a7d3 49 if(pck_divider == 8'd0)\r
50 begin\r
51 pck_divider <= divisor[7:0];\r
52 ant_lo = !ant_lo;\r
53 if(ant_lo == 1'b0)\r
54 begin\r
55 ssp_divider <= 7'b0011111;\r
56 to_arm_shiftreg <= adc_d;\r
57 end\r
58 end\r
59 else\r
60 begin\r
61 pck_divider <= pck_divider - 1;\r
62 if(ssp_divider[6] == 1'b0)\r
63 begin\r
64 if (ssp_divider[1:0] == 1'b11) to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];\r
65 ssp_divider <= ssp_divider - 1;\r
66 end\r
67 end\r
6658905f 68end\r
69\r
6658905f 70assign ssp_din = to_arm_shiftreg[7];\r
30f2a7d3 71assign ssp_clk = pck_divider[1];\r
72assign ssp_frame = ~ssp_divider[5];\r
6658905f 73assign pwr_hi = 1'b0;\r
30f2a7d3 74assign pwr_lo = ant_lo;\r
75assign adc_clk = ~ant_lo;\r
6658905f 76assign dbg = adc_clk;\r
6658905f 77endmodule\r
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