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Added UID reading to SRI512, and reordered the output to reflect the
[proxmark3-svn] / fpga / lo_read.v
1 //-----------------------------------------------------------------------------
2 // The way that we connect things in low-frequency read mode. In this case
3 // we are generating the 134 kHz or 125 kHz carrier, and running the
4 // unmodulated carrier at that frequency. The A/D samples at that same rate,
5 // and the result is serialized.
6 //
7 // Jonathan Westhues, April 2006
8 //-----------------------------------------------------------------------------
9
10 module lo_read(
11 pck0, ck_1356meg, ck_1356megb,
12 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
13 adc_d, adc_clk,
14 ssp_frame, ssp_din, ssp_dout, ssp_clk,
15 cross_hi, cross_lo,
16 dbg,
17 lo_is_125khz, divisor
18 );
19 input pck0, ck_1356meg, ck_1356megb;
20 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
21 input [7:0] adc_d;
22 output adc_clk;
23 input ssp_dout;
24 output ssp_frame, ssp_din, ssp_clk;
25 input cross_hi, cross_lo;
26 output dbg;
27 input lo_is_125khz;
28 input [7:0] divisor;
29
30 // The low-frequency RFID stuff. This is relatively simple, because most
31 // of the work happens on the ARM, and we just pass samples through. The
32 // PCK0 must be divided down to generate the A/D clock, and from there by
33 // a factor of 8 to generate the carrier (that we apply to the coil drivers).
34 //
35 // This is also where we decode the received synchronous serial port words,
36 // to determine how to drive the output enables.
37
38 // PCK0 will run at (PLL clock) / 4, or 24 MHz. That means that we can do
39 // 125 kHz by dividing by a further factor of (8*12*2), or ~134 kHz by
40 // dividing by a factor of (8*11*2) (for 136 kHz, ~2% error, tolerable).
41
42 reg [7:0] to_arm_shiftreg;
43 reg [7:0] pck_divider;
44 reg [6:0] ssp_divider;
45 reg ant_lo;
46
47 always @(posedge pck0)
48 begin
49 if(pck_divider == 8'd0)
50 begin
51 pck_divider <= divisor[7:0];
52 ant_lo = !ant_lo;
53 if(ant_lo == 1'b0)
54 begin
55 ssp_divider <= 7'b0011111;
56 to_arm_shiftreg <= adc_d;
57 end
58 end
59 else
60 begin
61 pck_divider <= pck_divider - 1;
62 if(ssp_divider[6] == 1'b0)
63 begin
64 if (ssp_divider[1:0] == 1'b11) to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
65 ssp_divider <= ssp_divider - 1;
66 end
67 end
68 end
69
70 assign ssp_din = to_arm_shiftreg[7];
71 assign ssp_clk = pck_divider[1];
72 assign ssp_frame = ~ssp_divider[5];
73 assign pwr_hi = 1'b0;
74 assign pwr_lo = ant_lo;
75 assign adc_clk = ~ant_lo;
76 assign dbg = adc_clk;
77 endmodule
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