]> git.zerfleddert.de Git - proxmark3-svn/blame - armsrc/lfops.c
Merge branch 'master' of https://github.com/Proxmark/proxmark3
[proxmark3-svn] / armsrc / lfops.c
CommitLineData
15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
15c4dc5a 6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
15c4dc5a 12#include "apps.h"
f7e3ed82 13#include "util.h"
15c4dc5a 14#include "hitag2.h"
15#include "crc16.h"
9ab7a6c7 16#include "string.h"
7db5f1ca 17#include "lfdemod.h"
15c4dc5a 18
b2256785
MHS
19
20/**
21* Does the sample acquisition. If threshold is specified, the actual sampling
22* is not commenced until the threshold has been reached.
23* @param trigger_threshold - the threshold
24* @param silent - is true, now outputs are made. If false, dbprints the status
25*/
f97d4e23 26void DoAcquisition125k_internal(int trigger_threshold,bool silent)
69d88ec4 27{
ae8e8a43
MHS
28 uint8_t *dest = (uint8_t *)BigBuf;
29 int n = sizeof(BigBuf);
30 int i;
31
32 memset(dest, 0, n);
33 i = 0;
34 for(;;) {
35 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
36 AT91C_BASE_SSC->SSC_THR = 0x43;
37 LED_D_ON();
38 }
39 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
40 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
41 LED_D_OFF();
42 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
43 continue;
44 else
45 trigger_threshold = -1;
46 if (++i >= n) break;
47 }
48 }
49 if(!silent)
50 {
51 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
52 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
53
54 }
69d88ec4 55}
b2256785
MHS
56/**
57* Perform sample aquisition.
58*/
f97d4e23 59void DoAcquisition125k(int trigger_threshold)
69d88ec4 60{
ae8e8a43 61 DoAcquisition125k_internal(trigger_threshold, false);
69d88ec4
MHS
62}
63
b2256785
MHS
64/**
65* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
66* if not already loaded, sets divisor and starts up the antenna.
67* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
68* 0 or 95 ==> 125 KHz
69*
70**/
b014c96d 71void LFSetupFPGAForADC(int divisor, bool lf_field)
15c4dc5a 72{
ae8e8a43
MHS
73 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
74 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
75 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
76 else if (divisor == 0)
77 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
78 else
79 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
80
81 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
82
83 // Connect the A/D to the peak-detected low-frequency path.
84 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
85 // Give it a bit of time for the resonant antenna to settle.
86 SpinDelay(50);
87 // Now set up the SSC to get the ADC samples that are now streaming at us.
88 FpgaSetupSsc();
15c4dc5a 89}
b2256785
MHS
90/**
91* Initializes the FPGA, and acquires the samples.
92**/
69d88ec4 93void AcquireRawAdcSamples125k(int divisor)
15c4dc5a 94{
ae8e8a43
MHS
95 LFSetupFPGAForADC(divisor, true);
96 // Now call the acquisition routine
97 DoAcquisition125k_internal(-1,false);
b014c96d 98}
b2256785
MHS
99/**
100* Initializes the FPGA for snoop-mode, and acquires the samples.
101**/
102
b014c96d 103void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
104{
ae8e8a43
MHS
105 LFSetupFPGAForADC(divisor, false);
106 DoAcquisition125k(trigger_threshold);
15c4dc5a 107}
108
f7e3ed82 109void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
15c4dc5a 110{
15c4dc5a 111
ae8e8a43
MHS
112 /* Make sure the tag is reset */
113 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
115 SpinDelay(2500);
e30c654b 116
b2256785 117
ae8e8a43
MHS
118 int divisor_used = 95; // 125 KHz
119 // see if 'h' was specified
b2256785 120
ae8e8a43
MHS
121 if (command[strlen((char *) command) - 1] == 'h')
122 divisor_used = 88; // 134.8 KHz
15c4dc5a 123
15c4dc5a 124
ae8e8a43
MHS
125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
127 // Give it a bit of time for the resonant antenna to settle.
128 SpinDelay(50);
b2256785 129
ae8e8a43
MHS
130 // And a little more time for the tag to fully power up
131 SpinDelay(2000);
15c4dc5a 132
ae8e8a43
MHS
133 // Now set up the SSC to get the ADC samples that are now streaming at us.
134 FpgaSetupSsc();
15c4dc5a 135
ae8e8a43
MHS
136 // now modulate the reader field
137 while(*command != '\0' && *command != ' ') {
138 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
139 LED_D_OFF();
140 SpinDelayUs(delay_off);
141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
15c4dc5a 142
ae8e8a43
MHS
143 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
144 LED_D_ON();
145 if(*(command++) == '0')
146 SpinDelayUs(period_0);
147 else
148 SpinDelayUs(period_1);
149 }
150 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
151 LED_D_OFF();
152 SpinDelayUs(delay_off);
153 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
15c4dc5a 154
ae8e8a43 155 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
15c4dc5a 156
ae8e8a43
MHS
157 // now do the read
158 DoAcquisition125k(-1);
15c4dc5a 159}
160
161/* blank r/w tag data stream
162...0000000000000000 01111111
1631010101010101010101010101010101010101010101010101010101010101010
1640011010010100001
16501111111
166101010101010101[0]000...
167
168[5555fe852c5555555555555555fe0000]
169*/
170void ReadTItag(void)
171{
ae8e8a43
MHS
172 // some hardcoded initial params
173 // when we read a TI tag we sample the zerocross line at 2Mhz
174 // TI tags modulate a 1 as 16 cycles of 123.2Khz
175 // TI tags modulate a 0 as 16 cycles of 134.2Khz
176#define FSAMPLE 2000000
177#define FREQLO 123200
178#define FREQHI 134200
179
180 signed char *dest = (signed char *)BigBuf;
181 int n = sizeof(BigBuf);
ae8e8a43
MHS
182
183 // 128 bit shift register [shift3:shift2:shift1:shift0]
184 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
185
186 int i, cycles=0, samples=0;
187 // how many sample points fit in 16 cycles of each frequency
188 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
189 // when to tell if we're close enough to one freq or another
190 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
191
192 // TI tags charge at 134.2Khz
193 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
194 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
195
196 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
197 // connects to SSP_DIN and the SSP_DOUT logic level controls
198 // whether we're modulating the antenna (high)
199 // or listening to the antenna (low)
200 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
201
202 // get TI tag data into the buffer
203 AcquireTiType();
204
205 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
206
207 for (i=0; i<n-1; i++) {
208 // count cycles by looking for lo to hi zero crossings
209 if ( (dest[i]<0) && (dest[i+1]>0) ) {
210 cycles++;
211 // after 16 cycles, measure the frequency
212 if (cycles>15) {
213 cycles=0;
214 samples=i-samples; // number of samples in these 16 cycles
215
216 // TI bits are coming to us lsb first so shift them
217 // right through our 128 bit right shift register
218 shift0 = (shift0>>1) | (shift1 << 31);
219 shift1 = (shift1>>1) | (shift2 << 31);
220 shift2 = (shift2>>1) | (shift3 << 31);
221 shift3 >>= 1;
222
223 // check if the cycles fall close to the number
224 // expected for either the low or high frequency
225 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
226 // low frequency represents a 1
227 shift3 |= (1<<31);
228 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
229 // high frequency represents a 0
230 } else {
231 // probably detected a gay waveform or noise
232 // use this as gaydar or discard shift register and start again
233 shift3 = shift2 = shift1 = shift0 = 0;
234 }
235 samples = i;
236
237 // for each bit we receive, test if we've detected a valid tag
238
239 // if we see 17 zeroes followed by 6 ones, we might have a tag
240 // remember the bits are backwards
241 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
242 // if start and end bytes match, we have a tag so break out of the loop
243 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
244 cycles = 0xF0B; //use this as a flag (ugly but whatever)
245 break;
246 }
247 }
248 }
249 }
250 }
251
252 // if flag is set we have a tag
253 if (cycles!=0xF0B) {
254 DbpString("Info: No valid tag detected.");
255 } else {
256 // put 64 bit data into shift1 and shift0
257 shift0 = (shift0>>24) | (shift1 << 8);
258 shift1 = (shift1>>24) | (shift2 << 8);
259
260 // align 16 bit crc into lower half of shift2
261 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
262
263 // if r/w tag, check ident match
264 if ( shift3&(1<<15) ) {
265 DbpString("Info: TI tag is rewriteable");
266 // only 15 bits compare, last bit of ident is not valid
267 if ( ((shift3>>16)^shift0)&0x7fff ) {
268 DbpString("Error: Ident mismatch!");
269 } else {
270 DbpString("Info: TI tag ident is valid");
271 }
272 } else {
273 DbpString("Info: TI tag is readonly");
274 }
275
276 // WARNING the order of the bytes in which we calc crc below needs checking
277 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
278 // bytes in reverse or something
279 // calculate CRC
280 uint32_t crc=0;
281
282 crc = update_crc16(crc, (shift0)&0xff);
283 crc = update_crc16(crc, (shift0>>8)&0xff);
284 crc = update_crc16(crc, (shift0>>16)&0xff);
285 crc = update_crc16(crc, (shift0>>24)&0xff);
286 crc = update_crc16(crc, (shift1)&0xff);
287 crc = update_crc16(crc, (shift1>>8)&0xff);
288 crc = update_crc16(crc, (shift1>>16)&0xff);
289 crc = update_crc16(crc, (shift1>>24)&0xff);
290
291 Dbprintf("Info: Tag data: %x%08x, crc=%x",
292 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
293 if (crc != (shift2&0xffff)) {
294 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
295 } else {
296 DbpString("Info: CRC is good");
297 }
298 }
15c4dc5a 299}
300
f7e3ed82 301void WriteTIbyte(uint8_t b)
15c4dc5a 302{
ae8e8a43
MHS
303 int i = 0;
304
305 // modulate 8 bits out to the antenna
306 for (i=0; i<8; i++)
307 {
308 if (b&(1<<i)) {
309 // stop modulating antenna
310 LOW(GPIO_SSC_DOUT);
311 SpinDelayUs(1000);
312 // modulate antenna
313 HIGH(GPIO_SSC_DOUT);
314 SpinDelayUs(1000);
315 } else {
316 // stop modulating antenna
317 LOW(GPIO_SSC_DOUT);
318 SpinDelayUs(300);
319 // modulate antenna
320 HIGH(GPIO_SSC_DOUT);
321 SpinDelayUs(1700);
322 }
323 }
15c4dc5a 324}
325
326void AcquireTiType(void)
327{
ae8e8a43
MHS
328 int i, j, n;
329 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
330 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
331#define TIBUFLEN 1250
332
333 // clear buffer
334 memset(BigBuf,0,sizeof(BigBuf));
335
336 // Set up the synchronous serial port
337 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
338 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
345 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
346
347 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
348 // 48/2 = 24 MHz clock must be divided by 12
349 AT91C_BASE_SSC->SSC_CMR = 12;
350
351 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
352 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
353 AT91C_BASE_SSC->SSC_TCMR = 0;
354 AT91C_BASE_SSC->SSC_TFMR = 0;
355
356 LED_D_ON();
357
358 // modulate antenna
359 HIGH(GPIO_SSC_DOUT);
360
361 // Charge TI tag for 50ms.
362 SpinDelay(50);
363
364 // stop modulating antenna and listen
365 LOW(GPIO_SSC_DOUT);
366
367 LED_D_OFF();
368
369 i = 0;
370 for(;;) {
371 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
372 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
373 i++; if(i >= TIBUFLEN) break;
374 }
375 WDT_HIT();
376 }
377
378 // return stolen pin to SSP
379 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
380 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
381
382 char *dest = (char *)BigBuf;
383 n = TIBUFLEN*32;
384 // unpack buffer
385 for (i=TIBUFLEN-1; i>=0; i--) {
386 for (j=0; j<32; j++) {
387 if(BigBuf[i] & (1 << j)) {
388 dest[--n] = 1;
389 } else {
390 dest[--n] = -1;
391 }
392 }
393 }
15c4dc5a 394}
395
396// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
397// if crc provided, it will be written with the data verbatim (even if bogus)
398// if not provided a valid crc will be computed from the data and written.
f7e3ed82 399void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
15c4dc5a 400{
ae8e8a43
MHS
401 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
402 if(crc == 0) {
403 crc = update_crc16(crc, (idlo)&0xff);
404 crc = update_crc16(crc, (idlo>>8)&0xff);
405 crc = update_crc16(crc, (idlo>>16)&0xff);
406 crc = update_crc16(crc, (idlo>>24)&0xff);
407 crc = update_crc16(crc, (idhi)&0xff);
408 crc = update_crc16(crc, (idhi>>8)&0xff);
409 crc = update_crc16(crc, (idhi>>16)&0xff);
410 crc = update_crc16(crc, (idhi>>24)&0xff);
411 }
412 Dbprintf("Writing to tag: %x%08x, crc=%x",
413 (unsigned int) idhi, (unsigned int) idlo, crc);
414
415 // TI tags charge at 134.2Khz
416 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
417 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
418 // connects to SSP_DIN and the SSP_DOUT logic level controls
419 // whether we're modulating the antenna (high)
420 // or listening to the antenna (low)
421 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
422 LED_A_ON();
423
424 // steal this pin from the SSP and use it to control the modulation
425 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
426 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
427
428 // writing algorithm:
429 // a high bit consists of a field off for 1ms and field on for 1ms
430 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
431 // initiate a charge time of 50ms (field on) then immediately start writing bits
432 // start by writing 0xBB (keyword) and 0xEB (password)
433 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
434 // finally end with 0x0300 (write frame)
435 // all data is sent lsb firts
436 // finish with 15ms programming time
437
438 // modulate antenna
439 HIGH(GPIO_SSC_DOUT);
440 SpinDelay(50); // charge time
441
442 WriteTIbyte(0xbb); // keyword
443 WriteTIbyte(0xeb); // password
444 WriteTIbyte( (idlo )&0xff );
445 WriteTIbyte( (idlo>>8 )&0xff );
446 WriteTIbyte( (idlo>>16)&0xff );
447 WriteTIbyte( (idlo>>24)&0xff );
448 WriteTIbyte( (idhi )&0xff );
449 WriteTIbyte( (idhi>>8 )&0xff );
450 WriteTIbyte( (idhi>>16)&0xff );
451 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
452 WriteTIbyte( (crc )&0xff ); // crc lo
453 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
454 WriteTIbyte(0x00); // write frame lo
455 WriteTIbyte(0x03); // write frame hi
456 HIGH(GPIO_SSC_DOUT);
457 SpinDelay(50); // programming time
458
459 LED_A_OFF();
460
461 // get TI tag data into the buffer
462 AcquireTiType();
463
464 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
465 DbpString("Now use tiread to check");
15c4dc5a 466}
467
468void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
469{
ae8e8a43
MHS
470 int i;
471 uint8_t *tab = (uint8_t *)BigBuf;
d19929cb 472
ae8e8a43
MHS
473 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
474 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
d19929cb 475
ae8e8a43 476 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
d19929cb 477
ae8e8a43
MHS
478 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
479 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
d19929cb 480
15c4dc5a 481#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
482#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
d19929cb 483
ae8e8a43
MHS
484 i = 0;
485 for(;;) {
486 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
487 if(BUTTON_PRESS()) {
488 DbpString("Stopped");
489 return;
490 }
491 WDT_HIT();
492 }
d19929cb 493
ae8e8a43
MHS
494 if (ledcontrol)
495 LED_D_ON();
d19929cb 496
ae8e8a43
MHS
497 if(tab[i])
498 OPEN_COIL();
499 else
500 SHORT_COIL();
d19929cb 501
ae8e8a43
MHS
502 if (ledcontrol)
503 LED_D_OFF();
d19929cb 504
ae8e8a43
MHS
505 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
506 if(BUTTON_PRESS()) {
507 DbpString("Stopped");
508 return;
509 }
510 WDT_HIT();
511 }
d19929cb 512
ae8e8a43
MHS
513 i++;
514 if(i == period) {
515 i = 0;
516 if (gap) {
517 SHORT_COIL();
518 SpinDelayUs(gap);
519 }
520 }
521 }
15c4dc5a 522}
523
15c4dc5a 524#define DEBUG_FRAME_CONTENTS 1
525void SimulateTagLowFrequencyBidir(int divisor, int t0)
526{
15c4dc5a 527}
528
529// compose fc/8 fc/10 waveform
530static void fc(int c, int *n) {
ae8e8a43
MHS
531 uint8_t *dest = (uint8_t *)BigBuf;
532 int idx;
533
534 // for when we want an fc8 pattern every 4 logical bits
535 if(c==0) {
536 dest[((*n)++)]=1;
537 dest[((*n)++)]=1;
538 dest[((*n)++)]=0;
539 dest[((*n)++)]=0;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 }
545 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
546 if(c==8) {
547 for (idx=0; idx<6; idx++) {
548 dest[((*n)++)]=1;
549 dest[((*n)++)]=1;
550 dest[((*n)++)]=0;
551 dest[((*n)++)]=0;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 }
557 }
558
559 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
560 if(c==10) {
561 for (idx=0; idx<5; idx++) {
562 dest[((*n)++)]=1;
563 dest[((*n)++)]=1;
564 dest[((*n)++)]=1;
565 dest[((*n)++)]=0;
566 dest[((*n)++)]=0;
567 dest[((*n)++)]=0;
568 dest[((*n)++)]=0;
569 dest[((*n)++)]=0;
570 dest[((*n)++)]=0;
571 dest[((*n)++)]=0;
572 }
573 }
15c4dc5a 574}
575
576// prepare a waveform pattern in the buffer based on the ID given then
577// simulate a HID tag until the button is pressed
578void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
579{
ae8e8a43
MHS
580 int n=0, i=0;
581 /*
582 HID tag bitstream format
583 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
584 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
585 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
586 A fc8 is inserted before every 4 bits
587 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
588 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
589 */
590
591 if (hi>0xFFF) {
592 DbpString("Tags can only have 44 bits.");
593 return;
594 }
595 fc(0,&n);
596 // special start of frame marker containing invalid bit sequences
597 fc(8, &n); fc(8, &n); // invalid
598 fc(8, &n); fc(10, &n); // logical 0
599 fc(10, &n); fc(10, &n); // invalid
600 fc(8, &n); fc(10, &n); // logical 0
601
602 WDT_HIT();
603 // manchester encode bits 43 to 32
604 for (i=11; i>=0; i--) {
605 if ((i%4)==3) fc(0,&n);
606 if ((hi>>i)&1) {
607 fc(10, &n); fc(8, &n); // low-high transition
608 } else {
609 fc(8, &n); fc(10, &n); // high-low transition
610 }
611 }
612
613 WDT_HIT();
614 // manchester encode bits 31 to 0
615 for (i=31; i>=0; i--) {
616 if ((i%4)==3) fc(0,&n);
617 if ((lo>>i)&1) {
618 fc(10, &n); fc(8, &n); // low-high transition
619 } else {
620 fc(8, &n); fc(10, &n); // high-low transition
621 }
622 }
623
624 if (ledcontrol)
625 LED_A_ON();
3fe4ff4f 626
ae8e8a43
MHS
627 SimulateTagLowFrequency(n, 0, ledcontrol);
628
629 if (ledcontrol)
630 LED_A_OFF();
15c4dc5a 631}
eb191de6 632
b3b70669 633// loop to get raw HID waveform then FSK demodulate the TAG ID from it
69d88ec4
MHS
634void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
635{
ae8e8a43
MHS
636 uint8_t *dest = (uint8_t *)BigBuf;
637
638 size_t size=0; //, found=0;
639 uint32_t hi2=0, hi=0, lo=0;
640
641 // Configure to go in 125Khz listen mode
642 LFSetupFPGAForADC(95, true);
643
644 while(!BUTTON_PRESS()) {
645
646 WDT_HIT();
647 if (ledcontrol) LED_A_ON();
648
649 DoAcquisition125k_internal(-1,true);
650 size = sizeof(BigBuf);
651 if (size < 2000) continue;
652 // FSK demodulator
653
654 int bitLen = HIDdemodFSK(dest,size,&hi2,&hi,&lo);
655
656 WDT_HIT();
657
658 if (bitLen>0 && lo>0){
659 // final loop, go over previously decoded manchester data and decode into usable tag ID
660 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
661 if (hi2 != 0){ //extra large HID tags
662 Dbprintf("TAG ID: %x%08x%08x (%d)",
663 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
664 }else { //standard HID tags <38 bits
665 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
666 uint8_t bitlen = 0;
667 uint32_t fc = 0;
668 uint32_t cardnum = 0;
669 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
670 uint32_t lo2=0;
671 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
672 uint8_t idx3 = 1;
673 while(lo2>1){ //find last bit set to 1 (format len bit)
674 lo2=lo2>>1;
675 idx3++;
676 }
677 bitlen =idx3+19;
678 fc =0;
679 cardnum=0;
680 if(bitlen==26){
681 cardnum = (lo>>1)&0xFFFF;
682 fc = (lo>>17)&0xFF;
683 }
684 if(bitlen==37){
685 cardnum = (lo>>1)&0x7FFFF;
686 fc = ((hi&0xF)<<12)|(lo>>20);
687 }
688 if(bitlen==34){
689 cardnum = (lo>>1)&0xFFFF;
690 fc= ((hi&1)<<15)|(lo>>17);
691 }
692 if(bitlen==35){
693 cardnum = (lo>>1)&0xFFFFF;
694 fc = ((hi&1)<<11)|(lo>>21);
695 }
696 }
697 else { //if bit 38 is not set then 37 bit format is used
698 bitlen= 37;
699 fc =0;
700 cardnum=0;
701 if(bitlen==37){
702 cardnum = (lo>>1)&0x7FFFF;
703 fc = ((hi&0xF)<<12)|(lo>>20);
704 }
705 }
706 //Dbprintf("TAG ID: %x%08x (%d)",
707 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
708 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
709 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
710 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
711 }
712 if (findone){
713 if (ledcontrol) LED_A_OFF();
714 return;
715 }
716 // reset
717 hi2 = hi = lo = 0;
718 }
719 WDT_HIT();
ae8e8a43
MHS
720 }
721 DbpString("Stopped");
722 if (ledcontrol) LED_A_OFF();
eb191de6 723}
724
66707a3b 725void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
eb191de6 726{
ae8e8a43
MHS
727 uint8_t *dest = (uint8_t *)BigBuf;
728
729 size_t size=0; //, found=0;
730 uint32_t bitLen=0;
731 int clk=0, invert=0, errCnt=0;
732 uint64_t lo=0;
733 // Configure to go in 125Khz listen mode
734 LFSetupFPGAForADC(95, true);
735
736 while(!BUTTON_PRESS()) {
737
738 WDT_HIT();
739 if (ledcontrol) LED_A_ON();
740
741 DoAcquisition125k_internal(-1,true);
742 size = sizeof(BigBuf);
743 if (size < 2000) continue;
744 // FSK demodulator
745 //int askmandemod(uint8_t *BinStream,uint32_t *BitLen,int *clk, int *invert);
746 bitLen=size;
747 //Dbprintf("DEBUG: Buffer got");
748 errCnt = askmandemod(dest,&bitLen,&clk,&invert); //HIDdemodFSK(dest,size,&hi2,&hi,&lo);
749 //Dbprintf("DEBUG: ASK Got");
750 WDT_HIT();
751
752 if (errCnt>=0){
753 lo = Em410xDecode(dest,bitLen);
754 //Dbprintf("DEBUG: EM GOT");
755 //printEM410x(lo);
756 if (lo>0){
757 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",(uint32_t)(lo>>32),(uint32_t)lo,(uint32_t)(lo&0xFFFF),(uint32_t)((lo>>16LL) & 0xFF),(uint32_t)(lo & 0xFFFFFF));
758 }
759 if (findone){
760 if (ledcontrol) LED_A_OFF();
761 return;
762 }
763 } else{
764 //Dbprintf("DEBUG: No Tag");
765 }
766 WDT_HIT();
767 lo = 0;
768 clk=0;
769 invert=0;
770 errCnt=0;
771 size=0;
772 //SpinDelay(50);
773 }
774 DbpString("Stopped");
775 if (ledcontrol) LED_A_OFF();
15c4dc5a 776}
69d88ec4 777
a1f3bb12 778void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
eb191de6 779{
ae8e8a43 780 uint8_t *dest = (uint8_t *)BigBuf;
ae8e8a43
MHS
781 int idx=0;
782 uint32_t code=0, code2=0;
783 uint8_t version=0;
784 uint8_t facilitycode=0;
785 uint16_t number=0;
786 // Configure to go in 125Khz listen mode
787 LFSetupFPGAForADC(95, true);
788
789 while(!BUTTON_PRESS()) {
790 WDT_HIT();
791 if (ledcontrol) LED_A_ON();
792 DoAcquisition125k_internal(-1,true);
793 //fskdemod and get start index
794 WDT_HIT();
6ca4c646 795 idx = IOdemodFSK(dest,sizeof(BigBuf));
ae8e8a43
MHS
796 if (idx>0){
797 //valid tag found
798
799 //Index map
800 //0 10 20 30 40 50 60
801 //| | | | | | |
802 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
803 //-----------------------------------------------------------------------------
804 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
805 //
806 //XSF(version)facility:codeone+codetwo
807 //Handle the data
808 if(findone){ //only print binary if we are doing one
809 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
810 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
811 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
812 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
813 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
814 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
815 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
816 }
817 code = bytebits_to_byte(dest+idx,32);
818 code2 = bytebits_to_byte(dest+idx+32,32);
819 version = bytebits_to_byte(dest+idx+27,8); //14,4
820 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
821 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
822
823 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
824 // if we're only looking for one tag
825 if (findone){
826 if (ledcontrol) LED_A_OFF();
827 //LED_A_OFF();
828 return;
829 }
830 code=code2=0;
831 version=facilitycode=0;
832 number=0;
833 idx=0;
834 }
835 WDT_HIT();
836 }
837 DbpString("Stopped");
838 if (ledcontrol) LED_A_OFF();
eb191de6 839}
a1f3bb12 840
2d4eae76 841/*------------------------------
842 * T5555/T5557/T5567 routines
843 *------------------------------
844 */
845
846/* T55x7 configuration register definitions */
847#define T55x7_POR_DELAY 0x00000001
848#define T55x7_ST_TERMINATOR 0x00000008
849#define T55x7_PWD 0x00000010
850#define T55x7_MAXBLOCK_SHIFT 5
851#define T55x7_AOR 0x00000200
852#define T55x7_PSKCF_RF_2 0
853#define T55x7_PSKCF_RF_4 0x00000400
854#define T55x7_PSKCF_RF_8 0x00000800
855#define T55x7_MODULATION_DIRECT 0
856#define T55x7_MODULATION_PSK1 0x00001000
857#define T55x7_MODULATION_PSK2 0x00002000
858#define T55x7_MODULATION_PSK3 0x00003000
859#define T55x7_MODULATION_FSK1 0x00004000
860#define T55x7_MODULATION_FSK2 0x00005000
861#define T55x7_MODULATION_FSK1a 0x00006000
862#define T55x7_MODULATION_FSK2a 0x00007000
863#define T55x7_MODULATION_MANCHESTER 0x00008000
864#define T55x7_MODULATION_BIPHASE 0x00010000
865#define T55x7_BITRATE_RF_8 0
866#define T55x7_BITRATE_RF_16 0x00040000
867#define T55x7_BITRATE_RF_32 0x00080000
868#define T55x7_BITRATE_RF_40 0x000C0000
869#define T55x7_BITRATE_RF_50 0x00100000
870#define T55x7_BITRATE_RF_64 0x00140000
871#define T55x7_BITRATE_RF_100 0x00180000
872#define T55x7_BITRATE_RF_128 0x001C0000
873
874/* T5555 (Q5) configuration register definitions */
875#define T5555_ST_TERMINATOR 0x00000001
876#define T5555_MAXBLOCK_SHIFT 0x00000001
877#define T5555_MODULATION_MANCHESTER 0
878#define T5555_MODULATION_PSK1 0x00000010
879#define T5555_MODULATION_PSK2 0x00000020
880#define T5555_MODULATION_PSK3 0x00000030
881#define T5555_MODULATION_FSK1 0x00000040
882#define T5555_MODULATION_FSK2 0x00000050
883#define T5555_MODULATION_BIPHASE 0x00000060
884#define T5555_MODULATION_DIRECT 0x00000070
885#define T5555_INVERT_OUTPUT 0x00000080
886#define T5555_PSK_RF_2 0
887#define T5555_PSK_RF_4 0x00000100
888#define T5555_PSK_RF_8 0x00000200
889#define T5555_USE_PWD 0x00000400
890#define T5555_USE_AOR 0x00000800
891#define T5555_BITRATE_SHIFT 12
892#define T5555_FAST_WRITE 0x00004000
893#define T5555_PAGE_SELECT 0x00008000
894
895/*
896 * Relevant times in microsecond
897 * To compensate antenna falling times shorten the write times
898 * and enlarge the gap ones.
899 */
900#define START_GAP 250
901#define WRITE_GAP 160
902#define WRITE_0 144 // 192
903#define WRITE_1 400 // 432 for T55x7; 448 for E5550
904
905// Write one bit to card
906void T55xxWriteBit(int bit)
ec09b62d 907{
ae8e8a43
MHS
908 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
909 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
910 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
911 if (bit == 0)
912 SpinDelayUs(WRITE_0);
913 else
914 SpinDelayUs(WRITE_1);
915 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
916 SpinDelayUs(WRITE_GAP);
ec09b62d 917}
918
2d4eae76 919// Write one card block in page 0, no lock
54a942b0 920void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 921{
ae8e8a43
MHS
922 //unsigned int i; //enio adjustment 12/10/14
923 uint32_t i;
924
925 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
926 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
927 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
928
929 // Give it a bit of time for the resonant antenna to settle.
930 // And for the tag to fully power up
931 SpinDelay(150);
932
933 // Now start writting
934 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
935 SpinDelayUs(START_GAP);
936
937 // Opcode
938 T55xxWriteBit(1);
939 T55xxWriteBit(0); //Page 0
940 if (PwdMode == 1){
941 // Pwd
942 for (i = 0x80000000; i != 0; i >>= 1)
943 T55xxWriteBit(Pwd & i);
944 }
945 // Lock bit
946 T55xxWriteBit(0);
947
948 // Data
54a942b0 949 for (i = 0x80000000; i != 0; i >>= 1)
ae8e8a43
MHS
950 T55xxWriteBit(Data & i);
951
952 // Block
953 for (i = 0x04; i != 0; i >>= 1)
954 T55xxWriteBit(Block & i);
955
956 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
957 // so wait a little more)
958 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
959 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
960 SpinDelay(20);
961 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
ec09b62d 962}
963
54a942b0 964// Read one card block in page 0
965void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 966{
ae8e8a43
MHS
967 uint8_t *dest = (uint8_t *)BigBuf;
968 //int m=0, i=0; //enio adjustment 12/10/14
969 uint32_t m=0, i=0;
970 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
971 m = sizeof(BigBuf);
972 // Clear destination buffer before sending the command
973 memset(dest, 128, m);
974 // Connect the A/D to the peak-detected low-frequency path.
975 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
976 // Now set up the SSC to get the ADC samples that are now streaming at us.
977 FpgaSetupSsc();
978
979 LED_D_ON();
980 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
981 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
982
983 // Give it a bit of time for the resonant antenna to settle.
984 // And for the tag to fully power up
985 SpinDelay(150);
986
987 // Now start writting
988 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
989 SpinDelayUs(START_GAP);
990
991 // Opcode
992 T55xxWriteBit(1);
993 T55xxWriteBit(0); //Page 0
994 if (PwdMode == 1){
995 // Pwd
996 for (i = 0x80000000; i != 0; i >>= 1)
997 T55xxWriteBit(Pwd & i);
998 }
999 // Lock bit
1000 T55xxWriteBit(0);
1001 // Block
1002 for (i = 0x04; i != 0; i >>= 1)
1003 T55xxWriteBit(Block & i);
1004
1005 // Turn field on to read the response
1006 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1007 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1008
1009 // Now do the acquisition
1010 i = 0;
1011 for(;;) {
1012 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1013 AT91C_BASE_SSC->SSC_THR = 0x43;
1014 }
1015 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1016 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1017 // we don't care about actual value, only if it's more or less than a
1018 // threshold essentially we capture zero crossings for later analysis
1019 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1020 i++;
1021 if (i >= m) break;
1022 }
1023 }
1024
1025 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1026 LED_D_OFF();
1027 DbpString("DONE!");
54a942b0 1028}
2d4eae76 1029
54a942b0 1030// Read card traceability data (page 1)
1031void T55xxReadTrace(void){
ae8e8a43
MHS
1032 uint8_t *dest = (uint8_t *)BigBuf;
1033 int m=0, i=0;
1034
1035 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1036 m = sizeof(BigBuf);
1037 // Clear destination buffer before sending the command
1038 memset(dest, 128, m);
1039 // Connect the A/D to the peak-detected low-frequency path.
1040 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1041 // Now set up the SSC to get the ADC samples that are now streaming at us.
1042 FpgaSetupSsc();
1043
1044 LED_D_ON();
1045 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1046 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1047
1048 // Give it a bit of time for the resonant antenna to settle.
1049 // And for the tag to fully power up
1050 SpinDelay(150);
1051
1052 // Now start writting
1053 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1054 SpinDelayUs(START_GAP);
1055
1056 // Opcode
1057 T55xxWriteBit(1);
1058 T55xxWriteBit(1); //Page 1
1059
1060 // Turn field on to read the response
1061 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1062 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1063
1064 // Now do the acquisition
1065 i = 0;
1066 for(;;) {
1067 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1068 AT91C_BASE_SSC->SSC_THR = 0x43;
1069 }
1070 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1071 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1072 i++;
1073 if (i >= m) break;
1074 }
1075 }
1076
1077 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1078 LED_D_OFF();
1079 DbpString("DONE!");
54a942b0 1080}
ec09b62d 1081
54a942b0 1082/*-------------- Cloning routines -----------*/
1083// Copy HID id to card and setup block 0 config
1084void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1085{
ae8e8a43
MHS
1086 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1087 int last_block = 0;
1088
1089 if (longFMT){
1090 // Ensure no more than 84 bits supplied
1091 if (hi2>0xFFFFF) {
1092 DbpString("Tags can only have 84 bits.");
1093 return;
1094 }
1095 // Build the 6 data blocks for supplied 84bit ID
1096 last_block = 6;
1097 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1098 for (int i=0;i<4;i++) {
1099 if (hi2 & (1<<(19-i)))
1100 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1101 else
1102 data1 |= (1<<((3-i)*2)); // 0 -> 01
1103 }
1104
1105 data2 = 0;
1106 for (int i=0;i<16;i++) {
1107 if (hi2 & (1<<(15-i)))
1108 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1109 else
1110 data2 |= (1<<((15-i)*2)); // 0 -> 01
1111 }
1112
1113 data3 = 0;
1114 for (int i=0;i<16;i++) {
1115 if (hi & (1<<(31-i)))
1116 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1117 else
1118 data3 |= (1<<((15-i)*2)); // 0 -> 01
1119 }
1120
1121 data4 = 0;
1122 for (int i=0;i<16;i++) {
1123 if (hi & (1<<(15-i)))
1124 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1125 else
1126 data4 |= (1<<((15-i)*2)); // 0 -> 01
1127 }
1128
1129 data5 = 0;
1130 for (int i=0;i<16;i++) {
1131 if (lo & (1<<(31-i)))
1132 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1133 else
1134 data5 |= (1<<((15-i)*2)); // 0 -> 01
1135 }
1136
1137 data6 = 0;
1138 for (int i=0;i<16;i++) {
1139 if (lo & (1<<(15-i)))
1140 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1141 else
1142 data6 |= (1<<((15-i)*2)); // 0 -> 01
1143 }
54a942b0 1144 }
ae8e8a43
MHS
1145 else {
1146 // Ensure no more than 44 bits supplied
1147 if (hi>0xFFF) {
1148 DbpString("Tags can only have 44 bits.");
1149 return;
1150 }
1151
1152 // Build the 3 data blocks for supplied 44bit ID
1153 last_block = 3;
1154
1155 data1 = 0x1D000000; // load preamble
1156
1157 for (int i=0;i<12;i++) {
1158 if (hi & (1<<(11-i)))
1159 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1160 else
1161 data1 |= (1<<((11-i)*2)); // 0 -> 01
1162 }
1163
1164 data2 = 0;
1165 for (int i=0;i<16;i++) {
1166 if (lo & (1<<(31-i)))
1167 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1168 else
1169 data2 |= (1<<((15-i)*2)); // 0 -> 01
1170 }
1171
1172 data3 = 0;
1173 for (int i=0;i<16;i++) {
1174 if (lo & (1<<(15-i)))
1175 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1176 else
1177 data3 |= (1<<((15-i)*2)); // 0 -> 01
1178 }
54a942b0 1179 }
ae8e8a43
MHS
1180
1181 LED_D_ON();
1182 // Program the data blocks for supplied ID
1183 // and the block 0 for HID format
1184 T55xxWriteBlock(data1,1,0,0);
1185 T55xxWriteBlock(data2,2,0,0);
1186 T55xxWriteBlock(data3,3,0,0);
1187
1188 if (longFMT) { // if long format there are 6 blocks
1189 T55xxWriteBlock(data4,4,0,0);
1190 T55xxWriteBlock(data5,5,0,0);
1191 T55xxWriteBlock(data6,6,0,0);
54a942b0 1192 }
ae8e8a43
MHS
1193
1194 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1195 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1196 T55x7_MODULATION_FSK2a |
1197 last_block << T55x7_MAXBLOCK_SHIFT,
1198 0,0,0);
1199
1200 LED_D_OFF();
1201
1202 DbpString("DONE!");
2d4eae76 1203}
ec09b62d 1204
a1f3bb12 1205void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1206{
ae8e8a43
MHS
1207 int data1=0, data2=0; //up to six blocks for long format
1208
a1f3bb12 1209 data1 = hi; // load preamble
1210 data2 = lo;
1211
1212 LED_D_ON();
1213 // Program the data blocks for supplied ID
1214 // and the block 0 for HID format
1215 T55xxWriteBlock(data1,1,0,0);
1216 T55xxWriteBlock(data2,2,0,0);
ae8e8a43 1217
a1f3bb12 1218 //Config Block
1219 T55xxWriteBlock(0x00147040,0,0,0);
1220 LED_D_OFF();
ae8e8a43 1221
a1f3bb12 1222 DbpString("DONE!");
1223}
1224
2d4eae76 1225// Define 9bit header for EM410x tags
1226#define EM410X_HEADER 0x1FF
1227#define EM410X_ID_LENGTH 40
ec09b62d 1228
2d4eae76 1229void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1230{
ae8e8a43
MHS
1231 int i, id_bit;
1232 uint64_t id = EM410X_HEADER;
1233 uint64_t rev_id = 0; // reversed ID
1234 int c_parity[4]; // column parity
1235 int r_parity = 0; // row parity
1236 uint32_t clock = 0;
1237
1238 // Reverse ID bits given as parameter (for simpler operations)
1239 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1240 if (i < 32) {
1241 rev_id = (rev_id << 1) | (id_lo & 1);
1242 id_lo >>= 1;
1243 } else {
1244 rev_id = (rev_id << 1) | (id_hi & 1);
1245 id_hi >>= 1;
1246 }
1247 }
1248
1249 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1250 id_bit = rev_id & 1;
1251
1252 if (i % 4 == 0) {
1253 // Don't write row parity bit at start of parsing
1254 if (i)
1255 id = (id << 1) | r_parity;
1256 // Start counting parity for new row
1257 r_parity = id_bit;
1258 } else {
1259 // Count row parity
1260 r_parity ^= id_bit;
1261 }
1262
1263 // First elements in column?
1264 if (i < 4)
1265 // Fill out first elements
1266 c_parity[i] = id_bit;
1267 else
1268 // Count column parity
1269 c_parity[i % 4] ^= id_bit;
1270
1271 // Insert ID bit
1272 id = (id << 1) | id_bit;
1273 rev_id >>= 1;
1274 }
1275
1276 // Insert parity bit of last row
1277 id = (id << 1) | r_parity;
1278
1279 // Fill out column parity at the end of tag
1280 for (i = 0; i < 4; ++i)
1281 id = (id << 1) | c_parity[i];
1282
1283 // Add stop bit
1284 id <<= 1;
1285
1286 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1287 LED_D_ON();
1288
1289 // Write EM410x ID
1290 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1291 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1292
1293 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1294 if (card) {
1295 // Clock rate is stored in bits 8-15 of the card value
1296 clock = (card & 0xFF00) >> 8;
1297 Dbprintf("Clock rate: %d", clock);
1298 switch (clock)
1299 {
1300 case 32:
1301 clock = T55x7_BITRATE_RF_32;
1302 break;
1303 case 16:
1304 clock = T55x7_BITRATE_RF_16;
1305 break;
1306 case 0:
1307 // A value of 0 is assumed to be 64 for backwards-compatibility
1308 // Fall through...
1309 case 64:
1310 clock = T55x7_BITRATE_RF_64;
1311 break;
1312 default:
1313 Dbprintf("Invalid clock rate: %d", clock);
1314 return;
1315 }
1316
1317 // Writing configuration for T55x7 tag
1318 T55xxWriteBlock(clock |
1319 T55x7_MODULATION_MANCHESTER |
1320 2 << T55x7_MAXBLOCK_SHIFT,
1321 0, 0, 0);
1322 }
1323 else
1324 // Writing configuration for T5555(Q5) tag
1325 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1326 T5555_MODULATION_MANCHESTER |
1327 2 << T5555_MAXBLOCK_SHIFT,
1328 0, 0, 0);
1329
1330 LED_D_OFF();
1331 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1332 (uint32_t)(id >> 32), (uint32_t)id);
2d4eae76 1333}
2414f978 1334
1335// Clone Indala 64-bit tag by UID to T55x7
1336void CopyIndala64toT55x7(int hi, int lo)
1337{
ae8e8a43
MHS
1338 //Program the 2 data blocks for supplied 64bit UID
1339 // and the block 0 for Indala64 format
1340 T55xxWriteBlock(hi,1,0,0);
1341 T55xxWriteBlock(lo,2,0,0);
1342 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1343 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1344 T55x7_MODULATION_PSK1 |
1345 2 << T55x7_MAXBLOCK_SHIFT,
1346 0, 0, 0);
1347 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1348 // T5567WriteBlock(0x603E1042,0);
2414f978 1349
ae8e8a43 1350 DbpString("DONE!");
2414f978 1351}
1352
1353void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1354{
ae8e8a43
MHS
1355 //Program the 7 data blocks for supplied 224bit UID
1356 // and the block 0 for Indala224 format
1357 T55xxWriteBlock(uid1,1,0,0);
1358 T55xxWriteBlock(uid2,2,0,0);
1359 T55xxWriteBlock(uid3,3,0,0);
1360 T55xxWriteBlock(uid4,4,0,0);
1361 T55xxWriteBlock(uid5,5,0,0);
1362 T55xxWriteBlock(uid6,6,0,0);
1363 T55xxWriteBlock(uid7,7,0,0);
1364 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1365 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1366 T55x7_MODULATION_PSK1 |
1367 7 << T55x7_MAXBLOCK_SHIFT,
1368 0,0,0);
1369 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1370 // T5567WriteBlock(0x603E10E2,0);
1371
1372 DbpString("DONE!");
2414f978 1373}
54a942b0 1374
1375
1376#define abs(x) ( ((x)<0) ? -(x) : (x) )
1377#define max(x,y) ( x<y ? y:x)
1378
1379int DemodPCF7931(uint8_t **outBlocks) {
ae8e8a43
MHS
1380 uint8_t BitStream[256];
1381 uint8_t Blocks[8][16];
1382 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1383 int GraphTraceLen = sizeof(BigBuf);
1384 int i, j, lastval, bitidx, half_switch;
1385 int clock = 64;
1386 int tolerance = clock / 8;
1387 int pmc, block_done;
1388 int lc, warnings = 0;
1389 int num_blocks = 0;
1390 int lmin=128, lmax=128;
1391 uint8_t dir;
1392
1393 AcquireRawAdcSamples125k(0);
1394
1395 lmin = 64;
1396 lmax = 192;
1397
1398 i = 2;
1399
1400 /* Find first local max/min */
1401 if(GraphBuffer[1] > GraphBuffer[0]) {
1402 while(i < GraphTraceLen) {
1403 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1404 break;
1405 i++;
1406 }
1407 dir = 0;
54a942b0 1408 }
ae8e8a43
MHS
1409 else {
1410 while(i < GraphTraceLen) {
1411 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1412 break;
1413 i++;
1414 }
1415 dir = 1;
54a942b0 1416 }
ae8e8a43
MHS
1417
1418 lastval = i++;
1419 half_switch = 0;
1420 pmc = 0;
1421 block_done = 0;
1422
1423 for (bitidx = 0; i < GraphTraceLen; i++)
1424 {
1425 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1426 {
1427 lc = i - lastval;
1428 lastval = i;
1429
1430 // Switch depending on lc length:
1431 // Tolerance is 1/8 of clock rate (arbitrary)
1432 if (abs(lc-clock/4) < tolerance) {
1433 // 16T0
1434 if((i - pmc) == lc) { /* 16T0 was previous one */
1435 /* It's a PMC ! */
1436 i += (128+127+16+32+33+16)-1;
1437 lastval = i;
1438 pmc = 0;
1439 block_done = 1;
1440 }
1441 else {
1442 pmc = i;
1443 }
1444 } else if (abs(lc-clock/2) < tolerance) {
1445 // 32TO
1446 if((i - pmc) == lc) { /* 16T0 was previous one */
1447 /* It's a PMC ! */
1448 i += (128+127+16+32+33)-1;
1449 lastval = i;
1450 pmc = 0;
1451 block_done = 1;
1452 }
1453 else if(half_switch == 1) {
1454 BitStream[bitidx++] = 0;
1455 half_switch = 0;
1456 }
1457 else
1458 half_switch++;
1459 } else if (abs(lc-clock) < tolerance) {
1460 // 64TO
1461 BitStream[bitidx++] = 1;
1462 } else {
1463 // Error
1464 warnings++;
1465 if (warnings > 10)
1466 {
1467 Dbprintf("Error: too many detection errors, aborting.");
1468 return 0;
1469 }
1470 }
1471
1472 if(block_done == 1) {
1473 if(bitidx == 128) {
1474 for(j=0; j<16; j++) {
1475 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1476 64*BitStream[j*8+6]+
1477 32*BitStream[j*8+5]+
1478 16*BitStream[j*8+4]+
1479 8*BitStream[j*8+3]+
1480 4*BitStream[j*8+2]+
1481 2*BitStream[j*8+1]+
1482 BitStream[j*8];
1483 }
1484 num_blocks++;
1485 }
1486 bitidx = 0;
1487 block_done = 0;
1488 half_switch = 0;
1489 }
1490 if(i < GraphTraceLen)
1491 {
1492 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1493 else dir = 1;
1494 }
1495 }
1496 if(bitidx==255)
1497 bitidx=0;
1498 warnings = 0;
1499 if(num_blocks == 4) break;
1500 }
1501 memcpy(outBlocks, Blocks, 16*num_blocks);
1502 return num_blocks;
54a942b0 1503}
1504
1505int IsBlock0PCF7931(uint8_t *Block) {
ae8e8a43
MHS
1506 // Assume RFU means 0 :)
1507 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1508 return 1;
1509 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1510 return 1;
1511 return 0;
54a942b0 1512}
1513
1514int IsBlock1PCF7931(uint8_t *Block) {
ae8e8a43
MHS
1515 // Assume RFU means 0 :)
1516 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1517 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1518 return 1;
1519
1520 return 0;
54a942b0 1521}
54a942b0 1522#define ALLOC 16
1523
1524void ReadPCF7931() {
ae8e8a43
MHS
1525 uint8_t Blocks[8][17];
1526 uint8_t tmpBlocks[4][16];
1527 int i, j, ind, ind2, n;
1528 int num_blocks = 0;
1529 int max_blocks = 8;
1530 int ident = 0;
1531 int error = 0;
1532 int tries = 0;
1533
1534 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1535
1536 do {
1537 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1538 n = DemodPCF7931((uint8_t**)tmpBlocks);
1539 if(!n)
1540 error++;
1541 if(error==10 && num_blocks == 0) {
1542 Dbprintf("Error, no tag or bad tag");
1543 return;
54a942b0 1544 }
ae8e8a43
MHS
1545 else if (tries==20 || error==10) {
1546 Dbprintf("Error reading the tag");
1547 Dbprintf("Here is the partial content");
1548 goto end;
1549 }
1550
1551 for(i=0; i<n; i++)
1552 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1553 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1554 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1555 if(!ident) {
1556 for(i=0; i<n; i++) {
1557 if(IsBlock0PCF7931(tmpBlocks[i])) {
1558 // Found block 0 ?
1559 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1560 // Found block 1!
1561 // \o/
1562 ident = 1;
1563 memcpy(Blocks[0], tmpBlocks[i], 16);
1564 Blocks[0][ALLOC] = 1;
1565 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1566 Blocks[1][ALLOC] = 1;
1567 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1568 // Debug print
1569 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1570 num_blocks = 2;
1571 // Handle following blocks
1572 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1573 if(j==n) j=0;
1574 if(j==i) break;
1575 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1576 Blocks[ind2][ALLOC] = 1;
1577 }
1578 break;
1579 }
54a942b0 1580 }
ae8e8a43
MHS
1581 }
1582 }
1583 else {
1584 for(i=0; i<n; i++) { // Look for identical block in known blocks
1585 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1586 for(j=0; j<max_blocks; j++) {
1587 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1588 // Found an identical block
1589 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1590 if(ind2 < 0)
1591 ind2 = max_blocks;
1592 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1593 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1594 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1595 Blocks[ind2][ALLOC] = 1;
1596 num_blocks++;
1597 if(num_blocks == max_blocks) goto end;
1598 }
1599 }
1600 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1601 if(ind2 > max_blocks)
1602 ind2 = 0;
1603 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1604 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1605 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1606 Blocks[ind2][ALLOC] = 1;
1607 num_blocks++;
1608 if(num_blocks == max_blocks) goto end;
1609 }
1610 }
1611 }
1612 }
54a942b0 1613 }
54a942b0 1614 }
54a942b0 1615 }
ae8e8a43
MHS
1616 tries++;
1617 if (BUTTON_PRESS()) return;
1618 } while (num_blocks != max_blocks);
54a942b0 1619end:
ae8e8a43
MHS
1620 Dbprintf("-----------------------------------------");
1621 Dbprintf("Memory content:");
1622 Dbprintf("-----------------------------------------");
1623 for(i=0; i<max_blocks; i++) {
1624 if(Blocks[i][ALLOC]==1)
1625 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1626 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1627 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1628 else
1629 Dbprintf("<missing block %d>", i);
1630 }
1631 Dbprintf("-----------------------------------------");
1632
1633 return ;
54a942b0 1634}
1635
1636
1637//-----------------------------------
1638// EM4469 / EM4305 routines
1639//-----------------------------------
1640#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1641#define FWD_CMD_WRITE 0xA
1642#define FWD_CMD_READ 0x9
1643#define FWD_CMD_DISABLE 0x5
1644
1645
1646uint8_t forwardLink_data[64]; //array of forwarded bits
1647uint8_t * forward_ptr; //ptr for forward message preparation
1648uint8_t fwd_bit_sz; //forwardlink bit counter
1649uint8_t * fwd_write_ptr; //forwardlink bit pointer
1650
1651//====================================================================
1652// prepares command bits
1653// see EM4469 spec
1654//====================================================================
1655//--------------------------------------------------------------------
1656uint8_t Prepare_Cmd( uint8_t cmd ) {
ae8e8a43
MHS
1657 //--------------------------------------------------------------------
1658
1659 *forward_ptr++ = 0; //start bit
1660 *forward_ptr++ = 0; //second pause for 4050 code
1661
1662 *forward_ptr++ = cmd;
1663 cmd >>= 1;
1664 *forward_ptr++ = cmd;
1665 cmd >>= 1;
1666 *forward_ptr++ = cmd;
1667 cmd >>= 1;
1668 *forward_ptr++ = cmd;
1669
1670 return 6; //return number of emited bits
54a942b0 1671}
1672
1673//====================================================================
1674// prepares address bits
1675// see EM4469 spec
1676//====================================================================
1677
1678//--------------------------------------------------------------------
1679uint8_t Prepare_Addr( uint8_t addr ) {
ae8e8a43
MHS
1680 //--------------------------------------------------------------------
1681
1682 register uint8_t line_parity;
1683
1684 uint8_t i;
1685 line_parity = 0;
1686 for(i=0;i<6;i++) {
1687 *forward_ptr++ = addr;
1688 line_parity ^= addr;
1689 addr >>= 1;
1690 }
1691
1692 *forward_ptr++ = (line_parity & 1);
1693
1694 return 7; //return number of emited bits
54a942b0 1695}
1696
1697//====================================================================
1698// prepares data bits intreleaved with parity bits
1699// see EM4469 spec
1700//====================================================================
1701
1702//--------------------------------------------------------------------
1703uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
ae8e8a43
MHS
1704 //--------------------------------------------------------------------
1705
1706 register uint8_t line_parity;
1707 register uint8_t column_parity;
1708 register uint8_t i, j;
1709 register uint16_t data;
1710
1711 data = data_low;
1712 column_parity = 0;
1713
1714 for(i=0; i<4; i++) {
1715 line_parity = 0;
1716 for(j=0; j<8; j++) {
1717 line_parity ^= data;
1718 column_parity ^= (data & 1) << j;
1719 *forward_ptr++ = data;
1720 data >>= 1;
1721 }
1722 *forward_ptr++ = line_parity;
1723 if(i == 1)
1724 data = data_hi;
1725 }
1726
54a942b0 1727 for(j=0; j<8; j++) {
ae8e8a43
MHS
1728 *forward_ptr++ = column_parity;
1729 column_parity >>= 1;
54a942b0 1730 }
ae8e8a43
MHS
1731 *forward_ptr = 0;
1732
1733 return 45; //return number of emited bits
54a942b0 1734}
1735
1736//====================================================================
1737// Forward Link send function
1738// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1739// fwd_bit_count set with number of bits to be sent
1740//====================================================================
1741void SendForward(uint8_t fwd_bit_count) {
ae8e8a43
MHS
1742
1743 fwd_write_ptr = forwardLink_data;
1744 fwd_bit_sz = fwd_bit_count;
1745
1746 LED_D_ON();
1747
1748 //Field on
1749 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1750 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1751 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1752
1753 // Give it a bit of time for the resonant antenna to settle.
1754 // And for the tag to fully power up
1755 SpinDelay(150);
1756
1757 // force 1st mod pulse (start gap must be longer for 4305)
1758 fwd_bit_sz--; //prepare next bit modulation
1759 fwd_write_ptr++;
1760 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1761 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1762 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1763 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1764 SpinDelayUs(16*8); //16 cycles on (8us each)
1765
1766 // now start writting
1767 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1768 if(((*fwd_write_ptr++) & 1) == 1)
1769 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1770 else {
1771 //These timings work for 4469/4269/4305 (with the 55*8 above)
1772 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1773 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1774 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1775 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1776 SpinDelayUs(9*8); //16 cycles on (8us each)
1777 }
54a942b0 1778 }
54a942b0 1779}
1780
3fe4ff4f 1781
54a942b0 1782void EM4xLogin(uint32_t Password) {
ae8e8a43
MHS
1783
1784 uint8_t fwd_bit_count;
1785
1786 forward_ptr = forwardLink_data;
1787 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1788 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1789
1790 SendForward(fwd_bit_count);
1791
1792 //Wait for command to complete
1793 SpinDelay(20);
1794
54a942b0 1795}
1796
1797void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
ae8e8a43
MHS
1798
1799 uint8_t fwd_bit_count;
1800 uint8_t *dest = (uint8_t *)BigBuf;
1801 int m=0, i=0;
1802
1803 //If password mode do login
1804 if (PwdMode == 1) EM4xLogin(Pwd);
1805
1806 forward_ptr = forwardLink_data;
1807 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1808 fwd_bit_count += Prepare_Addr( Address );
1809
1810 m = sizeof(BigBuf);
1811 // Clear destination buffer before sending the command
1812 memset(dest, 128, m);
1813 // Connect the A/D to the peak-detected low-frequency path.
1814 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1815 // Now set up the SSC to get the ADC samples that are now streaming at us.
1816 FpgaSetupSsc();
1817
1818 SendForward(fwd_bit_count);
1819
1820 // Now do the acquisition
1821 i = 0;
1822 for(;;) {
1823 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1824 AT91C_BASE_SSC->SSC_THR = 0x43;
1825 }
1826 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1827 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1828 i++;
1829 if (i >= m) break;
1830 }
54a942b0 1831 }
ae8e8a43
MHS
1832 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1833 LED_D_OFF();
54a942b0 1834}
1835
1836void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
ae8e8a43
MHS
1837
1838 uint8_t fwd_bit_count;
1839
1840 //If password mode do login
1841 if (PwdMode == 1) EM4xLogin(Pwd);
1842
1843 forward_ptr = forwardLink_data;
1844 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1845 fwd_bit_count += Prepare_Addr( Address );
1846 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1847
1848 SendForward(fwd_bit_count);
1849
1850 //Wait for write to complete
1851 SpinDelay(20);
1852 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1853 LED_D_OFF();
54a942b0 1854}
Impressum, Datenschutz