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6658905f 1//-----------------------------------------------------------------------------\r
2// The FPGA is responsible for interfacing between the A/D, the coil drivers,\r
3// and the ARM. In the low-frequency modes it passes the data straight\r
4// through, so that the ARM gets raw A/D samples over the SSP. In the high-\r
5// frequency modes, the FPGA might perform some demodulation first, to\r
6// reduce the amount of data that we must send to the ARM.\r
7//\r
8// I am not really an FPGA/ASIC designer, so I am sure that a lot of this\r
9// could be improved.\r
10//\r
11// Jonathan Westhues, March 2006\r
12// Added ISO14443-A support by Gerhard de Koning Gans, April 2008\r
13//-----------------------------------------------------------------------------\r
14\r
15`include "lo_read.v"\r
16`include "lo_simulate.v"\r
17`include "hi_read_tx.v"\r
18`include "hi_read_rx_xcorr.v"\r
19`include "hi_simulate.v"\r
20`include "hi_iso14443a.v"\r
21`include "util.v"\r
22\r
23module fpga(\r
30f2a7d3 24 spcki, miso, mosi, ncs,\r
6658905f 25 pck0i, ck_1356meg, ck_1356megb,\r
26 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
27 adc_d, adc_clk, adc_noe,\r
28 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
29 cross_hi, cross_lo,\r
30 dbg\r
31);\r
30f2a7d3 32 input spcki, mosi, ncs;\r
6658905f 33 output miso;\r
34 input pck0i, ck_1356meg, ck_1356megb;\r
35 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
36 input [7:0] adc_d;\r
37 output adc_clk, adc_noe;\r
38 input ssp_dout;\r
39 output ssp_frame, ssp_din, ssp_clk;\r
40 input cross_hi, cross_lo;\r
41 output dbg;\r
42\r
30f2a7d3 43//assign pck0 = pck0i;\r
6658905f 44 IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(\r
45 .O(pck0),\r
46 .I(pck0i)\r
47 );\r
30f2a7d3 48//assign spck = spcki;\r
49 IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(\r
50 .O(spck),\r
51 .I(spcki)\r
52 );\r
6658905f 53//-----------------------------------------------------------------------------\r
54// The SPI receiver. This sets up the configuration word, which the rest of\r
55// the logic looks at to determine how to connect the A/D and the coil\r
56// drivers (i.e., which section gets it). Also assign some symbolic names\r
57// to the configuration bits, for use below.\r
58//-----------------------------------------------------------------------------\r
59\r
30f2a7d3 60reg [15:0] shift_reg;\r
61reg [7:0] divisor;\r
6658905f 62reg [7:0] conf_word;\r
63\r
64// We switch modes between transmitting to the 13.56 MHz tag and receiving\r
65// from it, which means that we must make sure that we can do so without\r
66// glitching, or else we will glitch the transmitted carrier.\r
67always @(posedge ncs)\r
68begin\r
30f2a7d3 69 case(shift_reg[15:12])\r
70 4'b0001: conf_word <= shift_reg[7:0];\r
71 4'b0010: divisor <= shift_reg[7:0];\r
72 endcase\r
6658905f 73end\r
74\r
75always @(posedge spck)\r
76begin\r
77 if(~ncs)\r
78 begin\r
30f2a7d3 79 shift_reg[15:1] <= shift_reg[14:0];\r
80 shift_reg[0] <= mosi;\r
6658905f 81 end\r
82end\r
83\r
84wire [2:0] major_mode;\r
85assign major_mode = conf_word[7:5];\r
86\r
87// For the low-frequency configuration:\r
88wire lo_is_125khz;\r
89assign lo_is_125khz = conf_word[3];\r
90\r
91// For the high-frequency transmit configuration: modulation depth, either\r
92// 100% (just quite driving antenna, steady LOW), or shallower (tri-state\r
93// some fraction of the buffers)\r
94wire hi_read_tx_shallow_modulation;\r
95assign hi_read_tx_shallow_modulation = conf_word[0];\r
96\r
97// For the high-frequency receive correlator: frequency against which to\r
98// correlate.\r
99wire hi_read_rx_xcorr_848;\r
100assign hi_read_rx_xcorr_848 = conf_word[0];\r
101// and whether to drive the coil (reader) or just short it (snooper)\r
102wire hi_read_rx_xcorr_snoop;\r
103assign hi_read_rx_xcorr_snoop = conf_word[1];\r
104\r
105// For the high-frequency simulated tag: what kind of modulation to use.\r
106wire [2:0] hi_simulate_mod_type;\r
107assign hi_simulate_mod_type = conf_word[2:0];\r
108\r
109//-----------------------------------------------------------------------------\r
110// And then we instantiate the modules corresponding to each of the FPGA's\r
111// major modes, and use muxes to connect the outputs of the active mode to\r
112// the output pins.\r
113//-----------------------------------------------------------------------------\r
114\r
115lo_read lr(\r
116 pck0, ck_1356meg, ck_1356megb,\r
117 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,\r
118 adc_d, lr_adc_clk,\r
119 lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,\r
120 cross_hi, cross_lo,\r
121 lr_dbg,\r
30f2a7d3 122 lo_is_125khz, divisor\r
6658905f 123);\r
124\r
125lo_simulate ls(\r
126 pck0, ck_1356meg, ck_1356megb,\r
127 ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,\r
128 adc_d, ls_adc_clk,\r
129 ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,\r
130 cross_hi, cross_lo,\r
131 ls_dbg\r
132);\r
133\r
134hi_read_tx ht(\r
135 pck0, ck_1356meg, ck_1356megb,\r
136 ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,\r
137 adc_d, ht_adc_clk,\r
138 ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,\r
139 cross_hi, cross_lo,\r
140 ht_dbg,\r
141 hi_read_tx_shallow_modulation\r
142);\r
143\r
144hi_read_rx_xcorr hrxc(\r
145 pck0, ck_1356meg, ck_1356megb,\r
146 hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,\r
147 adc_d, hrxc_adc_clk,\r
148 hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,\r
149 cross_hi, cross_lo,\r
150 hrxc_dbg,\r
151 hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop\r
152);\r
153\r
154hi_simulate hs(\r
155 pck0, ck_1356meg, ck_1356megb,\r
156 hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,\r
157 adc_d, hs_adc_clk,\r
158 hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,\r
159 cross_hi, cross_lo,\r
160 hs_dbg,\r
161 hi_simulate_mod_type\r
162);\r
163\r
164hi_iso14443a hisn(\r
165 pck0, ck_1356meg, ck_1356megb,\r
166 hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,\r
167 adc_d, hisn_adc_clk,\r
168 hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,\r
169 cross_hi, cross_lo,\r
170 hisn_dbg,\r
171 hi_simulate_mod_type\r
172);\r
173\r
174// Major modes:\r
175// 000 -- LF reader (generic)\r
176// 001 -- LF simulated tag (generic)\r
177// 010 -- HF reader, transmitting to tag; modulation depth selectable\r
178// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable\r
179// 100 -- HF simulated tag\r
180// 101 -- HF ISO14443-A\r
181// 110 -- unused\r
182// 111 -- everything off\r
183\r
184mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1'b0, 1'b0);\r
185mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1'b0, 1'b0);\r
186mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0);\r
187mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1'b0, 1'b0);\r
188mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1'b0, 1'b0);\r
189mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1'b0, 1'b0);\r
190mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1'b0, 1'b0);\r
191mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1'b0, 1'b0);\r
192mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1'b0, 1'b0);\r
193mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1'b0, 1'b0);\r
194mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0);\r
195\r
196// In all modes, let the ADC's outputs be enabled.\r
197assign adc_noe = 1'b0;\r
198\r
199endmodule\r
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