| | 1 | #include <at91sam7s512.h>\r |
| | 2 | \r |
| | 3 | #ifndef __AT91SAM7S128_H\r |
| | 4 | #define __AT91SAM7S128_H\r |
| | 5 | \r |
| | 6 | /***************************************************************\r |
| | 7 | * Start of translation between PM3 defines and AT91 defines\r |
| | 8 | * TODO these should be replaced throughout the code at some stage\r |
| | 9 | ***************************************************************/\r |
| | 10 | #define PERIPH_PIOA AT91C_ID_PIOA\r |
| | 11 | #define PERIPH_ADC AT91C_ID_ADC\r |
| | 12 | #define PERIPH_SPI AT91C_ID_SPI\r |
| | 13 | #define PERIPH_SSC AT91C_ID_SSC\r |
| | 14 | #define PERIPH_PWMC AT91C_ID_PWMC\r |
| | 15 | #define PERIPH_UDP AT91C_ID_UDP\r |
| | 16 | #define PERIPH_TC1 AT91C_ID_TC1\r |
| | 17 | \r |
| | 18 | #define SSC_BASE AT91C_BASE_SSC\r |
| | 19 | \r |
| | 20 | #define WDT_CONTROL AT91C_BASE_WDTC->WDTC_WDCR\r |
| | 21 | \r |
| | 22 | #define PWM_ENABLE AT91C_BASE_PWMC->PWMC_ENA\r |
| | 23 | \r |
| | 24 | // TODO WARNING these PWM defines MUST be replaced in the code ASAP before\r |
| | 25 | // someone starts using a value of x other than that selected below\r |
| | 26 | #define PWM_CH_PERIOD(x) AT91C_BASE_PWMC_CH0->PWMC_CPRDR\r |
| | 27 | #define PWM_CH_COUNTER(x) AT91C_BASE_PWMC_CH0->PWMC_CCNTR\r |
| | 28 | #define PWM_CH_MODE(x) AT91C_BASE_PWMC_CH0->PWMC_CMR\r |
| | 29 | #define PWM_CH_DUTY_CYCLE(x) AT91C_BASE_PWMC_CH0->PWMC_CDTYR\r |
| | 30 | \r |
| | 31 | #define PDC_RX_POINTER(x) AT91C_BASE_PDC_SSC->PDC_RPR\r |
| | 32 | #define PDC_RX_COUNTER(x) AT91C_BASE_PDC_SSC->PDC_RCR\r |
| | 33 | #define PDC_RX_NEXT_POINTER(x) AT91C_BASE_PDC_SSC->PDC_RNPR\r |
| | 34 | #define PDC_RX_NEXT_COUNTER(x) AT91C_BASE_PDC_SSC->PDC_RNCR\r |
| | 35 | #define PDC_CONTROL(x) AT91C_BASE_PDC_SSC->PDC_PTCR\r |
| | 36 | // End WARNING\r |
| | 37 | \r |
| | 38 | #define DBGU_CIDR AT91C_BASE_DBGU->DBGU_CIDR\r |
| | 39 | \r |
| | 40 | #define RSTC_CONTROL AT91C_BASE_RSTC->RSTC_RCR\r |
| | 41 | #define RSTC_STATUS AT91C_BASE_RSTC->RSTC_RSR\r |
| | 42 | \r |
| | 43 | #define MC_FLASH_COMMAND AT91C_BASE_EFC0->EFC_FCR\r |
| | 44 | #define MC_FLASH_MODE0 AT91C_BASE_EFC0->EFC_FMR\r |
| | 45 | #define MC_FLASH_MODE1 AT91C_BASE_EFC1->EFC_FMR\r |
| | 46 | #define MC_FLASH_STATUS AT91C_BASE_EFC0->EFC_FSR\r |
| | 47 | \r |
| | 48 | #define ADC_CONTROL AT91C_BASE_ADC->ADC_CR\r |
| | 49 | #define ADC_MODE AT91C_BASE_ADC->ADC_MR\r |
| | 50 | #define ADC_CHANNEL_ENABLE AT91C_BASE_ADC->ADC_CHER\r |
| | 51 | #define ADC_STATUS AT91C_BASE_ADC->ADC_SR\r |
| | 52 | #define ADC_CHANNEL_DATA(x) AT91C_BASE_ADC->ADC_CDR[x]\r |
| | 53 | \r |
| | 54 | #define PIO_ENABLE AT91C_BASE_PIOA->PIO_PER\r |
| | 55 | #define PIO_DISABLE AT91C_BASE_PIOA->PIO_PDR\r |
| | 56 | #define PIO_OUTPUT_ENABLE AT91C_BASE_PIOA->PIO_OER\r |
| | 57 | #define PIO_OUTPUT_DISABLE AT91C_BASE_PIOA->PIO_ODR\r |
| | 58 | #define PIO_OUTPUT_DATA_SET AT91C_BASE_PIOA->PIO_SODR\r |
| | 59 | #define PIO_OUTPUT_DATA_CLEAR AT91C_BASE_PIOA->PIO_CODR\r |
| | 60 | #define PIO_PIN_DATA_STATUS AT91C_BASE_PIOA->PIO_PDSR\r |
| | 61 | #define PIO_NO_PULL_UP_ENABLE AT91C_BASE_PIOA->PIO_PPUDR\r |
| | 62 | #define PIO_NO_PULL_UP_DISABLE AT91C_BASE_PIOA->PIO_PPUER\r |
| | 63 | #define PIO_PERIPHERAL_B_SEL AT91C_BASE_PIOA->PIO_BSR\r |
| | 64 | #define PIO_PERIPHERAL_A_SEL AT91C_BASE_PIOA->PIO_ASR\r |
| | 65 | \r |
| | 66 | #define PMC_SYS_CLK_ENABLE AT91C_BASE_PMC->PMC_SCER\r |
| | 67 | #define PMC_PERIPHERAL_CLK_ENABLE AT91C_BASE_PMC->PMC_PCER\r |
| | 68 | #define PMC_MAIN_OSCILLATOR AT91C_BASE_PMC->PMC_MOR\r |
| | 69 | #define PMC_PLL AT91C_BASE_PMC->PMC_PLLR\r |
| | 70 | #define PMC_MASTER_CLK AT91C_BASE_PMC->PMC_MCKR\r |
| | 71 | #define PMC_PROGRAMMABLE_CLK_0 AT91C_BASE_PMC->PMC_PCKR[0]\r |
| | 72 | #define PMC_INTERRUPT_STATUS AT91C_BASE_PMC->PMC_SR\r |
| | 73 | \r |
| | 74 | #define SSC_CONTROL AT91C_BASE_SSC->SSC_CR\r |
| | 75 | #define SSC_CLOCK_DIVISOR AT91C_BASE_SSC->SSC_CMR\r |
| | 76 | #define SSC_RECEIVE_CLOCK_MODE AT91C_BASE_SSC->SSC_RCMR\r |
| | 77 | #define SSC_RECEIVE_FRAME_MODE AT91C_BASE_SSC->SSC_RFMR\r |
| | 78 | #define SSC_TRANSMIT_CLOCK_MODE AT91C_BASE_SSC->SSC_TCMR\r |
| | 79 | #define SSC_TRANSMIT_FRAME_MODE AT91C_BASE_SSC->SSC_TFMR\r |
| | 80 | #define SSC_RECEIVE_HOLDING AT91C_BASE_SSC->SSC_RHR\r |
| | 81 | #define SSC_TRANSMIT_HOLDING AT91C_BASE_SSC->SSC_THR\r |
| | 82 | #define SSC_STATUS AT91C_BASE_SSC->SSC_SR\r |
| | 83 | \r |
| | 84 | #define SPI_CONTROL AT91C_BASE_SPI->SPI_CR\r |
| | 85 | #define SPI_MODE AT91C_BASE_SPI->SPI_MR\r |
| | 86 | #define SPI_TX_DATA AT91C_BASE_SPI->SPI_TDR\r |
| | 87 | #define SPI_STATUS AT91C_BASE_SPI->SPI_SR\r |
| | 88 | #define SPI_FOR_CHIPSEL_0 AT91C_BASE_SPI->SPI_CSR[0]\r |
| | 89 | #define SPI_FOR_CHIPSEL_1 AT91C_BASE_SPI->SPI_CSR[1]\r |
| | 90 | #define SPI_FOR_CHIPSEL_2 AT91C_BASE_SPI->SPI_CSR[2]\r |
| | 91 | #define SPI_FOR_CHIPSEL_3 AT91C_BASE_SPI->SPI_CSR[3]\r |
| | 92 | \r |
| | 93 | #define TC1_CCR AT91C_BASE_TC1->TC_CCR\r |
| | 94 | #define TC1_CMR AT91C_BASE_TC1->TC_CMR\r |
| | 95 | #define TC1_CV AT91C_BASE_TC1->TC_CV\r |
| | 96 | #define TC1_RA AT91C_BASE_TC1->TC_RA\r |
| | 97 | #define TC1_SR AT91C_BASE_TC1->TC_SR\r |
| | 98 | \r |
| | 99 | #define PDC_RX_ENABLE AT91C_PDC_RXTEN\r |
| | 100 | #define PDC_RX_DISABLE AT91C_PDC_RXTDIS\r |
| | 101 | \r |
| | 102 | #define TC_CMR_ETRGEDG_RISING AT91C_TC_ETRGEDG_RISING\r |
| | 103 | #define TC_CMR_ABETRG AT91C_TC_ABETRG\r |
| | 104 | #define TC_CMR_LDRA_RISING AT91C_TC_LDRA_RISING\r |
| | 105 | #define TC_CMR_LDRB_RISING AT91C_TC_LDRB_RISING\r |
| | 106 | #define TC_CCR_CLKEN AT91C_TC_CLKEN\r |
| | 107 | #define TC_CCR_SWTRG AT91C_TC_SWTRG\r |
| | 108 | #define TC_SR_LDRAS AT91C_TC_LDRAS\r |
| | 109 | #define TC_CMR_ETRGEDG AT91C_TC_ETRGEDG\r |
| | 110 | #define TC_CCR_CLKDIS AT91C_TC_CLKDIS\r |
| | 111 | \r |
| | 112 | #define ADC_CONTROL_RESET AT91C_ADC_SWRST\r |
| | 113 | #define ADC_CONTROL_START AT91C_ADC_START\r |
| | 114 | \r |
| | 115 | #define SPI_CONTROL_ENABLE AT91C_SPI_SPIEN\r |
| | 116 | #define SPI_CONTROL_LAST_TRANSFER AT91C_SPI_LASTXFER\r |
| | 117 | #define SPI_CONTROL_RESET AT91C_SPI_SWRST\r |
| | 118 | #define SPI_CONTROL_DISABLE AT91C_SPI_SPIDIS\r |
| | 119 | #define SPI_STATUS_TX_EMPTY AT91C_SPI_TXEMPTY\r |
| | 120 | \r |
| | 121 | #define SSC_CONTROL_RX_ENABLE AT91C_SSC_RXEN\r |
| | 122 | #define SSC_CONTROL_TX_ENABLE AT91C_SSC_TXEN\r |
| | 123 | #define SSC_FRAME_MODE_MSB_FIRST AT91C_SSC_MSBF\r |
| | 124 | #define SSC_CONTROL_RESET AT91C_SSC_SWRST\r |
| | 125 | #define SSC_STATUS_TX_READY AT91C_SSC_TXRDY\r |
| | 126 | #define SSC_STATUS_RX_READY AT91C_SSC_RXRDY\r |
| | 127 | \r |
| | 128 | #define FCMD_WRITE_PAGE AT91C_MC_FCMD_START_PROG\r |
| | 129 | #define FLASH_PAGE_SIZE_BYTES AT91C_IFLASH_PAGE_SIZE\r |
| | 130 | \r |
| | 131 | #define RST_CONTROL_PROCESSOR_RESET AT91C_RSTC_PROCRST\r |
| | 132 | #define RST_STATUS_TYPE_MASK AT91C_RSTC_RSTTYP\r |
| | 133 | #define RST_STATUS_TYPE_WATCHDOG AT91C_RSTC_RSTTYP_WATCHDOG\r |
| | 134 | #define RST_STATUS_TYPE_SOFTWARE AT91C_RSTC_RSTTYP_SOFTWARE\r |
| | 135 | #define RST_STATUS_TYPE_USER AT91C_RSTC_RSTTYP_USER\r |
| | 136 | \r |
| | 137 | #define PMC_SYS_CLK_PROCESSOR_CLK AT91C_PMC_PCK\r |
| | 138 | #define PMC_SYS_CLK_UDP_CLK AT91C_PMC_UDP\r |
| | 139 | #define PMC_CLK_SELECTION_PLL_CLOCK AT91C_PMC_CSS_PLL_CLK\r |
| | 140 | #define PMC_CLK_PRESCALE_DIV_4 AT91C_PMC_PRES_CLK_4\r |
| | 141 | #define PMC_SYS_CLK_PROGRAMMABLE_CLK_0 AT91C_PMC_PCK0\r |
| | 142 | \r |
| | 143 | #define UDP_INTERRUPT_STATUS AT91C_BASE_UDP->UDP_ISR\r |
| | 144 | #define UDP_INTERRUPT_CLEAR AT91C_BASE_UDP->UDP_ICR\r |
| | 145 | #define UDP_FUNCTION_ADDR AT91C_BASE_UDP->UDP_FADDR\r |
| | 146 | #define UDP_RESET_ENDPOINT AT91C_BASE_UDP->UDP_RSTEP\r |
| | 147 | #define UDP_GLOBAL_STATE AT91C_BASE_UDP->UDP_GLBSTATE\r |
| | 148 | #define UDP_ENDPOINT_CSR(x) AT91C_BASE_UDP->UDP_CSR[x]\r |
| | 149 | #define UDP_ENDPOINT_FIFO(x) AT91C_BASE_UDP->UDP_FDR[x]\r |
| | 150 | \r |
| | 151 | #define UDP_CSR_CONTROL_DATA_DIR AT91C_UDP_DIR\r |
| | 152 | #define UDP_CSR_ENABLE_EP AT91C_UDP_EPEDS\r |
| | 153 | #define UDP_CSR_EPTYPE_CONTROL AT91C_UDP_EPTYPE_CTRL\r |
| | 154 | #define UDP_CSR_EPTYPE_INTERRUPT_IN AT91C_UDP_EPTYPE_INT_IN\r |
| | 155 | #define UDP_CSR_EPTYPE_INTERRUPT_OUT AT91C_UDP_EPTYPE_INT_OUT\r |
| | 156 | #define UDP_CSR_FORCE_STALL AT91C_UDP_FORCESTALL\r |
| | 157 | #define UDP_CSR_RX_HAVE_READ_SETUP_DATA AT91C_UDP_RXSETUP\r |
| | 158 | #define UDP_CSR_RX_PACKET_RECEIVED_BANK_0 AT91C_UDP_RX_DATA_BK0\r |
| | 159 | #define UDP_CSR_RX_PACKET_RECEIVED_BANK_1 AT91C_UDP_RX_DATA_BK1\r |
| | 160 | #define UDP_CSR_STALL_SENT AT91C_UDP_STALLSENT\r |
| | 161 | #define UDP_CSR_TX_PACKET AT91C_UDP_TXPKTRDY\r |
| | 162 | #define UDP_CSR_TX_PACKET_ACKED AT91C_UDP_TXCOMP\r |
| | 163 | \r |
| | 164 | #define UDP_FUNCTION_ADDR_ENABLED AT91C_UDP_FEN\r |
| | 165 | #define UDP_GLOBAL_STATE_ADDRESSED AT91C_UDP_FADDEN\r |
| | 166 | #define UDP_GLOBAL_STATE_CONFIGURED AT91C_UDP_CONFG\r |
| | 167 | #define UDP_INTERRUPT_END_OF_BUS_RESET AT91C_UDP_ENDBUSRES\r |
| | 168 | /***************************************************************\r |
| | 169 | * end of translation between PM3 defines and AT91 defines\r |
| | 170 | ***************************************************************/\r |
| | 171 | \r |
| | 172 | /***************************************************************\r |
| | 173 | * the defines below this line have no AT91 equivalents and can\r |
| | 174 | * be ideally moved to proxmark3.h\r |
| | 175 | ***************************************************************/\r |
| | 176 | #define WDT_HIT() WDT_CONTROL = 0xa5000001\r |
| | 177 | \r |
| | 178 | #define PWM_CH_MODE_PRESCALER(x) ((x)<<0)\r |
| | 179 | #define PWM_CHANNEL(x) (1<<(x))\r |
| | 180 | \r |
| | 181 | #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)\r |
| | 182 | \r |
| | 183 | #define ADC_CHAN_LF 4\r |
| | 184 | #define ADC_CHAN_HF 5\r |
| | 185 | #define ADC_MODE_PRESCALE(x) ((x)<<8)\r |
| | 186 | #define ADC_MODE_STARTUP_TIME(x) ((x)<<16)\r |
| | 187 | #define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)\r |
| | 188 | #define ADC_CHANNEL(x) (1<<(x))\r |
| | 189 | #define ADC_END_OF_CONVERSION(x) (1<<(x))\r |
| | 190 | \r |
| | 191 | #define SSC_CLOCK_MODE_START(x) ((x)<<8)\r |
| | 192 | #define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)\r |
| | 193 | #define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)\r |
| | 194 | #define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)\r |
| | 195 | \r |
| | 196 | #define MC_FLASH_COMMAND_KEY ((0x5A)<<24)\r |
| | 197 | #define MC_FLASH_STATUS_READY (1<<0)\r |
| | 198 | #define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)\r |
| | 199 | #define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)\r |
| | 200 | #define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)\r |
| | 201 | \r |
| | 202 | #define RST_CONTROL_KEY (0xA5<<24)\r |
| | 203 | \r |
| | 204 | #define PMC_MAIN_OSCILLATOR_ENABLE (1<<0)\r |
| | 205 | #define PMC_MAIN_OSCILLATOR_STABILIZED (1<<0)\r |
| | 206 | #define PMC_MAIN_OSCILLATOR_PLL_LOCK (1<<2)\r |
| | 207 | #define PMC_MAIN_OSCILLATOR_MCK_READY (1<<3)\r |
| | 208 | \r |
| | 209 | #define PMC_PLL_DIVISOR(x) (x)\r |
| | 210 | #define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x) ((x)<<8)\r |
| | 211 | #define PMC_CLK_PRESCALE_DIV_2 (1<<2)\r |
| | 212 | #define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)\r |
| | 213 | #define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)\r |
| | 214 | #define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)\r |
| | 215 | #define PMC_PLL_USB_DIVISOR(x) ((x)<<28)\r |
| | 216 | \r |
| | 217 | #define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))\r |
| | 218 | #define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)\r |
| | 219 | \r |
| | 220 | #endif\r |
projects / proxmark3-svn / blame_incremental