Hitag fixes (#887)
[proxmark3-svn] / fpga / fpga_lf.v
1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, March 2006
3 // iZsh <izsh at fail0verflow.com>, June 2014
4 //-----------------------------------------------------------------------------
5
6 // Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
7 // Note: the definitions here are without shifts
8
9 // Commands:
10 `define FPGA_CMD_SET_CONFREG 1
11 `define FPGA_CMD_SET_DIVISOR 2
12 `define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD 3
13
14 // Major modes:
15 `define FPGA_MAJOR_MODE_LF_ADC 0
16 `define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
17 `define FPGA_MAJOR_MODE_LF_PASSTHRU 2
18
19 // Options for LF_ADC
20 `define FPGA_LF_ADC_READER_FIELD 1
21
22 // Options for LF_EDGE_DETECT
23 `define FPGA_LF_EDGE_DETECT_READER_FIELD 1
24 `define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 2
25
26 `include "lo_read.v"
27 `include "lo_passthru.v"
28 `include "lo_edge_detect.v"
29 `include "util.v"
30 `include "clk_divider.v"
31
32 module fpga_lf(
33 input spck, output miso, input mosi, input ncs,
34 input pck0, input ck_1356meg, input ck_1356megb,
35 output pwr_lo, output pwr_hi,
36 output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
37 input [7:0] adc_d, output adc_clk, output adc_noe,
38 output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
39 input cross_hi, input cross_lo,
40 output dbg
41 );
42
43 //-----------------------------------------------------------------------------
44 // The SPI receiver. This sets up the configuration word, which the rest of
45 // the logic looks at to determine how to connect the A/D and the coil
46 // drivers (i.e., which section gets it). Also assign some symbolic names
47 // to the configuration bits, for use below.
48 //-----------------------------------------------------------------------------
49
50 reg [15:0] shift_reg;
51 reg [7:0] divisor;
52 reg [8:0] conf_word;
53 reg [7:0] lf_ed_threshold;
54
55 always @(posedge ncs)
56 begin
57 case (shift_reg[15:12])
58 `FPGA_CMD_SET_CONFREG:
59 begin
60 conf_word <= shift_reg[8:0];
61 if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
62 begin
63 lf_ed_threshold <= 127; // default threshold
64 end
65 end
66 `FPGA_CMD_SET_DIVISOR:
67 divisor <= shift_reg[7:0];
68 `FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
69 lf_ed_threshold <= shift_reg[7:0];
70 endcase
71 end
72
73 always @(posedge spck)
74 begin
75 if (~ncs)
76 begin
77 shift_reg[15:1] <= shift_reg[14:0];
78 shift_reg[0] <= mosi;
79 end
80 end
81
82 wire [2:0] major_mode = conf_word[8:6];
83
84 // For the low-frequency configuration:
85 wire lf_field = conf_word[0];
86 wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect
87
88 //-----------------------------------------------------------------------------
89 // And then we instantiate the modules corresponding to each of the FPGA's
90 // major modes, and use muxes to connect the outputs of the active mode to
91 // the output pins.
92 //-----------------------------------------------------------------------------
93 wire [7:0] pck_cnt;
94 wire pck_divclk;
95 clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
96
97 lo_read lr(
98 pck0, pck_cnt, pck_divclk,
99 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
100 adc_d, lr_adc_clk,
101 lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
102 lr_dbg, lf_field
103 );
104
105 lo_passthru lp(
106 pck_divclk,
107 lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
108 lp_adc_clk,
109 lp_ssp_din, ssp_dout,
110 cross_lo,
111 lp_dbg
112 );
113
114 lo_edge_detect le(
115 pck0, pck_divclk,
116 le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
117 adc_d, le_adc_clk,
118 le_ssp_frame, ssp_dout, le_ssp_clk,
119 cross_lo,
120 le_dbg,
121 lf_field,
122 lf_ed_toggle_mode, lf_ed_threshold
123 );
124
125 // Major modes:
126 // 000 -- LF reader (generic)
127 // 001 -- LF edge detect (generic)
128 // 010 -- LF passthrough
129
130 mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
131 mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
132 mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
133 mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
134 mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
135 mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
136 mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
137 mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
138 mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
139 mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
140 mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
141
142 // In all modes, let the ADC's outputs be enabled.
143 assign adc_noe = 1'b0;
144
145 endmodule
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