]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Minor corrections in fskdemod i lfops.c , see Holimans branch.
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "../include/proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "../include/hitag2.h"
15 #include "../common/crc16.h"
16 #include "string.h"
17 #include "crapto1.h"
18 #include "mifareutil.h"
19
20 void LFSetupFPGAForADC(int divisor, bool lf_field)
21 {
22 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
23 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
24 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
25 else if (divisor == 0)
26 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
27 else
28 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
29
30 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
31
32 // Connect the A/D to the peak-detected low-frequency path.
33 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
34
35 // Give it a bit of time for the resonant antenna to settle.
36 SpinDelay(150);
37
38 // Now set up the SSC to get the ADC samples that are now streaming at us.
39 FpgaSetupSsc();
40 }
41
42 void AcquireRawAdcSamples125k(int divisor)
43 {
44 LFSetupFPGAForADC(divisor, true);
45 DoAcquisition125k();
46 }
47
48 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
49 {
50 LFSetupFPGAForADC(divisor, false);
51 DoAcquisition125k_threshold(trigger_threshold);
52 }
53
54 // split into two routines so we can avoid timing issues after sending commands //
55 void DoAcquisition125k_internal(int trigger_threshold, bool silent)
56 {
57 uint8_t *dest = mifare_get_bigbufptr();
58 int n = 24000;
59 int i;
60
61 memset(dest, 0x00, n);
62 i = 0;
63 for(;;) {
64 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
65 AT91C_BASE_SSC->SSC_THR = 0x43;
66 LED_D_ON();
67 }
68 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
69 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
70 LED_D_OFF();
71 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
72 continue;
73 else
74 trigger_threshold = -1;
75 if (++i >= n) break;
76 }
77 }
78 if (!silent){
79 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
80 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
81 }
82 }
83 void DoAcquisition125k_threshold(int trigger_threshold) {
84 DoAcquisition125k_internal(trigger_threshold, true);
85 }
86 void DoAcquisition125k() {
87 DoAcquisition125k_internal(-1, true);
88 }
89
90 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
91 {
92
93 /* Make sure the tag is reset */
94 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
95 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
96 SpinDelay(2500);
97
98 int divisor_used = 95; // 125 KHz
99 // see if 'h' was specified
100
101 if (command[strlen((char *) command) - 1] == 'h')
102 divisor_used = 88; // 134.8 KHz
103
104 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
105 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
106 // Give it a bit of time for the resonant antenna to settle.
107 SpinDelay(50);
108
109
110 // And a little more time for the tag to fully power up
111 SpinDelay(2000);
112
113 // Now set up the SSC to get the ADC samples that are now streaming at us.
114 FpgaSetupSsc();
115
116 // now modulate the reader field
117 while(*command != '\0' && *command != ' ') {
118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
119 LED_D_OFF();
120 SpinDelayUs(delay_off);
121 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
122
123 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
124 LED_D_ON();
125 if(*(command++) == '0')
126 SpinDelayUs(period_0);
127 else
128 SpinDelayUs(period_1);
129 }
130 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
131 LED_D_OFF();
132 SpinDelayUs(delay_off);
133 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
134
135 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
136
137 // now do the read
138 DoAcquisition125k(-1);
139 }
140
141 /* blank r/w tag data stream
142 ...0000000000000000 01111111
143 1010101010101010101010101010101010101010101010101010101010101010
144 0011010010100001
145 01111111
146 101010101010101[0]000...
147
148 [5555fe852c5555555555555555fe0000]
149 */
150 void ReadTItag(void)
151 {
152 // some hardcoded initial params
153 // when we read a TI tag we sample the zerocross line at 2Mhz
154 // TI tags modulate a 1 as 16 cycles of 123.2Khz
155 // TI tags modulate a 0 as 16 cycles of 134.2Khz
156 #define FSAMPLE 2000000
157 #define FREQLO 123200
158 #define FREQHI 134200
159
160 signed char *dest = (signed char *)BigBuf;
161 int n = sizeof(BigBuf);
162 // int *dest = GraphBuffer;
163 // int n = GraphTraceLen;
164
165 // 128 bit shift register [shift3:shift2:shift1:shift0]
166 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
167
168 int i, cycles=0, samples=0;
169 // how many sample points fit in 16 cycles of each frequency
170 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
171 // when to tell if we're close enough to one freq or another
172 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
173
174 // TI tags charge at 134.2Khz
175 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
176 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
177
178 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
179 // connects to SSP_DIN and the SSP_DOUT logic level controls
180 // whether we're modulating the antenna (high)
181 // or listening to the antenna (low)
182 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
183
184 // get TI tag data into the buffer
185 AcquireTiType();
186
187 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
188
189 for (i=0; i<n-1; i++) {
190 // count cycles by looking for lo to hi zero crossings
191 if ( (dest[i]<0) && (dest[i+1]>0) ) {
192 cycles++;
193 // after 16 cycles, measure the frequency
194 if (cycles>15) {
195 cycles=0;
196 samples=i-samples; // number of samples in these 16 cycles
197
198 // TI bits are coming to us lsb first so shift them
199 // right through our 128 bit right shift register
200 shift0 = (shift0>>1) | (shift1 << 31);
201 shift1 = (shift1>>1) | (shift2 << 31);
202 shift2 = (shift2>>1) | (shift3 << 31);
203 shift3 >>= 1;
204
205 // check if the cycles fall close to the number
206 // expected for either the low or high frequency
207 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
208 // low frequency represents a 1
209 shift3 |= (1<<31);
210 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
211 // high frequency represents a 0
212 } else {
213 // probably detected a gay waveform or noise
214 // use this as gaydar or discard shift register and start again
215 shift3 = shift2 = shift1 = shift0 = 0;
216 }
217 samples = i;
218
219 // for each bit we receive, test if we've detected a valid tag
220
221 // if we see 17 zeroes followed by 6 ones, we might have a tag
222 // remember the bits are backwards
223 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
224 // if start and end bytes match, we have a tag so break out of the loop
225 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
226 cycles = 0xF0B; //use this as a flag (ugly but whatever)
227 break;
228 }
229 }
230 }
231 }
232 }
233
234 // if flag is set we have a tag
235 if (cycles!=0xF0B) {
236 DbpString("Info: No valid tag detected.");
237 } else {
238 // put 64 bit data into shift1 and shift0
239 shift0 = (shift0>>24) | (shift1 << 8);
240 shift1 = (shift1>>24) | (shift2 << 8);
241
242 // align 16 bit crc into lower half of shift2
243 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
244
245 // if r/w tag, check ident match
246 if ( shift3&(1<<15) ) {
247 DbpString("Info: TI tag is rewriteable");
248 // only 15 bits compare, last bit of ident is not valid
249 if ( ((shift3>>16)^shift0)&0x7fff ) {
250 DbpString("Error: Ident mismatch!");
251 } else {
252 DbpString("Info: TI tag ident is valid");
253 }
254 } else {
255 DbpString("Info: TI tag is readonly");
256 }
257
258 // WARNING the order of the bytes in which we calc crc below needs checking
259 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
260 // bytes in reverse or something
261 // calculate CRC
262 uint32_t crc=0;
263
264 crc = update_crc16(crc, (shift0)&0xff);
265 crc = update_crc16(crc, (shift0>>8)&0xff);
266 crc = update_crc16(crc, (shift0>>16)&0xff);
267 crc = update_crc16(crc, (shift0>>24)&0xff);
268 crc = update_crc16(crc, (shift1)&0xff);
269 crc = update_crc16(crc, (shift1>>8)&0xff);
270 crc = update_crc16(crc, (shift1>>16)&0xff);
271 crc = update_crc16(crc, (shift1>>24)&0xff);
272
273 Dbprintf("Info: Tag data: %x%08x, crc=%x",
274 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
275 if (crc != (shift2&0xffff)) {
276 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
277 } else {
278 DbpString("Info: CRC is good");
279 }
280 }
281 }
282
283 void WriteTIbyte(uint8_t b)
284 {
285 int i = 0;
286
287 // modulate 8 bits out to the antenna
288 for (i=0; i<8; i++)
289 {
290 if (b&(1<<i)) {
291 // stop modulating antenna
292 LOW(GPIO_SSC_DOUT);
293 SpinDelayUs(1000);
294 // modulate antenna
295 HIGH(GPIO_SSC_DOUT);
296 SpinDelayUs(1000);
297 } else {
298 // stop modulating antenna
299 LOW(GPIO_SSC_DOUT);
300 SpinDelayUs(300);
301 // modulate antenna
302 HIGH(GPIO_SSC_DOUT);
303 SpinDelayUs(1700);
304 }
305 }
306 }
307
308 void AcquireTiType(void)
309 {
310 int i, j, n;
311 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
312 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
313 #define TIBUFLEN 1250
314
315 // clear buffer
316 memset(BigBuf,0,sizeof(BigBuf));
317
318 // Set up the synchronous serial port
319 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
320 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
321
322 // steal this pin from the SSP and use it to control the modulation
323 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
324 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
325
326 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
327 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
328
329 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
330 // 48/2 = 24 MHz clock must be divided by 12
331 AT91C_BASE_SSC->SSC_CMR = 12;
332
333 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
334 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
335 AT91C_BASE_SSC->SSC_TCMR = 0;
336 AT91C_BASE_SSC->SSC_TFMR = 0;
337
338 LED_D_ON();
339
340 // modulate antenna
341 HIGH(GPIO_SSC_DOUT);
342
343 // Charge TI tag for 50ms.
344 SpinDelay(50);
345
346 // stop modulating antenna and listen
347 LOW(GPIO_SSC_DOUT);
348
349 LED_D_OFF();
350
351 i = 0;
352 for(;;) {
353 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
354 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
355 i++; if(i >= TIBUFLEN) break;
356 }
357 WDT_HIT();
358 }
359
360 // return stolen pin to SSP
361 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
362 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
363
364 char *dest = (char *)BigBuf;
365 n = TIBUFLEN*32;
366 // unpack buffer
367 for (i=TIBUFLEN-1; i>=0; i--) {
368 for (j=0; j<32; j++) {
369 if(BigBuf[i] & (1 << j)) {
370 dest[--n] = 1;
371 } else {
372 dest[--n] = -1;
373 }
374 }
375 }
376 }
377
378 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
379 // if crc provided, it will be written with the data verbatim (even if bogus)
380 // if not provided a valid crc will be computed from the data and written.
381 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
382 {
383 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
384 if(crc == 0) {
385 crc = update_crc16(crc, (idlo)&0xff);
386 crc = update_crc16(crc, (idlo>>8)&0xff);
387 crc = update_crc16(crc, (idlo>>16)&0xff);
388 crc = update_crc16(crc, (idlo>>24)&0xff);
389 crc = update_crc16(crc, (idhi)&0xff);
390 crc = update_crc16(crc, (idhi>>8)&0xff);
391 crc = update_crc16(crc, (idhi>>16)&0xff);
392 crc = update_crc16(crc, (idhi>>24)&0xff);
393 }
394 Dbprintf("Writing to tag: %x%08x, crc=%x",
395 (unsigned int) idhi, (unsigned int) idlo, crc);
396
397 // TI tags charge at 134.2Khz
398 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
399 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
400 // connects to SSP_DIN and the SSP_DOUT logic level controls
401 // whether we're modulating the antenna (high)
402 // or listening to the antenna (low)
403 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
404 LED_A_ON();
405
406 // steal this pin from the SSP and use it to control the modulation
407 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
408 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
409
410 // writing algorithm:
411 // a high bit consists of a field off for 1ms and field on for 1ms
412 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
413 // initiate a charge time of 50ms (field on) then immediately start writing bits
414 // start by writing 0xBB (keyword) and 0xEB (password)
415 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
416 // finally end with 0x0300 (write frame)
417 // all data is sent lsb firts
418 // finish with 15ms programming time
419
420 // modulate antenna
421 HIGH(GPIO_SSC_DOUT);
422 SpinDelay(50); // charge time
423
424 WriteTIbyte(0xbb); // keyword
425 WriteTIbyte(0xeb); // password
426 WriteTIbyte( (idlo )&0xff );
427 WriteTIbyte( (idlo>>8 )&0xff );
428 WriteTIbyte( (idlo>>16)&0xff );
429 WriteTIbyte( (idlo>>24)&0xff );
430 WriteTIbyte( (idhi )&0xff );
431 WriteTIbyte( (idhi>>8 )&0xff );
432 WriteTIbyte( (idhi>>16)&0xff );
433 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
434 WriteTIbyte( (crc )&0xff ); // crc lo
435 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
436 WriteTIbyte(0x00); // write frame lo
437 WriteTIbyte(0x03); // write frame hi
438 HIGH(GPIO_SSC_DOUT);
439 SpinDelay(50); // programming time
440
441 LED_A_OFF();
442
443 // get TI tag data into the buffer
444 AcquireTiType();
445
446 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
447 DbpString("Now use tiread to check");
448 }
449
450 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
451 {
452 int i;
453 uint8_t *tab = (uint8_t *)BigBuf;
454
455 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
456 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
457
458 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
459
460 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
461 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
462
463 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
464 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
465
466 i = 0;
467 for(;;) {
468 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
469 if(BUTTON_PRESS()) {
470 DbpString("Stopped");
471 return;
472 }
473 WDT_HIT();
474 }
475
476 if (ledcontrol)
477 LED_D_ON();
478
479 if(tab[i])
480 OPEN_COIL();
481 else
482 SHORT_COIL();
483
484 if (ledcontrol)
485 LED_D_OFF();
486
487 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
488 if(BUTTON_PRESS()) {
489 DbpString("Stopped");
490 return;
491 }
492 WDT_HIT();
493 }
494
495 i++;
496 if(i == period) {
497 i = 0;
498 if (gap) {
499 SHORT_COIL();
500 SpinDelayUs(gap);
501 }
502 }
503 }
504 }
505
506 #define DEBUG_FRAME_CONTENTS 1
507 void SimulateTagLowFrequencyBidir(int divisor, int t0)
508 {
509 }
510
511 // compose fc/8 fc/10 waveform
512 static void fc(int c, int *n) {
513 uint8_t *dest = (uint8_t *)BigBuf;
514 int idx;
515
516 // for when we want an fc8 pattern every 4 logical bits
517 if(c==0) {
518 dest[((*n)++)]=1;
519 dest[((*n)++)]=1;
520 dest[((*n)++)]=0;
521 dest[((*n)++)]=0;
522 dest[((*n)++)]=0;
523 dest[((*n)++)]=0;
524 dest[((*n)++)]=0;
525 dest[((*n)++)]=0;
526 }
527 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
528 if(c==8) {
529 for (idx=0; idx<6; idx++) {
530 dest[((*n)++)]=1;
531 dest[((*n)++)]=1;
532 dest[((*n)++)]=0;
533 dest[((*n)++)]=0;
534 dest[((*n)++)]=0;
535 dest[((*n)++)]=0;
536 dest[((*n)++)]=0;
537 dest[((*n)++)]=0;
538 }
539 }
540
541 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
542 if(c==10) {
543 for (idx=0; idx<5; idx++) {
544 dest[((*n)++)]=1;
545 dest[((*n)++)]=1;
546 dest[((*n)++)]=1;
547 dest[((*n)++)]=0;
548 dest[((*n)++)]=0;
549 dest[((*n)++)]=0;
550 dest[((*n)++)]=0;
551 dest[((*n)++)]=0;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 }
555 }
556 }
557
558 // prepare a waveform pattern in the buffer based on the ID given then
559 // simulate a HID tag until the button is pressed
560 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
561 {
562 int n=0, i=0;
563 /*
564 HID tag bitstream format
565 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
566 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
567 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
568 A fc8 is inserted before every 4 bits
569 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
570 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
571 */
572
573 if (hi>0xFFF) {
574 DbpString("Tags can only have 44 bits.");
575 return;
576 }
577 fc(0,&n);
578 // special start of frame marker containing invalid bit sequences
579 fc(8, &n); fc(8, &n); // invalid
580 fc(8, &n); fc(10, &n); // logical 0
581 fc(10, &n); fc(10, &n); // invalid
582 fc(8, &n); fc(10, &n); // logical 0
583
584 WDT_HIT();
585 // manchester encode bits 43 to 32
586 for (i=11; i>=0; i--) {
587 if ((i%4)==3) fc(0,&n);
588 if ((hi>>i)&1) {
589 fc(10, &n); fc(8, &n); // low-high transition
590 } else {
591 fc(8, &n); fc(10, &n); // high-low transition
592 }
593 }
594
595 WDT_HIT();
596 // manchester encode bits 31 to 0
597 for (i=31; i>=0; i--) {
598 if ((i%4)==3) fc(0,&n);
599 if ((lo>>i)&1) {
600 fc(10, &n); fc(8, &n); // low-high transition
601 } else {
602 fc(8, &n); fc(10, &n); // high-low transition
603 }
604 }
605
606 if (ledcontrol)
607 LED_A_ON();
608 SimulateTagLowFrequency(n, 0, ledcontrol);
609
610 if (ledcontrol)
611 LED_A_OFF();
612 }
613
614 size_t fsk_demod(uint8_t * dest, size_t size)
615 {
616 uint32_t last_transition = 0;
617 uint32_t idx = 1;
618
619 // we don't care about actual value, only if it's more or less than a
620 // threshold essentially we capture zero crossings for later analysis
621 uint8_t threshold_value = 127;
622
623 // sync to first lo-hi transition, and threshold
624
625 //Need to threshold first sample
626 dest[0] = (dest[0] < threshold_value) ? 0 : 1;
627
628 size_t numBits = 0;
629 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
630 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
631 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
632 for(idx = 1; idx < size; idx++) {
633 // threshold current value
634 dest[idx] = (dest[idx] < threshold_value) ? 0 : 1;
635
636 // Check for 0->1 transition
637 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
638
639 dest[numBits] = (idx-last_transition < 9) ? 1 : 0;
640 last_transition = idx;
641 numBits++;
642 }
643 }
644 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
645 }
646
647
648 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
649 {
650 uint8_t lastval=dest[0];
651 uint32_t idx=0;
652 size_t numBits=0;
653 uint32_t n=1;
654
655 for( idx=1; idx < size; idx++) {
656
657 if (dest[idx]==lastval) {
658 n++;
659 continue;
660 }
661 //if lastval was 1, we have a 1->0 crossing
662 if ( dest[idx-1] ) {
663 n=(n+1) / h2l_crossing_value;
664 } else {// 0->1 crossing
665 n=(n+1) / l2h_crossing_value;
666 }
667 if (n == 0) n = 1;
668
669 if(n < maxConsequtiveBits)
670 {
671 memset(dest+numBits, dest[idx-1] , n);
672 numBits += n;
673 }
674 n=0;
675 lastval=dest[idx];
676 }//end for
677
678 return numBits;
679
680 }
681 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
682 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
683 {
684 uint8_t *dest = (uint8_t *)BigBuf;
685
686 size_t size=0,idx=0; //, found=0;
687 uint32_t hi2=0, hi=0, lo=0;
688
689 // Configure to go in 125Khz listen mode
690 LFSetupFPGAForADC(0, true);
691
692 while(!BUTTON_PRESS()) {
693
694 WDT_HIT();
695 if (ledcontrol) LED_A_ON();
696
697 DoAcquisition125k_internal(-1,true);
698 size = sizeof(BigBuf);
699
700 // FSK demodulator
701 size = fsk_demod(dest, size);
702
703 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
704 // 1->0 : fc/8 in sets of 6
705 // 0->1 : fc/10 in sets of 5
706 size = aggregate_bits(dest,size, 6,5,5);
707
708 WDT_HIT();
709
710 // final loop, go over previously decoded manchester data and decode into usable tag ID
711 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
712 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
713 int numshifts = 0;
714 idx = 0;
715 while( idx + sizeof(frame_marker_mask) < size) {
716 // search for a start of frame marker
717 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
718 { // frame marker found
719 idx+=sizeof(frame_marker_mask);
720
721 while(dest[idx] != dest[idx+1] && idx < size-2)
722 {
723 // Keep going until next frame marker (or error)
724 // Shift in a bit. Start by shifting high registers
725 hi2=(hi2<<1)|(hi>>31);
726 hi=(hi<<1)|(lo>>31);
727 //Then, shift in a 0 or one into low
728 if (dest[idx] && !dest[idx+1]) // 1 0
729 lo=(lo<<1)|0;
730 else // 0 1
731 lo=(lo<<1)|
732 1;
733 numshifts ++;
734 idx += 2;
735 }
736 //Dbprintf("Num shifts: %d ", numshifts);
737 // Hopefully, we read a tag and hit upon the next frame marker
738 if(idx + sizeof(frame_marker_mask) < size)
739 {
740 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
741 {
742 if (hi2 != 0){
743 Dbprintf("TAG ID: %x%08x%08x (%d)",
744 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
745 }
746 else {
747 Dbprintf("TAG ID: %x%08x (%d)",
748 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
749 }
750 }
751
752 }
753
754 // reset
755 hi2 = hi = lo = 0;
756 numshifts = 0;
757 }else
758 {
759 idx++;
760 }
761 }
762 WDT_HIT();
763
764 }
765 DbpString("Stopped");
766 if (ledcontrol) LED_A_OFF();
767 }
768
769 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
770 {
771 uint32_t num = 0;
772 for(int i = 0 ; i < numbits ; i++)
773 {
774 num = (num << 1) | (*src);
775 src++;
776 }
777 return num;
778 }
779
780
781 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
782 {
783 uint8_t *dest = (uint8_t *)BigBuf;
784
785 size_t size=0, idx=0;
786 uint32_t code=0, code2=0;
787
788 // Configure to go in 125Khz listen mode
789 LFSetupFPGAForADC(0, true);
790
791 while(!BUTTON_PRESS()) {
792
793
794 WDT_HIT();
795 if (ledcontrol) LED_A_ON();
796
797 DoAcquisition125k_internal(-1,true);
798 size = sizeof(BigBuf);
799
800 // FSK demodulator
801 size = fsk_demod(dest, size);
802
803 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
804 // 1->0 : fc/8 in sets of 7
805 // 0->1 : fc/10 in sets of 6
806 size = aggregate_bits(dest, size, 7,6,13);
807
808 WDT_HIT();
809
810 //Handle the data
811 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
812 for( idx=0; idx < size - 64; idx++) {
813
814 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
815
816 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
817 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
818 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
819 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
820 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
821 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
822 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
823 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
824
825 code = bytebits_to_byte(dest+idx,32);
826 code2 = bytebits_to_byte(dest+idx+32,32);
827
828 short version = bytebits_to_byte(dest+idx+14,4);
829 char unknown = bytebits_to_byte(dest+idx+19,8) ;
830 uint16_t number = bytebits_to_byte(dest+idx+36,9);
831
832 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
833 if (ledcontrol) LED_D_OFF();
834
835 // if we're only looking for one tag
836 if (findone){
837 LED_A_OFF();
838 return;
839 }
840 }
841 WDT_HIT();
842 }
843 DbpString("Stopped");
844 if (ledcontrol) LED_A_OFF();
845 }
846
847 /*------------------------------
848 * T5555/T5557/T5567 routines
849 *------------------------------
850 */
851
852 /* T55x7 configuration register definitions */
853 #define T55x7_POR_DELAY 0x00000001
854 #define T55x7_ST_TERMINATOR 0x00000008
855 #define T55x7_PWD 0x00000010
856 #define T55x7_MAXBLOCK_SHIFT 5
857 #define T55x7_AOR 0x00000200
858 #define T55x7_PSKCF_RF_2 0
859 #define T55x7_PSKCF_RF_4 0x00000400
860 #define T55x7_PSKCF_RF_8 0x00000800
861 #define T55x7_MODULATION_DIRECT 0
862 #define T55x7_MODULATION_PSK1 0x00001000
863 #define T55x7_MODULATION_PSK2 0x00002000
864 #define T55x7_MODULATION_PSK3 0x00003000
865 #define T55x7_MODULATION_FSK1 0x00004000
866 #define T55x7_MODULATION_FSK2 0x00005000
867 #define T55x7_MODULATION_FSK1a 0x00006000
868 #define T55x7_MODULATION_FSK2a 0x00007000
869 #define T55x7_MODULATION_MANCHESTER 0x00008000
870 #define T55x7_MODULATION_BIPHASE 0x00010000
871 #define T55x7_BITRATE_RF_8 0
872 #define T55x7_BITRATE_RF_16 0x00040000
873 #define T55x7_BITRATE_RF_32 0x00080000
874 #define T55x7_BITRATE_RF_40 0x000C0000
875 #define T55x7_BITRATE_RF_50 0x00100000
876 #define T55x7_BITRATE_RF_64 0x00140000
877 #define T55x7_BITRATE_RF_100 0x00180000
878 #define T55x7_BITRATE_RF_128 0x001C0000
879
880 /* T5555 (Q5) configuration register definitions */
881 #define T5555_ST_TERMINATOR 0x00000001
882 #define T5555_MAXBLOCK_SHIFT 0x00000001
883 #define T5555_MODULATION_MANCHESTER 0
884 #define T5555_MODULATION_PSK1 0x00000010
885 #define T5555_MODULATION_PSK2 0x00000020
886 #define T5555_MODULATION_PSK3 0x00000030
887 #define T5555_MODULATION_FSK1 0x00000040
888 #define T5555_MODULATION_FSK2 0x00000050
889 #define T5555_MODULATION_BIPHASE 0x00000060
890 #define T5555_MODULATION_DIRECT 0x00000070
891 #define T5555_INVERT_OUTPUT 0x00000080
892 #define T5555_PSK_RF_2 0
893 #define T5555_PSK_RF_4 0x00000100
894 #define T5555_PSK_RF_8 0x00000200
895 #define T5555_USE_PWD 0x00000400
896 #define T5555_USE_AOR 0x00000800
897 #define T5555_BITRATE_SHIFT 12
898 #define T5555_FAST_WRITE 0x00004000
899 #define T5555_PAGE_SELECT 0x00008000
900
901 /*
902 * Relevant times in microsecond
903 * To compensate antenna falling times shorten the write times
904 * and enlarge the gap ones.
905 */
906 #define START_GAP 30*8 // 10 - 50fc 250
907 #define WRITE_GAP 20*8 // 8 - 30fc
908 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
909 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
910
911 // VALUES TAKEN FROM EM4x function: SendForward
912 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
913 // WRITE_GAP = 128; (16*8)
914 // WRITE_1 = 256 32*8; (32*8)
915
916 // These timings work for 4469/4269/4305 (with the 55*8 above)
917 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
918
919 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
920
921 // Write one bit to card
922 void T55xxWriteBit(int bit)
923 {
924 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
925 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
926 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
927 if (!bit)
928 SpinDelayUs(WRITE_0);
929 else
930 SpinDelayUs(WRITE_1);
931 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
932 SpinDelayUs(WRITE_GAP);
933 }
934
935 // Write one card block in page 0, no lock
936 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
937 {
938 uint32_t i = 0;
939
940 // Set up FPGA, 125kHz
941 // Wait for config.. (192+8190xPOW)x8 == 67ms
942 LFSetupFPGAForADC(0, true);
943
944 // Now start writting
945 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
946 SpinDelayUs(START_GAP);
947
948 // Opcode
949 T55xxWriteBit(1);
950 T55xxWriteBit(0); //Page 0
951 if (PwdMode == 1){
952 // Pwd
953 for (i = 0x80000000; i != 0; i >>= 1)
954 T55xxWriteBit(Pwd & i);
955 }
956 // Lock bit
957 T55xxWriteBit(0);
958
959 // Data
960 for (i = 0x80000000; i != 0; i >>= 1)
961 T55xxWriteBit(Data & i);
962
963 // Block
964 for (i = 0x04; i != 0; i >>= 1)
965 T55xxWriteBit(Block & i);
966
967 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
968 // so wait a little more)
969 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
970 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
971 SpinDelay(20);
972 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
973 }
974
975 // Read one card block in page 0
976 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
977 {
978 uint8_t *dest = mifare_get_bigbufptr();
979 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
980 uint32_t i = 0;
981
982 // Clear destination buffer before sending the command 0x80 = average.
983 memset(dest, 0x80, bufferlength);
984
985 // Set up FPGA, 125kHz
986 // Wait for config.. (192+8190xPOW)x8 == 67ms
987 LFSetupFPGAForADC(0, true);
988
989 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
990 SpinDelayUs(START_GAP);
991
992 // Opcode
993 T55xxWriteBit(1);
994 T55xxWriteBit(0); //Page 0
995 if (PwdMode == 1){
996 // Pwd
997 for (i = 0x80000000; i != 0; i >>= 1)
998 T55xxWriteBit(Pwd & i);
999 }
1000 // Lock bit
1001 T55xxWriteBit(0);
1002 // Block
1003 for (i = 0x04; i != 0; i >>= 1)
1004 T55xxWriteBit(Block & i);
1005
1006 // Turn field on to read the response
1007 TurnReadLFOn();
1008
1009 // Now do the acquisition
1010 i = 0;
1011 for(;;) {
1012 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1013 AT91C_BASE_SSC->SSC_THR = 0x43;
1014 LED_D_ON();
1015 }
1016 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1017 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1018 ++i;
1019 LED_D_OFF();
1020 if (i > bufferlength) break;
1021 }
1022 }
1023
1024 cmd_send(CMD_ACK,0,0,0,0,0);
1025 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1026 LED_D_OFF();
1027 }
1028
1029 // Read card traceability data (page 1)
1030 void T55xxReadTrace(void){
1031 uint8_t *dest = mifare_get_bigbufptr();
1032 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1033 int i=0;
1034
1035 // Clear destination buffer before sending the command 0x80 = average
1036 memset(dest, 0x80, bufferlength);
1037
1038 LFSetupFPGAForADC(0, true);
1039
1040 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1041 SpinDelayUs(START_GAP);
1042
1043 // Opcode
1044 T55xxWriteBit(1);
1045 T55xxWriteBit(1); //Page 1
1046
1047 // Turn field on to read the response
1048 TurnReadLFOn();
1049
1050 // Now do the acquisition
1051 for(;;) {
1052 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1053 AT91C_BASE_SSC->SSC_THR = 0x43;
1054 LED_D_ON();
1055 }
1056 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1057 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1058 ++i;
1059 LED_D_OFF();
1060
1061 if (i >= bufferlength) break;
1062 }
1063 }
1064
1065 cmd_send(CMD_ACK,0,0,0,0,0);
1066 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1067 LED_D_OFF();
1068 }
1069
1070 void TurnReadLFOn(){
1071 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1072 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1073 // Give it a bit of time for the resonant antenna to settle.
1074 //SpinDelay(30);
1075 SpinDelayUs(8*150);
1076 }
1077
1078 /*-------------- Cloning routines -----------*/
1079 // Copy HID id to card and setup block 0 config
1080 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1081 {
1082 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1083 int last_block = 0;
1084
1085 if (longFMT){
1086 // Ensure no more than 84 bits supplied
1087 if (hi2>0xFFFFF) {
1088 DbpString("Tags can only have 84 bits.");
1089 return;
1090 }
1091 // Build the 6 data blocks for supplied 84bit ID
1092 last_block = 6;
1093 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1094 for (int i=0;i<4;i++) {
1095 if (hi2 & (1<<(19-i)))
1096 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1097 else
1098 data1 |= (1<<((3-i)*2)); // 0 -> 01
1099 }
1100
1101 data2 = 0;
1102 for (int i=0;i<16;i++) {
1103 if (hi2 & (1<<(15-i)))
1104 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1105 else
1106 data2 |= (1<<((15-i)*2)); // 0 -> 01
1107 }
1108
1109 data3 = 0;
1110 for (int i=0;i<16;i++) {
1111 if (hi & (1<<(31-i)))
1112 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1113 else
1114 data3 |= (1<<((15-i)*2)); // 0 -> 01
1115 }
1116
1117 data4 = 0;
1118 for (int i=0;i<16;i++) {
1119 if (hi & (1<<(15-i)))
1120 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1121 else
1122 data4 |= (1<<((15-i)*2)); // 0 -> 01
1123 }
1124
1125 data5 = 0;
1126 for (int i=0;i<16;i++) {
1127 if (lo & (1<<(31-i)))
1128 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1129 else
1130 data5 |= (1<<((15-i)*2)); // 0 -> 01
1131 }
1132
1133 data6 = 0;
1134 for (int i=0;i<16;i++) {
1135 if (lo & (1<<(15-i)))
1136 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1137 else
1138 data6 |= (1<<((15-i)*2)); // 0 -> 01
1139 }
1140 }
1141 else {
1142 // Ensure no more than 44 bits supplied
1143 if (hi>0xFFF) {
1144 DbpString("Tags can only have 44 bits.");
1145 return;
1146 }
1147
1148 // Build the 3 data blocks for supplied 44bit ID
1149 last_block = 3;
1150
1151 data1 = 0x1D000000; // load preamble
1152
1153 for (int i=0;i<12;i++) {
1154 if (hi & (1<<(11-i)))
1155 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1156 else
1157 data1 |= (1<<((11-i)*2)); // 0 -> 01
1158 }
1159
1160 data2 = 0;
1161 for (int i=0;i<16;i++) {
1162 if (lo & (1<<(31-i)))
1163 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1164 else
1165 data2 |= (1<<((15-i)*2)); // 0 -> 01
1166 }
1167
1168 data3 = 0;
1169 for (int i=0;i<16;i++) {
1170 if (lo & (1<<(15-i)))
1171 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1172 else
1173 data3 |= (1<<((15-i)*2)); // 0 -> 01
1174 }
1175 }
1176
1177 LED_D_ON();
1178 // Program the data blocks for supplied ID
1179 // and the block 0 for HID format
1180 T55xxWriteBlock(data1,1,0,0);
1181 T55xxWriteBlock(data2,2,0,0);
1182 T55xxWriteBlock(data3,3,0,0);
1183
1184 if (longFMT) { // if long format there are 6 blocks
1185 T55xxWriteBlock(data4,4,0,0);
1186 T55xxWriteBlock(data5,5,0,0);
1187 T55xxWriteBlock(data6,6,0,0);
1188 }
1189
1190 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1191 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1192 T55x7_MODULATION_FSK2a |
1193 last_block << T55x7_MAXBLOCK_SHIFT,
1194 0,0,0);
1195
1196 LED_D_OFF();
1197
1198 DbpString("DONE!");
1199 }
1200
1201 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1202 {
1203 int data1=0, data2=0; //up to six blocks for long format
1204
1205 data1 = hi; // load preamble
1206 data2 = lo;
1207
1208 LED_D_ON();
1209 // Program the data blocks for supplied ID
1210 // and the block 0 for HID format
1211 T55xxWriteBlock(data1,1,0,0);
1212 T55xxWriteBlock(data2,2,0,0);
1213
1214 //Config Block
1215 T55xxWriteBlock(0x00147040,0,0,0);
1216 LED_D_OFF();
1217
1218 DbpString("DONE!");
1219 }
1220
1221 // Define 9bit header for EM410x tags
1222 #define EM410X_HEADER 0x1FF
1223 #define EM410X_ID_LENGTH 40
1224
1225 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1226 {
1227 int i, id_bit;
1228 uint64_t id = EM410X_HEADER;
1229 uint64_t rev_id = 0; // reversed ID
1230 int c_parity[4]; // column parity
1231 int r_parity = 0; // row parity
1232 uint32_t clock = 0;
1233
1234 // Reverse ID bits given as parameter (for simpler operations)
1235 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1236 if (i < 32) {
1237 rev_id = (rev_id << 1) | (id_lo & 1);
1238 id_lo >>= 1;
1239 } else {
1240 rev_id = (rev_id << 1) | (id_hi & 1);
1241 id_hi >>= 1;
1242 }
1243 }
1244
1245 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1246 id_bit = rev_id & 1;
1247
1248 if (i % 4 == 0) {
1249 // Don't write row parity bit at start of parsing
1250 if (i)
1251 id = (id << 1) | r_parity;
1252 // Start counting parity for new row
1253 r_parity = id_bit;
1254 } else {
1255 // Count row parity
1256 r_parity ^= id_bit;
1257 }
1258
1259 // First elements in column?
1260 if (i < 4)
1261 // Fill out first elements
1262 c_parity[i] = id_bit;
1263 else
1264 // Count column parity
1265 c_parity[i % 4] ^= id_bit;
1266
1267 // Insert ID bit
1268 id = (id << 1) | id_bit;
1269 rev_id >>= 1;
1270 }
1271
1272 // Insert parity bit of last row
1273 id = (id << 1) | r_parity;
1274
1275 // Fill out column parity at the end of tag
1276 for (i = 0; i < 4; ++i)
1277 id = (id << 1) | c_parity[i];
1278
1279 // Add stop bit
1280 id <<= 1;
1281
1282 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1283 LED_D_ON();
1284
1285 // Write EM410x ID
1286 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1287 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1288
1289 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1290 if (card) {
1291 // Clock rate is stored in bits 8-15 of the card value
1292 clock = (card & 0xFF00) >> 8;
1293 Dbprintf("Clock rate: %d", clock);
1294 switch (clock)
1295 {
1296 case 32:
1297 clock = T55x7_BITRATE_RF_32;
1298 break;
1299 case 16:
1300 clock = T55x7_BITRATE_RF_16;
1301 break;
1302 case 0:
1303 // A value of 0 is assumed to be 64 for backwards-compatibility
1304 // Fall through...
1305 case 64:
1306 clock = T55x7_BITRATE_RF_64;
1307 break;
1308 default:
1309 Dbprintf("Invalid clock rate: %d", clock);
1310 return;
1311 }
1312
1313 // Writing configuration for T55x7 tag
1314 T55xxWriteBlock(clock |
1315 T55x7_MODULATION_MANCHESTER |
1316 2 << T55x7_MAXBLOCK_SHIFT,
1317 0, 0, 0);
1318 }
1319 else
1320 // Writing configuration for T5555(Q5) tag
1321 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1322 T5555_MODULATION_MANCHESTER |
1323 2 << T5555_MAXBLOCK_SHIFT,
1324 0, 0, 0);
1325
1326 LED_D_OFF();
1327 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1328 (uint32_t)(id >> 32), (uint32_t)id);
1329 }
1330
1331 // Clone Indala 64-bit tag by UID to T55x7
1332 void CopyIndala64toT55x7(int hi, int lo)
1333 {
1334 //Program the 2 data blocks for supplied 64bit UID
1335 // and the block 0 for Indala64 format
1336 T55xxWriteBlock(hi,1,0,0);
1337 T55xxWriteBlock(lo,2,0,0);
1338 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1339 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1340 T55x7_MODULATION_PSK1 |
1341 2 << T55x7_MAXBLOCK_SHIFT,
1342 0, 0, 0);
1343 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1344 // T5567WriteBlock(0x603E1042,0);
1345
1346 DbpString("DONE!");
1347 }
1348
1349 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1350 {
1351 //Program the 7 data blocks for supplied 224bit UID
1352 // and the block 0 for Indala224 format
1353 T55xxWriteBlock(uid1,1,0,0);
1354 T55xxWriteBlock(uid2,2,0,0);
1355 T55xxWriteBlock(uid3,3,0,0);
1356 T55xxWriteBlock(uid4,4,0,0);
1357 T55xxWriteBlock(uid5,5,0,0);
1358 T55xxWriteBlock(uid6,6,0,0);
1359 T55xxWriteBlock(uid7,7,0,0);
1360 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1361 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1362 T55x7_MODULATION_PSK1 |
1363 7 << T55x7_MAXBLOCK_SHIFT,
1364 0,0,0);
1365 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1366 // T5567WriteBlock(0x603E10E2,0);
1367
1368 DbpString("DONE!");
1369 }
1370
1371
1372 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1373 #define max(x,y) ( x<y ? y:x)
1374
1375 int DemodPCF7931(uint8_t **outBlocks) {
1376 uint8_t BitStream[256];
1377 uint8_t Blocks[8][16];
1378 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1379 int GraphTraceLen = sizeof(BigBuf);
1380 int i, j, lastval, bitidx, half_switch;
1381 int clock = 64;
1382 int tolerance = clock / 8;
1383 int pmc, block_done;
1384 int lc, warnings = 0;
1385 int num_blocks = 0;
1386 int lmin=128, lmax=128;
1387 uint8_t dir;
1388
1389 AcquireRawAdcSamples125k(0);
1390
1391 lmin = 64;
1392 lmax = 192;
1393
1394 i = 2;
1395
1396 /* Find first local max/min */
1397 if(GraphBuffer[1] > GraphBuffer[0]) {
1398 while(i < GraphTraceLen) {
1399 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1400 break;
1401 i++;
1402 }
1403 dir = 0;
1404 }
1405 else {
1406 while(i < GraphTraceLen) {
1407 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1408 break;
1409 i++;
1410 }
1411 dir = 1;
1412 }
1413
1414 lastval = i++;
1415 half_switch = 0;
1416 pmc = 0;
1417 block_done = 0;
1418
1419 for (bitidx = 0; i < GraphTraceLen; i++)
1420 {
1421 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1422 {
1423 lc = i - lastval;
1424 lastval = i;
1425
1426 // Switch depending on lc length:
1427 // Tolerance is 1/8 of clock rate (arbitrary)
1428 if (abs(lc-clock/4) < tolerance) {
1429 // 16T0
1430 if((i - pmc) == lc) { /* 16T0 was previous one */
1431 /* It's a PMC ! */
1432 i += (128+127+16+32+33+16)-1;
1433 lastval = i;
1434 pmc = 0;
1435 block_done = 1;
1436 }
1437 else {
1438 pmc = i;
1439 }
1440 } else if (abs(lc-clock/2) < tolerance) {
1441 // 32TO
1442 if((i - pmc) == lc) { /* 16T0 was previous one */
1443 /* It's a PMC ! */
1444 i += (128+127+16+32+33)-1;
1445 lastval = i;
1446 pmc = 0;
1447 block_done = 1;
1448 }
1449 else if(half_switch == 1) {
1450 BitStream[bitidx++] = 0;
1451 half_switch = 0;
1452 }
1453 else
1454 half_switch++;
1455 } else if (abs(lc-clock) < tolerance) {
1456 // 64TO
1457 BitStream[bitidx++] = 1;
1458 } else {
1459 // Error
1460 warnings++;
1461 if (warnings > 10)
1462 {
1463 Dbprintf("Error: too many detection errors, aborting.");
1464 return 0;
1465 }
1466 }
1467
1468 if(block_done == 1) {
1469 if(bitidx == 128) {
1470 for(j=0; j<16; j++) {
1471 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1472 64*BitStream[j*8+6]+
1473 32*BitStream[j*8+5]+
1474 16*BitStream[j*8+4]+
1475 8*BitStream[j*8+3]+
1476 4*BitStream[j*8+2]+
1477 2*BitStream[j*8+1]+
1478 BitStream[j*8];
1479 }
1480 num_blocks++;
1481 }
1482 bitidx = 0;
1483 block_done = 0;
1484 half_switch = 0;
1485 }
1486 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1487 else dir = 1;
1488 }
1489 if(bitidx==255)
1490 bitidx=0;
1491 warnings = 0;
1492 if(num_blocks == 4) break;
1493 }
1494 memcpy(outBlocks, Blocks, 16*num_blocks);
1495 return num_blocks;
1496 }
1497
1498 int IsBlock0PCF7931(uint8_t *Block) {
1499 // Assume RFU means 0 :)
1500 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1501 return 1;
1502 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1503 return 1;
1504 return 0;
1505 }
1506
1507 int IsBlock1PCF7931(uint8_t *Block) {
1508 // Assume RFU means 0 :)
1509 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1510 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1511 return 1;
1512
1513 return 0;
1514 }
1515 #define ALLOC 16
1516
1517 void ReadPCF7931() {
1518 uint8_t Blocks[8][17];
1519 uint8_t tmpBlocks[4][16];
1520 int i, j, ind, ind2, n;
1521 int num_blocks = 0;
1522 int max_blocks = 8;
1523 int ident = 0;
1524 int error = 0;
1525 int tries = 0;
1526
1527 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1528
1529 do {
1530 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1531 n = DemodPCF7931((uint8_t**)tmpBlocks);
1532 if(!n)
1533 error++;
1534 if(error==10 && num_blocks == 0) {
1535 Dbprintf("Error, no tag or bad tag");
1536 return;
1537 }
1538 else if (tries==20 || error==10) {
1539 Dbprintf("Error reading the tag");
1540 Dbprintf("Here is the partial content");
1541 goto end;
1542 }
1543
1544 for(i=0; i<n; i++)
1545 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1546 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1547 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1548 if(!ident) {
1549 for(i=0; i<n; i++) {
1550 if(IsBlock0PCF7931(tmpBlocks[i])) {
1551 // Found block 0 ?
1552 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1553 // Found block 1!
1554 // \o/
1555 ident = 1;
1556 memcpy(Blocks[0], tmpBlocks[i], 16);
1557 Blocks[0][ALLOC] = 1;
1558 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1559 Blocks[1][ALLOC] = 1;
1560 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1561 // Debug print
1562 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1563 num_blocks = 2;
1564 // Handle following blocks
1565 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1566 if(j==n) j=0;
1567 if(j==i) break;
1568 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1569 Blocks[ind2][ALLOC] = 1;
1570 }
1571 break;
1572 }
1573 }
1574 }
1575 }
1576 else {
1577 for(i=0; i<n; i++) { // Look for identical block in known blocks
1578 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1579 for(j=0; j<max_blocks; j++) {
1580 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1581 // Found an identical block
1582 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1583 if(ind2 < 0)
1584 ind2 = max_blocks;
1585 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1586 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1587 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1588 Blocks[ind2][ALLOC] = 1;
1589 num_blocks++;
1590 if(num_blocks == max_blocks) goto end;
1591 }
1592 }
1593 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1594 if(ind2 > max_blocks)
1595 ind2 = 0;
1596 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1597 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1598 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1599 Blocks[ind2][ALLOC] = 1;
1600 num_blocks++;
1601 if(num_blocks == max_blocks) goto end;
1602 }
1603 }
1604 }
1605 }
1606 }
1607 }
1608 }
1609 tries++;
1610 if (BUTTON_PRESS()) return;
1611 } while (num_blocks != max_blocks);
1612 end:
1613 Dbprintf("-----------------------------------------");
1614 Dbprintf("Memory content:");
1615 Dbprintf("-----------------------------------------");
1616 for(i=0; i<max_blocks; i++) {
1617 if(Blocks[i][ALLOC]==1)
1618 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1619 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1620 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1621 else
1622 Dbprintf("<missing block %d>", i);
1623 }
1624 Dbprintf("-----------------------------------------");
1625
1626 return ;
1627 }
1628
1629
1630 //-----------------------------------
1631 // EM4469 / EM4305 routines
1632 //-----------------------------------
1633 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1634 #define FWD_CMD_WRITE 0xA
1635 #define FWD_CMD_READ 0x9
1636 #define FWD_CMD_DISABLE 0x5
1637
1638
1639 uint8_t forwardLink_data[64]; //array of forwarded bits
1640 uint8_t * forward_ptr; //ptr for forward message preparation
1641 uint8_t fwd_bit_sz; //forwardlink bit counter
1642 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1643
1644 //====================================================================
1645 // prepares command bits
1646 // see EM4469 spec
1647 //====================================================================
1648 //--------------------------------------------------------------------
1649 uint8_t Prepare_Cmd( uint8_t cmd ) {
1650 //--------------------------------------------------------------------
1651
1652 *forward_ptr++ = 0; //start bit
1653 *forward_ptr++ = 0; //second pause for 4050 code
1654
1655 *forward_ptr++ = cmd;
1656 cmd >>= 1;
1657 *forward_ptr++ = cmd;
1658 cmd >>= 1;
1659 *forward_ptr++ = cmd;
1660 cmd >>= 1;
1661 *forward_ptr++ = cmd;
1662
1663 return 6; //return number of emited bits
1664 }
1665
1666 //====================================================================
1667 // prepares address bits
1668 // see EM4469 spec
1669 //====================================================================
1670
1671 //--------------------------------------------------------------------
1672 uint8_t Prepare_Addr( uint8_t addr ) {
1673 //--------------------------------------------------------------------
1674
1675 register uint8_t line_parity;
1676
1677 uint8_t i;
1678 line_parity = 0;
1679 for(i=0;i<6;i++) {
1680 *forward_ptr++ = addr;
1681 line_parity ^= addr;
1682 addr >>= 1;
1683 }
1684
1685 *forward_ptr++ = (line_parity & 1);
1686
1687 return 7; //return number of emited bits
1688 }
1689
1690 //====================================================================
1691 // prepares data bits intreleaved with parity bits
1692 // see EM4469 spec
1693 //====================================================================
1694
1695 //--------------------------------------------------------------------
1696 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1697 //--------------------------------------------------------------------
1698
1699 register uint8_t line_parity;
1700 register uint8_t column_parity;
1701 register uint8_t i, j;
1702 register uint16_t data;
1703
1704 data = data_low;
1705 column_parity = 0;
1706
1707 for(i=0; i<4; i++) {
1708 line_parity = 0;
1709 for(j=0; j<8; j++) {
1710 line_parity ^= data;
1711 column_parity ^= (data & 1) << j;
1712 *forward_ptr++ = data;
1713 data >>= 1;
1714 }
1715 *forward_ptr++ = line_parity;
1716 if(i == 1)
1717 data = data_hi;
1718 }
1719
1720 for(j=0; j<8; j++) {
1721 *forward_ptr++ = column_parity;
1722 column_parity >>= 1;
1723 }
1724 *forward_ptr = 0;
1725
1726 return 45; //return number of emited bits
1727 }
1728
1729 //====================================================================
1730 // Forward Link send function
1731 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1732 // fwd_bit_count set with number of bits to be sent
1733 //====================================================================
1734 void SendForward(uint8_t fwd_bit_count) {
1735
1736 fwd_write_ptr = forwardLink_data;
1737 fwd_bit_sz = fwd_bit_count;
1738
1739 LED_D_ON();
1740
1741 //Field on
1742 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1743 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1744 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1745
1746 // Give it a bit of time for the resonant antenna to settle.
1747 // And for the tag to fully power up
1748 SpinDelay(150);
1749
1750 // force 1st mod pulse (start gap must be longer for 4305)
1751 fwd_bit_sz--; //prepare next bit modulation
1752 fwd_write_ptr++;
1753 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1754 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1755 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1756 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1757 SpinDelayUs(16*8); //16 cycles on (8us each)
1758
1759 // now start writting
1760 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1761 if(((*fwd_write_ptr++) & 1) == 1)
1762 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1763 else {
1764 //These timings work for 4469/4269/4305 (with the 55*8 above)
1765 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1766 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1767 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1768 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1769 SpinDelayUs(9*8); //16 cycles on (8us each)
1770 }
1771 }
1772 }
1773
1774
1775 void EM4xLogin(uint32_t Password) {
1776
1777 uint8_t fwd_bit_count;
1778
1779 forward_ptr = forwardLink_data;
1780 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1781 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1782
1783 SendForward(fwd_bit_count);
1784
1785 //Wait for command to complete
1786 SpinDelay(20);
1787
1788 }
1789
1790 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1791
1792 uint8_t *dest = mifare_get_bigbufptr();
1793 uint16_t bufferlength = 12000;
1794 uint32_t i = 0;
1795
1796 // Clear destination buffer before sending the command 0x80 = average.
1797 memset(dest, 0x80, bufferlength);
1798
1799 uint8_t fwd_bit_count;
1800
1801 //If password mode do login
1802 if (PwdMode == 1) EM4xLogin(Pwd);
1803
1804 forward_ptr = forwardLink_data;
1805 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1806 fwd_bit_count += Prepare_Addr( Address );
1807
1808 // Connect the A/D to the peak-detected low-frequency path.
1809 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1810 // Now set up the SSC to get the ADC samples that are now streaming at us.
1811 FpgaSetupSsc();
1812
1813 SendForward(fwd_bit_count);
1814
1815 // // Turn field on to read the response
1816 // TurnReadLFOn();
1817
1818 // Now do the acquisition
1819 i = 0;
1820 for(;;) {
1821 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1822 AT91C_BASE_SSC->SSC_THR = 0x43;
1823 }
1824 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1825 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1826 ++i;
1827 if (i >= bufferlength) break;
1828 }
1829 }
1830
1831 cmd_send(CMD_ACK,0,0,0,0,0);
1832 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1833 LED_D_OFF();
1834 }
1835
1836 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1837
1838 uint8_t fwd_bit_count;
1839
1840 //If password mode do login
1841 if (PwdMode == 1) EM4xLogin(Pwd);
1842
1843 forward_ptr = forwardLink_data;
1844 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1845 fwd_bit_count += Prepare_Addr( Address );
1846 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1847
1848 SendForward(fwd_bit_count);
1849
1850 //Wait for write to complete
1851 SpinDelay(20);
1852 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1853 LED_D_OFF();
1854 }
Proxmark3 GIT tracking
Impressum, Datenschutz