]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of https://github.com/Proxmark/proxmark3
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19
20
21 /**
22 * Function to do a modulation and then get samples.
23 * @param delay_off
24 * @param period_0
25 * @param period_1
26 * @param command
27 */
28 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
29 {
30
31 int divisor_used = 95; // 125 KHz
32 // see if 'h' was specified
33
34 if (command[strlen((char *) command) - 1] == 'h')
35 divisor_used = 88; // 134.8 KHz
36
37 sample_config sc = { 0,0,1, divisor_used, 0};
38 setSamplingConfig(&sc);
39
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
43 SpinDelay(2500);
44
45 LFSetupFPGAForADC(sc.divisor, 1);
46
47 // And a little more time for the tag to fully power up
48 SpinDelay(2000);
49
50 // now modulate the reader field
51 while(*command != '\0' && *command != ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
53 LED_D_OFF();
54 SpinDelayUs(delay_off);
55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
56
57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
58 LED_D_ON();
59 if(*(command++) == '0')
60 SpinDelayUs(period_0);
61 else
62 SpinDelayUs(period_1);
63 }
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
65 LED_D_OFF();
66 SpinDelayUs(delay_off);
67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
68
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
70
71 // now do the read
72 DoAcquisition_config(false);
73 }
74
75 /* blank r/w tag data stream
76 ...0000000000000000 01111111
77 1010101010101010101010101010101010101010101010101010101010101010
78 0011010010100001
79 01111111
80 101010101010101[0]000...
81
82 [5555fe852c5555555555555555fe0000]
83 */
84 void ReadTItag(void)
85 {
86 // some hardcoded initial params
87 // when we read a TI tag we sample the zerocross line at 2Mhz
88 // TI tags modulate a 1 as 16 cycles of 123.2Khz
89 // TI tags modulate a 0 as 16 cycles of 134.2Khz
90 #define FSAMPLE 2000000
91 #define FREQLO 123200
92 #define FREQHI 134200
93
94 signed char *dest = (signed char *)BigBuf_get_addr();
95 uint16_t n = BigBuf_max_traceLen();
96 // 128 bit shift register [shift3:shift2:shift1:shift0]
97 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
98
99 int i, cycles=0, samples=0;
100 // how many sample points fit in 16 cycles of each frequency
101 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
102 // when to tell if we're close enough to one freq or another
103 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
104
105 // TI tags charge at 134.2Khz
106 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
107 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
108
109 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
110 // connects to SSP_DIN and the SSP_DOUT logic level controls
111 // whether we're modulating the antenna (high)
112 // or listening to the antenna (low)
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
114
115 // get TI tag data into the buffer
116 AcquireTiType();
117
118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
119
120 for (i=0; i<n-1; i++) {
121 // count cycles by looking for lo to hi zero crossings
122 if ( (dest[i]<0) && (dest[i+1]>0) ) {
123 cycles++;
124 // after 16 cycles, measure the frequency
125 if (cycles>15) {
126 cycles=0;
127 samples=i-samples; // number of samples in these 16 cycles
128
129 // TI bits are coming to us lsb first so shift them
130 // right through our 128 bit right shift register
131 shift0 = (shift0>>1) | (shift1 << 31);
132 shift1 = (shift1>>1) | (shift2 << 31);
133 shift2 = (shift2>>1) | (shift3 << 31);
134 shift3 >>= 1;
135
136 // check if the cycles fall close to the number
137 // expected for either the low or high frequency
138 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
139 // low frequency represents a 1
140 shift3 |= (1<<31);
141 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
142 // high frequency represents a 0
143 } else {
144 // probably detected a gay waveform or noise
145 // use this as gaydar or discard shift register and start again
146 shift3 = shift2 = shift1 = shift0 = 0;
147 }
148 samples = i;
149
150 // for each bit we receive, test if we've detected a valid tag
151
152 // if we see 17 zeroes followed by 6 ones, we might have a tag
153 // remember the bits are backwards
154 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
155 // if start and end bytes match, we have a tag so break out of the loop
156 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
157 cycles = 0xF0B; //use this as a flag (ugly but whatever)
158 break;
159 }
160 }
161 }
162 }
163 }
164
165 // if flag is set we have a tag
166 if (cycles!=0xF0B) {
167 DbpString("Info: No valid tag detected.");
168 } else {
169 // put 64 bit data into shift1 and shift0
170 shift0 = (shift0>>24) | (shift1 << 8);
171 shift1 = (shift1>>24) | (shift2 << 8);
172
173 // align 16 bit crc into lower half of shift2
174 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
175
176 // if r/w tag, check ident match
177 if (shift3 & (1<<15) ) {
178 DbpString("Info: TI tag is rewriteable");
179 // only 15 bits compare, last bit of ident is not valid
180 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
181 DbpString("Error: Ident mismatch!");
182 } else {
183 DbpString("Info: TI tag ident is valid");
184 }
185 } else {
186 DbpString("Info: TI tag is readonly");
187 }
188
189 // WARNING the order of the bytes in which we calc crc below needs checking
190 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
191 // bytes in reverse or something
192 // calculate CRC
193 uint32_t crc=0;
194
195 crc = update_crc16(crc, (shift0)&0xff);
196 crc = update_crc16(crc, (shift0>>8)&0xff);
197 crc = update_crc16(crc, (shift0>>16)&0xff);
198 crc = update_crc16(crc, (shift0>>24)&0xff);
199 crc = update_crc16(crc, (shift1)&0xff);
200 crc = update_crc16(crc, (shift1>>8)&0xff);
201 crc = update_crc16(crc, (shift1>>16)&0xff);
202 crc = update_crc16(crc, (shift1>>24)&0xff);
203
204 Dbprintf("Info: Tag data: %x%08x, crc=%x",
205 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
206 if (crc != (shift2&0xffff)) {
207 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
208 } else {
209 DbpString("Info: CRC is good");
210 }
211 }
212 }
213
214 void WriteTIbyte(uint8_t b)
215 {
216 int i = 0;
217
218 // modulate 8 bits out to the antenna
219 for (i=0; i<8; i++)
220 {
221 if (b&(1<<i)) {
222 // stop modulating antenna
223 LOW(GPIO_SSC_DOUT);
224 SpinDelayUs(1000);
225 // modulate antenna
226 HIGH(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 } else {
229 // stop modulating antenna
230 LOW(GPIO_SSC_DOUT);
231 SpinDelayUs(300);
232 // modulate antenna
233 HIGH(GPIO_SSC_DOUT);
234 SpinDelayUs(1700);
235 }
236 }
237 }
238
239 void AcquireTiType(void)
240 {
241 int i, j, n;
242 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
243 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
244 #define TIBUFLEN 1250
245
246 // clear buffer
247 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
248 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
249
250 // Set up the synchronous serial port
251 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
252 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
253
254 // steal this pin from the SSP and use it to control the modulation
255 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
256 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
257
258 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
259 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
260
261 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
262 // 48/2 = 24 MHz clock must be divided by 12
263 AT91C_BASE_SSC->SSC_CMR = 12;
264
265 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
266 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
267 AT91C_BASE_SSC->SSC_TCMR = 0;
268 AT91C_BASE_SSC->SSC_TFMR = 0;
269
270 LED_D_ON();
271
272 // modulate antenna
273 HIGH(GPIO_SSC_DOUT);
274
275 // Charge TI tag for 50ms.
276 SpinDelay(50);
277
278 // stop modulating antenna and listen
279 LOW(GPIO_SSC_DOUT);
280
281 LED_D_OFF();
282
283 i = 0;
284 for(;;) {
285 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
286 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
287 i++; if(i >= TIBUFLEN) break;
288 }
289 WDT_HIT();
290 }
291
292 // return stolen pin to SSP
293 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
294 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
295
296 char *dest = (char *)BigBuf_get_addr();
297 n = TIBUFLEN*32;
298 // unpack buffer
299 for (i=TIBUFLEN-1; i>=0; i--) {
300 for (j=0; j<32; j++) {
301 if(BigBuf[i] & (1 << j)) {
302 dest[--n] = 1;
303 } else {
304 dest[--n] = -1;
305 }
306 }
307 }
308 }
309
310 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
311 // if crc provided, it will be written with the data verbatim (even if bogus)
312 // if not provided a valid crc will be computed from the data and written.
313 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
314 {
315 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
316 if(crc == 0) {
317 crc = update_crc16(crc, (idlo)&0xff);
318 crc = update_crc16(crc, (idlo>>8)&0xff);
319 crc = update_crc16(crc, (idlo>>16)&0xff);
320 crc = update_crc16(crc, (idlo>>24)&0xff);
321 crc = update_crc16(crc, (idhi)&0xff);
322 crc = update_crc16(crc, (idhi>>8)&0xff);
323 crc = update_crc16(crc, (idhi>>16)&0xff);
324 crc = update_crc16(crc, (idhi>>24)&0xff);
325 }
326 Dbprintf("Writing to tag: %x%08x, crc=%x",
327 (unsigned int) idhi, (unsigned int) idlo, crc);
328
329 // TI tags charge at 134.2Khz
330 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
331 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
332 // connects to SSP_DIN and the SSP_DOUT logic level controls
333 // whether we're modulating the antenna (high)
334 // or listening to the antenna (low)
335 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
336 LED_A_ON();
337
338 // steal this pin from the SSP and use it to control the modulation
339 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
340 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
341
342 // writing algorithm:
343 // a high bit consists of a field off for 1ms and field on for 1ms
344 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
345 // initiate a charge time of 50ms (field on) then immediately start writing bits
346 // start by writing 0xBB (keyword) and 0xEB (password)
347 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
348 // finally end with 0x0300 (write frame)
349 // all data is sent lsb firts
350 // finish with 15ms programming time
351
352 // modulate antenna
353 HIGH(GPIO_SSC_DOUT);
354 SpinDelay(50); // charge time
355
356 WriteTIbyte(0xbb); // keyword
357 WriteTIbyte(0xeb); // password
358 WriteTIbyte( (idlo )&0xff );
359 WriteTIbyte( (idlo>>8 )&0xff );
360 WriteTIbyte( (idlo>>16)&0xff );
361 WriteTIbyte( (idlo>>24)&0xff );
362 WriteTIbyte( (idhi )&0xff );
363 WriteTIbyte( (idhi>>8 )&0xff );
364 WriteTIbyte( (idhi>>16)&0xff );
365 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
366 WriteTIbyte( (crc )&0xff ); // crc lo
367 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
368 WriteTIbyte(0x00); // write frame lo
369 WriteTIbyte(0x03); // write frame hi
370 HIGH(GPIO_SSC_DOUT);
371 SpinDelay(50); // programming time
372
373 LED_A_OFF();
374
375 // get TI tag data into the buffer
376 AcquireTiType();
377
378 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
379 DbpString("Now use tiread to check");
380 }
381
382 void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)
383 {
384 int i;
385 uint8_t *tab = BigBuf_get_addr();
386
387 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
388 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
389
390 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
391
392 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
393 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
394
395 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
396 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
397
398 i = 0;
399 for(;;) {
400 //wait until SSC_CLK goes HIGH
401 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
402 if(BUTTON_PRESS()) {
403 DbpString("Stopped");
404 return;
405 }
406 WDT_HIT();
407 }
408 if (ledcontrol)
409 LED_D_ON();
410
411 if(tab[i])
412 OPEN_COIL();
413 else
414 SHORT_COIL();
415
416 if (ledcontrol)
417 LED_D_OFF();
418 //wait until SSC_CLK goes LOW
419 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
420 if(BUTTON_PRESS()) {
421 DbpString("Stopped");
422 return;
423 }
424 WDT_HIT();
425 }
426
427 i++;
428 if(i == period) {
429
430 i = 0;
431 if (gap) {
432 SHORT_COIL();
433 SpinDelayUs(gap);
434 }
435 }
436 }
437 }
438
439 #define DEBUG_FRAME_CONTENTS 1
440 void SimulateTagLowFrequencyBidir(int divisor, int t0)
441 {
442 }
443
444 // compose fc/8 fc/10 waveform (FSK2)
445 static void fc(int c, int *n)
446 {
447 uint8_t *dest = BigBuf_get_addr();
448 int idx;
449
450 // for when we want an fc8 pattern every 4 logical bits
451 if(c==0) {
452 dest[((*n)++)]=1;
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=0;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 }
461
462 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
463 if(c==8) {
464 for (idx=0; idx<6; idx++) {
465 dest[((*n)++)]=1;
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=0;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 }
474 }
475
476 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
477 if(c==10) {
478 for (idx=0; idx<5; idx++) {
479 dest[((*n)++)]=1;
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 }
490 }
491 }
492 // compose fc/X fc/Y waveform (FSKx)
493 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
494 {
495 uint8_t *dest = BigBuf_get_addr();
496 uint8_t halfFC = fc/2;
497 uint8_t wavesPerClock = clock/fc;
498 uint8_t mod = clock % fc; //modifier
499 uint8_t modAdj = fc/mod; //how often to apply modifier
500 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
501 // loop through clock - step field clock
502 for (uint8_t idx=0; idx < wavesPerClock; idx++){
503 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
504 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
505 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
506 *n += fc;
507 }
508 if (mod>0) (*modCnt)++;
509 if ((mod>0) && modAdjOk){ //fsk2
510 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
511 memset(dest+(*n), 0, fc-halfFC);
512 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
513 *n += fc;
514 }
515 }
516 if (mod>0 && !modAdjOk){ //fsk1
517 memset(dest+(*n), 0, mod-(mod/2));
518 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
519 *n += mod;
520 }
521 }
522
523 // prepare a waveform pattern in the buffer based on the ID given then
524 // simulate a HID tag until the button is pressed
525 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
526 {
527 int n=0, i=0;
528 /*
529 HID tag bitstream format
530 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
531 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
532 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
533 A fc8 is inserted before every 4 bits
534 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
535 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
536 */
537
538 if (hi>0xFFF) {
539 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
540 return;
541 }
542 fc(0,&n);
543 // special start of frame marker containing invalid bit sequences
544 fc(8, &n); fc(8, &n); // invalid
545 fc(8, &n); fc(10, &n); // logical 0
546 fc(10, &n); fc(10, &n); // invalid
547 fc(8, &n); fc(10, &n); // logical 0
548
549 WDT_HIT();
550 // manchester encode bits 43 to 32
551 for (i=11; i>=0; i--) {
552 if ((i%4)==3) fc(0,&n);
553 if ((hi>>i)&1) {
554 fc(10, &n); fc(8, &n); // low-high transition
555 } else {
556 fc(8, &n); fc(10, &n); // high-low transition
557 }
558 }
559
560 WDT_HIT();
561 // manchester encode bits 31 to 0
562 for (i=31; i>=0; i--) {
563 if ((i%4)==3) fc(0,&n);
564 if ((lo>>i)&1) {
565 fc(10, &n); fc(8, &n); // low-high transition
566 } else {
567 fc(8, &n); fc(10, &n); // high-low transition
568 }
569 }
570
571 if (ledcontrol)
572 LED_A_ON();
573 SimulateTagLowFrequency(n, 0, ledcontrol);
574
575 if (ledcontrol)
576 LED_A_OFF();
577 }
578
579 // prepare a waveform pattern in the buffer based on the ID given then
580 // simulate a FSK tag until the button is pressed
581 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
582 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
583 {
584 int ledcontrol=1;
585 int n=0, i=0;
586 uint8_t fcHigh = arg1 >> 8;
587 uint8_t fcLow = arg1 & 0xFF;
588 uint16_t modCnt = 0;
589 uint8_t clk = arg2 & 0xFF;
590 uint8_t invert = (arg2 >> 8) & 1;
591
592 for (i=0; i<size; i++){
593 if (BitStream[i] == invert){
594 fcAll(fcLow, &n, clk, &modCnt);
595 } else {
596 fcAll(fcHigh, &n, clk, &modCnt);
597 }
598 }
599 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
600 /*Dbprintf("DEBUG: First 32:");
601 uint8_t *dest = BigBuf_get_addr();
602 i=0;
603 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
604 i+=16;
605 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
606 */
607 if (ledcontrol)
608 LED_A_ON();
609
610 SimulateTagLowFrequency(n, 0, ledcontrol);
611
612 if (ledcontrol)
613 LED_A_OFF();
614 }
615
616 // compose ask waveform for one bit(ASK)
617 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
618 {
619 uint8_t *dest = BigBuf_get_addr();
620 uint8_t halfClk = clock/2;
621 // c = current bit 1 or 0
622 if (manchester){
623 memset(dest+(*n), c, halfClk);
624 memset(dest+(*n) + halfClk, c^1, halfClk);
625 } else {
626 memset(dest+(*n), c, clock);
627 }
628 *n += clock;
629 }
630
631 // args clock, ask/man or askraw, invert, transmission separator
632 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
633 {
634 int ledcontrol = 1;
635 int n=0, i=0;
636 uint8_t clk = (arg1 >> 8) & 0xFF;
637 uint8_t manchester = arg1 & 1;
638 uint8_t separator = arg2 & 1;
639 uint8_t invert = (arg2 >> 8) & 1;
640 for (i=0; i<size; i++){
641 askSimBit(BitStream[i]^invert, &n, clk, manchester);
642 }
643 if (manchester==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
644 for (i=0; i<size; i++){
645 askSimBit(BitStream[i]^invert^1, &n, clk, manchester);
646 }
647 }
648 if (separator==1) Dbprintf("sorry but separator option not yet available");
649
650 Dbprintf("Simulating with clk: %d, invert: %d, manchester: %d, separator: %d, n: %d",clk, invert, manchester, separator, n);
651 //DEBUG
652 //Dbprintf("First 32:");
653 //uint8_t *dest = BigBuf_get_addr();
654 //i=0;
655 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
656 //i+=16;
657 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
658
659 if (ledcontrol)
660 LED_A_ON();
661
662 SimulateTagLowFrequency(n, 0, ledcontrol);
663
664 if (ledcontrol)
665 LED_A_OFF();
666 }
667
668 //carrier can be 2,4 or 8
669 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
670 {
671 uint8_t *dest = BigBuf_get_addr();
672 uint8_t halfWave = waveLen/2;
673 //uint8_t idx;
674 int i = 0;
675 if (phaseChg){
676 // write phase change
677 memset(dest+(*n), *curPhase^1, halfWave);
678 memset(dest+(*n) + halfWave, *curPhase, halfWave);
679 *n += waveLen;
680 *curPhase ^= 1;
681 i += waveLen;
682 }
683 //write each normal clock wave for the clock duration
684 for (; i < clk; i+=waveLen){
685 memset(dest+(*n), *curPhase, halfWave);
686 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
687 *n += waveLen;
688 }
689 }
690
691 // args clock, carrier, invert,
692 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
693 {
694 int ledcontrol=1;
695 int n=0, i=0;
696 uint8_t clk = arg1 >> 8;
697 uint8_t carrier = arg1 & 0xFF;
698 uint8_t invert = arg2 & 0xFF;
699 uint8_t curPhase = 0;
700 for (i=0; i<size; i++){
701 if (BitStream[i] == curPhase){
702 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
703 } else {
704 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
705 }
706 }
707 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
708 //Dbprintf("DEBUG: First 32:");
709 //uint8_t *dest = BigBuf_get_addr();
710 //i=0;
711 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
712 //i+=16;
713 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
714
715 if (ledcontrol)
716 LED_A_ON();
717 SimulateTagLowFrequency(n, 0, ledcontrol);
718
719 if (ledcontrol)
720 LED_A_OFF();
721 }
722
723 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
724 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
725 {
726 uint8_t *dest = BigBuf_get_addr();
727 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
728 size_t size = 0;
729 uint32_t hi2=0, hi=0, lo=0;
730 int idx=0;
731 // Configure to go in 125Khz listen mode
732 LFSetupFPGAForADC(95, true);
733
734 while(!BUTTON_PRESS()) {
735
736 WDT_HIT();
737 if (ledcontrol) LED_A_ON();
738
739 DoAcquisition_default(-1,true);
740 // FSK demodulator
741 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
742 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
743
744 if (idx>0 && lo>0){
745 // final loop, go over previously decoded manchester data and decode into usable tag ID
746 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
747 if (hi2 != 0){ //extra large HID tags
748 Dbprintf("TAG ID: %x%08x%08x (%d)",
749 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
750 }else { //standard HID tags <38 bits
751 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
752 uint8_t bitlen = 0;
753 uint32_t fc = 0;
754 uint32_t cardnum = 0;
755 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
756 uint32_t lo2=0;
757 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
758 uint8_t idx3 = 1;
759 while(lo2 > 1){ //find last bit set to 1 (format len bit)
760 lo2=lo2 >> 1;
761 idx3++;
762 }
763 bitlen = idx3+19;
764 fc =0;
765 cardnum=0;
766 if(bitlen == 26){
767 cardnum = (lo>>1)&0xFFFF;
768 fc = (lo>>17)&0xFF;
769 }
770 if(bitlen == 37){
771 cardnum = (lo>>1)&0x7FFFF;
772 fc = ((hi&0xF)<<12)|(lo>>20);
773 }
774 if(bitlen == 34){
775 cardnum = (lo>>1)&0xFFFF;
776 fc= ((hi&1)<<15)|(lo>>17);
777 }
778 if(bitlen == 35){
779 cardnum = (lo>>1)&0xFFFFF;
780 fc = ((hi&1)<<11)|(lo>>21);
781 }
782 }
783 else { //if bit 38 is not set then 37 bit format is used
784 bitlen= 37;
785 fc =0;
786 cardnum=0;
787 if(bitlen==37){
788 cardnum = (lo>>1)&0x7FFFF;
789 fc = ((hi&0xF)<<12)|(lo>>20);
790 }
791 }
792 //Dbprintf("TAG ID: %x%08x (%d)",
793 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
794 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
795 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
796 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
797 }
798 if (findone){
799 if (ledcontrol) LED_A_OFF();
800 *high = hi;
801 *low = lo;
802 return;
803 }
804 // reset
805 hi2 = hi = lo = 0;
806 }
807 WDT_HIT();
808 }
809 DbpString("Stopped");
810 if (ledcontrol) LED_A_OFF();
811 }
812
813 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
814 {
815 uint8_t *dest = BigBuf_get_addr();
816
817 size_t size=0, idx=0;
818 int clk=0, invert=0, errCnt=0, maxErr=20;
819 uint64_t lo=0;
820 // Configure to go in 125Khz listen mode
821 LFSetupFPGAForADC(95, true);
822
823 while(!BUTTON_PRESS()) {
824
825 WDT_HIT();
826 if (ledcontrol) LED_A_ON();
827
828 DoAcquisition_default(-1,true);
829 size = BigBuf_max_traceLen();
830 //Dbprintf("DEBUG: Buffer got");
831 //askdemod and manchester decode
832 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
833 //Dbprintf("DEBUG: ASK Got");
834 WDT_HIT();
835
836 if (errCnt>=0){
837 lo = Em410xDecode(dest, &size, &idx);
838 //Dbprintf("DEBUG: EM GOT");
839 if (lo>0){
840 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
841 (uint32_t)(lo>>32),
842 (uint32_t)lo,
843 (uint32_t)(lo&0xFFFF),
844 (uint32_t)((lo>>16LL) & 0xFF),
845 (uint32_t)(lo & 0xFFFFFF));
846 }
847 if (findone){
848 if (ledcontrol) LED_A_OFF();
849 *high=lo>>32;
850 *low=lo & 0xFFFFFFFF;
851 return;
852 }
853 } else{
854 //Dbprintf("DEBUG: No Tag");
855 }
856 WDT_HIT();
857 lo = 0;
858 clk=0;
859 invert=0;
860 errCnt=0;
861 size=0;
862 }
863 DbpString("Stopped");
864 if (ledcontrol) LED_A_OFF();
865 }
866
867 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
868 {
869 uint8_t *dest = BigBuf_get_addr();
870 int idx=0;
871 uint32_t code=0, code2=0;
872 uint8_t version=0;
873 uint8_t facilitycode=0;
874 uint16_t number=0;
875 // Configure to go in 125Khz listen mode
876 LFSetupFPGAForADC(95, true);
877
878 while(!BUTTON_PRESS()) {
879 WDT_HIT();
880 if (ledcontrol) LED_A_ON();
881 DoAcquisition_default(-1,true);
882 //fskdemod and get start index
883 WDT_HIT();
884 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
885 if (idx>0){
886 //valid tag found
887
888 //Index map
889 //0 10 20 30 40 50 60
890 //| | | | | | |
891 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
892 //-----------------------------------------------------------------------------
893 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
894 //
895 //XSF(version)facility:codeone+codetwo
896 //Handle the data
897 if(findone){ //only print binary if we are doing one
898 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
899 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
900 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
901 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
902 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
903 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
904 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
905 }
906 code = bytebits_to_byte(dest+idx,32);
907 code2 = bytebits_to_byte(dest+idx+32,32);
908 version = bytebits_to_byte(dest+idx+27,8); //14,4
909 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
910 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
911
912 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
913 // if we're only looking for one tag
914 if (findone){
915 if (ledcontrol) LED_A_OFF();
916 //LED_A_OFF();
917 *high=code;
918 *low=code2;
919 return;
920 }
921 code=code2=0;
922 version=facilitycode=0;
923 number=0;
924 idx=0;
925 }
926 WDT_HIT();
927 }
928 DbpString("Stopped");
929 if (ledcontrol) LED_A_OFF();
930 }
931
932 /*------------------------------
933 * T5555/T5557/T5567 routines
934 *------------------------------
935 */
936
937 /* T55x7 configuration register definitions */
938 #define T55x7_POR_DELAY 0x00000001
939 #define T55x7_ST_TERMINATOR 0x00000008
940 #define T55x7_PWD 0x00000010
941 #define T55x7_MAXBLOCK_SHIFT 5
942 #define T55x7_AOR 0x00000200
943 #define T55x7_PSKCF_RF_2 0
944 #define T55x7_PSKCF_RF_4 0x00000400
945 #define T55x7_PSKCF_RF_8 0x00000800
946 #define T55x7_MODULATION_DIRECT 0
947 #define T55x7_MODULATION_PSK1 0x00001000
948 #define T55x7_MODULATION_PSK2 0x00002000
949 #define T55x7_MODULATION_PSK3 0x00003000
950 #define T55x7_MODULATION_FSK1 0x00004000
951 #define T55x7_MODULATION_FSK2 0x00005000
952 #define T55x7_MODULATION_FSK1a 0x00006000
953 #define T55x7_MODULATION_FSK2a 0x00007000
954 #define T55x7_MODULATION_MANCHESTER 0x00008000
955 #define T55x7_MODULATION_BIPHASE 0x00010000
956 #define T55x7_BITRATE_RF_8 0
957 #define T55x7_BITRATE_RF_16 0x00040000
958 #define T55x7_BITRATE_RF_32 0x00080000
959 #define T55x7_BITRATE_RF_40 0x000C0000
960 #define T55x7_BITRATE_RF_50 0x00100000
961 #define T55x7_BITRATE_RF_64 0x00140000
962 #define T55x7_BITRATE_RF_100 0x00180000
963 #define T55x7_BITRATE_RF_128 0x001C0000
964
965 /* T5555 (Q5) configuration register definitions */
966 #define T5555_ST_TERMINATOR 0x00000001
967 #define T5555_MAXBLOCK_SHIFT 0x00000001
968 #define T5555_MODULATION_MANCHESTER 0
969 #define T5555_MODULATION_PSK1 0x00000010
970 #define T5555_MODULATION_PSK2 0x00000020
971 #define T5555_MODULATION_PSK3 0x00000030
972 #define T5555_MODULATION_FSK1 0x00000040
973 #define T5555_MODULATION_FSK2 0x00000050
974 #define T5555_MODULATION_BIPHASE 0x00000060
975 #define T5555_MODULATION_DIRECT 0x00000070
976 #define T5555_INVERT_OUTPUT 0x00000080
977 #define T5555_PSK_RF_2 0
978 #define T5555_PSK_RF_4 0x00000100
979 #define T5555_PSK_RF_8 0x00000200
980 #define T5555_USE_PWD 0x00000400
981 #define T5555_USE_AOR 0x00000800
982 #define T5555_BITRATE_SHIFT 12
983 #define T5555_FAST_WRITE 0x00004000
984 #define T5555_PAGE_SELECT 0x00008000
985
986 /*
987 * Relevant times in microsecond
988 * To compensate antenna falling times shorten the write times
989 * and enlarge the gap ones.
990 */
991 #define START_GAP 30*8 // 10 - 50fc 250
992 #define WRITE_GAP 20*8 // 8 - 30fc
993 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
994 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
995
996 // VALUES TAKEN FROM EM4x function: SendForward
997 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
998 // WRITE_GAP = 128; (16*8)
999 // WRITE_1 = 256 32*8; (32*8)
1000
1001 // These timings work for 4469/4269/4305 (with the 55*8 above)
1002 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1003
1004 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
1005
1006 // Write one bit to card
1007 void T55xxWriteBit(int bit)
1008 {
1009 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1010 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1011 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1012 if (!bit)
1013 SpinDelayUs(WRITE_0);
1014 else
1015 SpinDelayUs(WRITE_1);
1016 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1017 SpinDelayUs(WRITE_GAP);
1018 }
1019
1020 // Write one card block in page 0, no lock
1021 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1022 {
1023 uint32_t i = 0;
1024
1025 // Set up FPGA, 125kHz
1026 // Wait for config.. (192+8190xPOW)x8 == 67ms
1027 LFSetupFPGAForADC(0, true);
1028
1029 // Now start writting
1030 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1031 SpinDelayUs(START_GAP);
1032
1033 // Opcode
1034 T55xxWriteBit(1);
1035 T55xxWriteBit(0); //Page 0
1036 if (PwdMode == 1){
1037 // Pwd
1038 for (i = 0x80000000; i != 0; i >>= 1)
1039 T55xxWriteBit(Pwd & i);
1040 }
1041 // Lock bit
1042 T55xxWriteBit(0);
1043
1044 // Data
1045 for (i = 0x80000000; i != 0; i >>= 1)
1046 T55xxWriteBit(Data & i);
1047
1048 // Block
1049 for (i = 0x04; i != 0; i >>= 1)
1050 T55xxWriteBit(Block & i);
1051
1052 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1053 // so wait a little more)
1054 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1055 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1056 SpinDelay(20);
1057 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1058 }
1059
1060 // Read one card block in page 0
1061 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1062 {
1063 uint32_t i = 0;
1064 uint8_t *dest = BigBuf_get_addr();
1065 uint16_t bufferlength = BigBuf_max_traceLen();
1066 if ( bufferlength > T55xx_SAMPLES_SIZE )
1067 bufferlength = T55xx_SAMPLES_SIZE;
1068
1069 memset(dest, 0x80, bufferlength);
1070
1071 // Set up FPGA, 125kHz
1072 // Wait for config.. (192+8190xPOW)x8 == 67ms
1073 LFSetupFPGAForADC(0, true);
1074 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1075 SpinDelayUs(START_GAP);
1076
1077 // Opcode
1078 T55xxWriteBit(1);
1079 T55xxWriteBit(0); //Page 0
1080 if (PwdMode == 1){
1081 // Pwd
1082 for (i = 0x80000000; i != 0; i >>= 1)
1083 T55xxWriteBit(Pwd & i);
1084 }
1085 // Lock bit
1086 T55xxWriteBit(0);
1087 // Block
1088 for (i = 0x04; i != 0; i >>= 1)
1089 T55xxWriteBit(Block & i);
1090
1091 // Turn field on to read the response
1092 TurnReadLFOn();
1093
1094 // Now do the acquisition
1095 i = 0;
1096 for(;;) {
1097 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1098 AT91C_BASE_SSC->SSC_THR = 0x43;
1099 LED_D_ON();
1100 }
1101 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1102 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1103 ++i;
1104 LED_D_OFF();
1105 if (i >= bufferlength) break;
1106 }
1107 }
1108
1109 cmd_send(CMD_ACK,0,0,0,0,0);
1110 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1111 LED_D_OFF();
1112 }
1113
1114 // Read card traceability data (page 1)
1115 void T55xxReadTrace(void){
1116
1117 uint32_t i = 0;
1118 uint8_t *dest = BigBuf_get_addr();
1119 uint16_t bufferlength = BigBuf_max_traceLen();
1120 if ( bufferlength > T55xx_SAMPLES_SIZE )
1121 bufferlength = T55xx_SAMPLES_SIZE;
1122
1123 memset(dest, 0x80, bufferlength);
1124
1125 LFSetupFPGAForADC(0, true);
1126 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1127 SpinDelayUs(START_GAP);
1128
1129 // Opcode
1130 T55xxWriteBit(1);
1131 T55xxWriteBit(1); //Page 1
1132
1133 // Turn field on to read the response
1134 TurnReadLFOn();
1135
1136 // Now do the acquisition
1137 for(;;) {
1138 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1139 AT91C_BASE_SSC->SSC_THR = 0x43;
1140 LED_D_ON();
1141 }
1142 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1143 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1144 ++i;
1145 LED_D_OFF();
1146
1147 if (i >= bufferlength) break;
1148 }
1149 }
1150
1151 cmd_send(CMD_ACK,0,0,0,0,0);
1152 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1153 LED_D_OFF();
1154 }
1155
1156 void TurnReadLFOn(){
1157 //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1158 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1159 // Give it a bit of time for the resonant antenna to settle.
1160 //SpinDelay(30);
1161 SpinDelayUs(9*150);
1162 }
1163
1164 /*-------------- Cloning routines -----------*/
1165 // Copy HID id to card and setup block 0 config
1166 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1167 {
1168 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1169 int last_block = 0;
1170
1171 if (longFMT){
1172 // Ensure no more than 84 bits supplied
1173 if (hi2>0xFFFFF) {
1174 DbpString("Tags can only have 84 bits.");
1175 return;
1176 }
1177 // Build the 6 data blocks for supplied 84bit ID
1178 last_block = 6;
1179 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1180 for (int i=0;i<4;i++) {
1181 if (hi2 & (1<<(19-i)))
1182 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1183 else
1184 data1 |= (1<<((3-i)*2)); // 0 -> 01
1185 }
1186
1187 data2 = 0;
1188 for (int i=0;i<16;i++) {
1189 if (hi2 & (1<<(15-i)))
1190 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1191 else
1192 data2 |= (1<<((15-i)*2)); // 0 -> 01
1193 }
1194
1195 data3 = 0;
1196 for (int i=0;i<16;i++) {
1197 if (hi & (1<<(31-i)))
1198 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1199 else
1200 data3 |= (1<<((15-i)*2)); // 0 -> 01
1201 }
1202
1203 data4 = 0;
1204 for (int i=0;i<16;i++) {
1205 if (hi & (1<<(15-i)))
1206 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1207 else
1208 data4 |= (1<<((15-i)*2)); // 0 -> 01
1209 }
1210
1211 data5 = 0;
1212 for (int i=0;i<16;i++) {
1213 if (lo & (1<<(31-i)))
1214 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1215 else
1216 data5 |= (1<<((15-i)*2)); // 0 -> 01
1217 }
1218
1219 data6 = 0;
1220 for (int i=0;i<16;i++) {
1221 if (lo & (1<<(15-i)))
1222 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1223 else
1224 data6 |= (1<<((15-i)*2)); // 0 -> 01
1225 }
1226 }
1227 else {
1228 // Ensure no more than 44 bits supplied
1229 if (hi>0xFFF) {
1230 DbpString("Tags can only have 44 bits.");
1231 return;
1232 }
1233
1234 // Build the 3 data blocks for supplied 44bit ID
1235 last_block = 3;
1236
1237 data1 = 0x1D000000; // load preamble
1238
1239 for (int i=0;i<12;i++) {
1240 if (hi & (1<<(11-i)))
1241 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1242 else
1243 data1 |= (1<<((11-i)*2)); // 0 -> 01
1244 }
1245
1246 data2 = 0;
1247 for (int i=0;i<16;i++) {
1248 if (lo & (1<<(31-i)))
1249 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1250 else
1251 data2 |= (1<<((15-i)*2)); // 0 -> 01
1252 }
1253
1254 data3 = 0;
1255 for (int i=0;i<16;i++) {
1256 if (lo & (1<<(15-i)))
1257 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1258 else
1259 data3 |= (1<<((15-i)*2)); // 0 -> 01
1260 }
1261 }
1262
1263 LED_D_ON();
1264 // Program the data blocks for supplied ID
1265 // and the block 0 for HID format
1266 T55xxWriteBlock(data1,1,0,0);
1267 T55xxWriteBlock(data2,2,0,0);
1268 T55xxWriteBlock(data3,3,0,0);
1269
1270 if (longFMT) { // if long format there are 6 blocks
1271 T55xxWriteBlock(data4,4,0,0);
1272 T55xxWriteBlock(data5,5,0,0);
1273 T55xxWriteBlock(data6,6,0,0);
1274 }
1275
1276 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1277 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1278 T55x7_MODULATION_FSK2a |
1279 last_block << T55x7_MAXBLOCK_SHIFT,
1280 0,0,0);
1281
1282 LED_D_OFF();
1283
1284 DbpString("DONE!");
1285 }
1286
1287 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1288 {
1289 int data1=0, data2=0; //up to six blocks for long format
1290
1291 data1 = hi; // load preamble
1292 data2 = lo;
1293
1294 LED_D_ON();
1295 // Program the data blocks for supplied ID
1296 // and the block 0 for HID format
1297 T55xxWriteBlock(data1,1,0,0);
1298 T55xxWriteBlock(data2,2,0,0);
1299
1300 //Config Block
1301 T55xxWriteBlock(0x00147040,0,0,0);
1302 LED_D_OFF();
1303
1304 DbpString("DONE!");
1305 }
1306
1307 // Define 9bit header for EM410x tags
1308 #define EM410X_HEADER 0x1FF
1309 #define EM410X_ID_LENGTH 40
1310
1311 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1312 {
1313 int i, id_bit;
1314 uint64_t id = EM410X_HEADER;
1315 uint64_t rev_id = 0; // reversed ID
1316 int c_parity[4]; // column parity
1317 int r_parity = 0; // row parity
1318 uint32_t clock = 0;
1319
1320 // Reverse ID bits given as parameter (for simpler operations)
1321 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1322 if (i < 32) {
1323 rev_id = (rev_id << 1) | (id_lo & 1);
1324 id_lo >>= 1;
1325 } else {
1326 rev_id = (rev_id << 1) | (id_hi & 1);
1327 id_hi >>= 1;
1328 }
1329 }
1330
1331 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1332 id_bit = rev_id & 1;
1333
1334 if (i % 4 == 0) {
1335 // Don't write row parity bit at start of parsing
1336 if (i)
1337 id = (id << 1) | r_parity;
1338 // Start counting parity for new row
1339 r_parity = id_bit;
1340 } else {
1341 // Count row parity
1342 r_parity ^= id_bit;
1343 }
1344
1345 // First elements in column?
1346 if (i < 4)
1347 // Fill out first elements
1348 c_parity[i] = id_bit;
1349 else
1350 // Count column parity
1351 c_parity[i % 4] ^= id_bit;
1352
1353 // Insert ID bit
1354 id = (id << 1) | id_bit;
1355 rev_id >>= 1;
1356 }
1357
1358 // Insert parity bit of last row
1359 id = (id << 1) | r_parity;
1360
1361 // Fill out column parity at the end of tag
1362 for (i = 0; i < 4; ++i)
1363 id = (id << 1) | c_parity[i];
1364
1365 // Add stop bit
1366 id <<= 1;
1367
1368 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1369 LED_D_ON();
1370
1371 // Write EM410x ID
1372 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1373 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1374
1375 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1376 if (card) {
1377 // Clock rate is stored in bits 8-15 of the card value
1378 clock = (card & 0xFF00) >> 8;
1379 Dbprintf("Clock rate: %d", clock);
1380 switch (clock)
1381 {
1382 case 32:
1383 clock = T55x7_BITRATE_RF_32;
1384 break;
1385 case 16:
1386 clock = T55x7_BITRATE_RF_16;
1387 break;
1388 case 0:
1389 // A value of 0 is assumed to be 64 for backwards-compatibility
1390 // Fall through...
1391 case 64:
1392 clock = T55x7_BITRATE_RF_64;
1393 break;
1394 default:
1395 Dbprintf("Invalid clock rate: %d", clock);
1396 return;
1397 }
1398
1399 // Writing configuration for T55x7 tag
1400 T55xxWriteBlock(clock |
1401 T55x7_MODULATION_MANCHESTER |
1402 2 << T55x7_MAXBLOCK_SHIFT,
1403 0, 0, 0);
1404 }
1405 else
1406 // Writing configuration for T5555(Q5) tag
1407 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1408 T5555_MODULATION_MANCHESTER |
1409 2 << T5555_MAXBLOCK_SHIFT,
1410 0, 0, 0);
1411
1412 LED_D_OFF();
1413 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1414 (uint32_t)(id >> 32), (uint32_t)id);
1415 }
1416
1417 // Clone Indala 64-bit tag by UID to T55x7
1418 void CopyIndala64toT55x7(int hi, int lo)
1419 {
1420
1421 //Program the 2 data blocks for supplied 64bit UID
1422 // and the block 0 for Indala64 format
1423 T55xxWriteBlock(hi,1,0,0);
1424 T55xxWriteBlock(lo,2,0,0);
1425 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1426 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1427 T55x7_MODULATION_PSK1 |
1428 2 << T55x7_MAXBLOCK_SHIFT,
1429 0, 0, 0);
1430 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1431 // T5567WriteBlock(0x603E1042,0);
1432
1433 DbpString("DONE!");
1434
1435 }
1436
1437 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1438 {
1439
1440 //Program the 7 data blocks for supplied 224bit UID
1441 // and the block 0 for Indala224 format
1442 T55xxWriteBlock(uid1,1,0,0);
1443 T55xxWriteBlock(uid2,2,0,0);
1444 T55xxWriteBlock(uid3,3,0,0);
1445 T55xxWriteBlock(uid4,4,0,0);
1446 T55xxWriteBlock(uid5,5,0,0);
1447 T55xxWriteBlock(uid6,6,0,0);
1448 T55xxWriteBlock(uid7,7,0,0);
1449 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1450 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1451 T55x7_MODULATION_PSK1 |
1452 7 << T55x7_MAXBLOCK_SHIFT,
1453 0,0,0);
1454 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1455 // T5567WriteBlock(0x603E10E2,0);
1456
1457 DbpString("DONE!");
1458
1459 }
1460
1461
1462 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1463 #define max(x,y) ( x<y ? y:x)
1464
1465 int DemodPCF7931(uint8_t **outBlocks) {
1466
1467 uint8_t BitStream[256] = {0x00};
1468 uint8_t Blocks[8][16] = [0x00};
1469 uint8_t *dest = BigBuf_get_addr();
1470 int GraphTraceLen = BigBuf_max_traceLen();
1471 int i, j, lastval, bitidx, half_switch;
1472 int clock = 64;
1473 int tolerance = clock / 8;
1474 int pmc, block_done;
1475 int lc, warnings = 0;
1476 int num_blocks = 0;
1477 int lmin=128, lmax=128;
1478 uint8_t dir;
1479
1480 LFSetupFPGAForADC(95, true);
1481 DoAcquisition_default(0, true);
1482
1483 lmin = 64;
1484 lmax = 192;
1485
1486 i = 2;
1487
1488 /* Find first local max/min */
1489 if(dest[1] > dest[0]) {
1490 while(i < GraphTraceLen) {
1491 if( !(dest[i] > dest[i-1]) && dest[i] > lmax)
1492 break;
1493 i++;
1494 }
1495 dir = 0;
1496 }
1497 else {
1498 while(i < GraphTraceLen) {
1499 if( !(dest[i] < dest[i-1]) && v[i] < lmin)
1500 break;
1501 i++;
1502 }
1503 dir = 1;
1504 }
1505
1506 lastval = i++;
1507 half_switch = 0;
1508 pmc = 0;
1509 block_done = 0;
1510
1511 for (bitidx = 0; i < GraphTraceLen; i++)
1512 {
1513 if ( (dest[i-1] > dest[i] && dir == 1 && dest[i] > lmax) || (dest[i-1] < dest[i] && dir == 0 && dest[i] < lmin))
1514 {
1515 lc = i - lastval;
1516 lastval = i;
1517
1518 // Switch depending on lc length:
1519 // Tolerance is 1/8 of clock rate (arbitrary)
1520 if (abs(lc-clock/4) < tolerance) {
1521 // 16T0
1522 if((i - pmc) == lc) { /* 16T0 was previous one */
1523 /* It's a PMC ! */
1524 i += (128+127+16+32+33+16)-1;
1525 lastval = i;
1526 pmc = 0;
1527 block_done = 1;
1528 }
1529 else {
1530 pmc = i;
1531 }
1532 } else if (abs(lc-clock/2) < tolerance) {
1533 // 32TO
1534 if((i - pmc) == lc) { /* 16T0 was previous one */
1535 /* It's a PMC ! */
1536 i += (128+127+16+32+33)-1;
1537 lastval = i;
1538 pmc = 0;
1539 block_done = 1;
1540 }
1541 else if(half_switch == 1) {
1542 BitStream[bitidx++] = 0;
1543 half_switch = 0;
1544 }
1545 else
1546 half_switch++;
1547 } else if (abs(lc-clock) < tolerance) {
1548 // 64TO
1549 BitStream[bitidx++] = 1;
1550 } else {
1551 // Error
1552 warnings++;
1553 if (warnings > 10)
1554 {
1555 Dbprintf("Error: too many detection errors, aborting.");
1556 return 0;
1557 }
1558 }
1559
1560 if(block_done == 1) {
1561 if(bitidx == 128) {
1562 for(j=0; j<16; j++) {
1563 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1564 64*BitStream[j*8+6]+
1565 32*BitStream[j*8+5]+
1566 16*BitStream[j*8+4]+
1567 8*BitStream[j*8+3]+
1568 4*BitStream[j*8+2]+
1569 2*BitStream[j*8+1]+
1570 BitStream[j*8];
1571 }
1572 num_blocks++;
1573 }
1574 bitidx = 0;
1575 block_done = 0;
1576 half_switch = 0;
1577 }
1578 if(i < GraphTraceLen)
1579 {
1580 if (dest[i-1] > dest[i]) dir=0;
1581 else dir = 1;
1582 }
1583 }
1584 if(bitidx==255)
1585 bitidx=0;
1586 warnings = 0;
1587 if(num_blocks == 4) break;
1588 }
1589 memcpy(outBlocks, Blocks, 16*num_blocks);
1590 return num_blocks;
1591 }
1592
1593 int IsBlock0PCF7931(uint8_t *Block) {
1594 // Assume RFU means 0 :)
1595 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1596 return 1;
1597 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1598 return 1;
1599 return 0;
1600 }
1601
1602 int IsBlock1PCF7931(uint8_t *Block) {
1603 // Assume RFU means 0 :)
1604 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1605 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1606 return 1;
1607
1608 return 0;
1609 }
1610
1611 #define ALLOC 16
1612
1613 void ReadPCF7931() {
1614 uint8_t Blocks[8][17];
1615 uint8_t tmpBlocks[4][16];
1616 int i, j, ind, ind2, n;
1617 int num_blocks = 0;
1618 int max_blocks = 8;
1619 int ident = 0;
1620 int error = 0;
1621 int tries = 0;
1622
1623 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1624
1625 do {
1626 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1627 n = DemodPCF7931((uint8_t**)tmpBlocks);
1628 if(!n)
1629 error++;
1630 if(error==10 && num_blocks == 0) {
1631 Dbprintf("Error, no tag or bad tag");
1632 return;
1633 }
1634 else if (tries==20 || error==10) {
1635 Dbprintf("Error reading the tag");
1636 Dbprintf("Here is the partial content");
1637 goto end;
1638 }
1639
1640 for(i=0; i<n; i++)
1641 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1642 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1643 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1644 if(!ident) {
1645 for(i=0; i<n; i++) {
1646 if(IsBlock0PCF7931(tmpBlocks[i])) {
1647 // Found block 0 ?
1648 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1649 // Found block 1!
1650 // \o/
1651 ident = 1;
1652 memcpy(Blocks[0], tmpBlocks[i], 16);
1653 Blocks[0][ALLOC] = 1;
1654 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1655 Blocks[1][ALLOC] = 1;
1656 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1657 // Debug print
1658 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1659 num_blocks = 2;
1660 // Handle following blocks
1661 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1662 if(j==n) j=0;
1663 if(j==i) break;
1664 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1665 Blocks[ind2][ALLOC] = 1;
1666 }
1667 break;
1668 }
1669 }
1670 }
1671 }
1672 else {
1673 for(i=0; i<n; i++) { // Look for identical block in known blocks
1674 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1675 for(j=0; j<max_blocks; j++) {
1676 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1677 // Found an identical block
1678 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1679 if(ind2 < 0)
1680 ind2 = max_blocks;
1681 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1682 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1683 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1684 Blocks[ind2][ALLOC] = 1;
1685 num_blocks++;
1686 if(num_blocks == max_blocks) goto end;
1687 }
1688 }
1689 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1690 if(ind2 > max_blocks)
1691 ind2 = 0;
1692 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1693 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1694 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1695 Blocks[ind2][ALLOC] = 1;
1696 num_blocks++;
1697 if(num_blocks == max_blocks) goto end;
1698 }
1699 }
1700 }
1701 }
1702 }
1703 }
1704 }
1705 tries++;
1706 if (BUTTON_PRESS()) return;
1707 } while (num_blocks != max_blocks);
1708 end:
1709 Dbprintf("-----------------------------------------");
1710 Dbprintf("Memory content:");
1711 Dbprintf("-----------------------------------------");
1712 for(i=0; i<max_blocks; i++) {
1713 if(Blocks[i][ALLOC]==1)
1714 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1715 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1716 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1717 else
1718 Dbprintf("<missing block %d>", i);
1719 }
1720 Dbprintf("-----------------------------------------");
1721
1722 return ;
1723 }
1724
1725
1726 //-----------------------------------
1727 // EM4469 / EM4305 routines
1728 //-----------------------------------
1729 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1730 #define FWD_CMD_WRITE 0xA
1731 #define FWD_CMD_READ 0x9
1732 #define FWD_CMD_DISABLE 0x5
1733
1734
1735 uint8_t forwardLink_data[64]; //array of forwarded bits
1736 uint8_t * forward_ptr; //ptr for forward message preparation
1737 uint8_t fwd_bit_sz; //forwardlink bit counter
1738 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1739
1740 //====================================================================
1741 // prepares command bits
1742 // see EM4469 spec
1743 //====================================================================
1744 //--------------------------------------------------------------------
1745 uint8_t Prepare_Cmd( uint8_t cmd ) {
1746 //--------------------------------------------------------------------
1747
1748 *forward_ptr++ = 0; //start bit
1749 *forward_ptr++ = 0; //second pause for 4050 code
1750
1751 *forward_ptr++ = cmd;
1752 cmd >>= 1;
1753 *forward_ptr++ = cmd;
1754 cmd >>= 1;
1755 *forward_ptr++ = cmd;
1756 cmd >>= 1;
1757 *forward_ptr++ = cmd;
1758
1759 return 6; //return number of emited bits
1760 }
1761
1762 //====================================================================
1763 // prepares address bits
1764 // see EM4469 spec
1765 //====================================================================
1766
1767 //--------------------------------------------------------------------
1768 uint8_t Prepare_Addr( uint8_t addr ) {
1769 //--------------------------------------------------------------------
1770
1771 register uint8_t line_parity;
1772
1773 uint8_t i;
1774 line_parity = 0;
1775 for(i=0;i<6;i++) {
1776 *forward_ptr++ = addr;
1777 line_parity ^= addr;
1778 addr >>= 1;
1779 }
1780
1781 *forward_ptr++ = (line_parity & 1);
1782
1783 return 7; //return number of emited bits
1784 }
1785
1786 //====================================================================
1787 // prepares data bits intreleaved with parity bits
1788 // see EM4469 spec
1789 //====================================================================
1790
1791 //--------------------------------------------------------------------
1792 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1793 //--------------------------------------------------------------------
1794
1795 register uint8_t line_parity;
1796 register uint8_t column_parity;
1797 register uint8_t i, j;
1798 register uint16_t data;
1799
1800 data = data_low;
1801 column_parity = 0;
1802
1803 for(i=0; i<4; i++) {
1804 line_parity = 0;
1805 for(j=0; j<8; j++) {
1806 line_parity ^= data;
1807 column_parity ^= (data & 1) << j;
1808 *forward_ptr++ = data;
1809 data >>= 1;
1810 }
1811 *forward_ptr++ = line_parity;
1812 if(i == 1)
1813 data = data_hi;
1814 }
1815
1816 for(j=0; j<8; j++) {
1817 *forward_ptr++ = column_parity;
1818 column_parity >>= 1;
1819 }
1820 *forward_ptr = 0;
1821
1822 return 45; //return number of emited bits
1823 }
1824
1825 //====================================================================
1826 // Forward Link send function
1827 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1828 // fwd_bit_count set with number of bits to be sent
1829 //====================================================================
1830 void SendForward(uint8_t fwd_bit_count) {
1831
1832 fwd_write_ptr = forwardLink_data;
1833 fwd_bit_sz = fwd_bit_count;
1834
1835 LED_D_ON();
1836
1837 //Field on
1838 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1839 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1840 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1841
1842 // Give it a bit of time for the resonant antenna to settle.
1843 // And for the tag to fully power up
1844 SpinDelay(150);
1845
1846 // force 1st mod pulse (start gap must be longer for 4305)
1847 fwd_bit_sz--; //prepare next bit modulation
1848 fwd_write_ptr++;
1849 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1850 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1851 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1852 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1853 SpinDelayUs(16*8); //16 cycles on (8us each)
1854
1855 // now start writting
1856 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1857 if(((*fwd_write_ptr++) & 1) == 1)
1858 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1859 else {
1860 //These timings work for 4469/4269/4305 (with the 55*8 above)
1861 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1862 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1863 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1864 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1865 SpinDelayUs(9*8); //16 cycles on (8us each)
1866 }
1867 }
1868 }
1869
1870 void EM4xLogin(uint32_t Password) {
1871
1872 uint8_t fwd_bit_count;
1873
1874 forward_ptr = forwardLink_data;
1875 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1876 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1877
1878 SendForward(fwd_bit_count);
1879
1880 //Wait for command to complete
1881 SpinDelay(20);
1882
1883 }
1884
1885 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1886
1887 uint8_t *dest = BigBuf_get_addr();
1888 uint16_t bufferlength = BigBuf_max_traceLen();
1889 uint32_t i = 0;
1890
1891 // Clear destination buffer before sending the command 0x80 = average.
1892 memset(dest, 0x80, bufferlength);
1893
1894 uint8_t fwd_bit_count;
1895
1896 //If password mode do login
1897 if (PwdMode == 1) EM4xLogin(Pwd);
1898
1899 forward_ptr = forwardLink_data;
1900 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1901 fwd_bit_count += Prepare_Addr( Address );
1902
1903 // Connect the A/D to the peak-detected low-frequency path.
1904 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1905 // Now set up the SSC to get the ADC samples that are now streaming at us.
1906 FpgaSetupSsc();
1907
1908 SendForward(fwd_bit_count);
1909
1910 // Now do the acquisition
1911 i = 0;
1912 for(;;) {
1913 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1914 AT91C_BASE_SSC->SSC_THR = 0x43;
1915 }
1916 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1917 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1918 ++i;
1919 if (i >= bufferlength) break;
1920 }
1921 }
1922
1923 cmd_send(CMD_ACK,0,0,0,0,0);
1924 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1925 LED_D_OFF();
1926 }
1927
1928 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1929
1930 uint8_t fwd_bit_count;
1931
1932 //If password mode do login
1933 if (PwdMode == 1) EM4xLogin(Pwd);
1934
1935 forward_ptr = forwardLink_data;
1936 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1937 fwd_bit_count += Prepare_Addr( Address );
1938 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1939
1940 SendForward(fwd_bit_count);
1941
1942 //Wait for write to complete
1943 SpinDelay(20);
1944 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1945 LED_D_OFF();
1946 }
Proxmark3 GIT tracking
Impressum, Datenschutz