Merge branch 'master' into fix_iclass_sim
[proxmark3-svn] / fpga / hi_simulate.v
1 //-----------------------------------------------------------------------------
2 // Pretend to be an ISO 14443 tag. We will do this by alternately short-
3 // circuiting and open-circuiting the antenna coil, with the tri-state
4 // pins.
5 //
6 // We communicate over the SSP, as a bitstream (i.e., might as well be
7 // unframed, though we still generate the word sync signal). The output
8 // (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
9 // -> ARM) is us using the A/D as a fancy comparator; this is with
10 // (software-added) hysteresis, to undo the high-pass filter.
11 //
12 // At this point only Type A is implemented. This means that we are using a
13 // bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
14 // things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
15 //
16 // Jonathan Westhues, October 2006
17 //-----------------------------------------------------------------------------
18
19 module hi_simulate(
20 ck_1356meg,
21 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
22 adc_d, adc_clk,
23 ssp_frame, ssp_din, ssp_dout, ssp_clk,
24 dbg,
25 mod_type
26 );
27 input ck_1356meg;
28 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
29 input [7:0] adc_d;
30 output adc_clk;
31 input ssp_dout;
32 output ssp_frame, ssp_din, ssp_clk;
33 output dbg;
34 input [2:0] mod_type;
35
36 assign adc_clk = ck_1356meg;
37
38 // The comparator with hysteresis on the output from the peak detector.
39 reg after_hysteresis;
40 reg [11:0] has_been_low_for;
41
42 always @(negedge adc_clk)
43 begin
44 if (& adc_d[7:5]) after_hysteresis <= 1'b1; // if (adc_d >= 224)
45 else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0; // if (adc_d <= 31)
46
47 if (adc_d >= 224)
48 begin
49 has_been_low_for <= 12'd0;
50 end
51 else
52 begin
53 if (has_been_low_for == 12'd4095)
54 begin
55 has_been_low_for <= 12'd0;
56 after_hysteresis <= 1'b1;
57 end
58 else
59 begin
60 has_been_low_for <= has_been_low_for + 1;
61 end
62 end
63 end
64
65
66 // Divide 13.56 MHz to produce various frequencies for SSP_CLK
67 // and modulation.
68 reg [8:0] ssp_clk_divider;
69
70 always @(negedge adc_clk)
71 ssp_clk_divider <= (ssp_clk_divider + 1);
72
73 reg ssp_clk;
74
75 always @(negedge adc_clk)
76 begin
77 if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
78 // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
79 ssp_clk <= ~ssp_clk_divider[7];
80 else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
81 // Get next bit at 212kHz
82 ssp_clk <= ~ssp_clk_divider[5];
83 else
84 // Get next bit at 424Khz
85 ssp_clk <= ~ssp_clk_divider[4];
86 end
87
88
89 // Produce the byte framing signal; the phase of this signal
90 // is arbitrary, because it's just a bit stream in this module.
91 reg ssp_frame;
92 always @(negedge adc_clk)
93 begin
94 if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
95 begin
96 if (ssp_clk_divider[8:5] == 4'd1)
97 ssp_frame <= 1'b1;
98 if (ssp_clk_divider[8:5] == 4'd5)
99 ssp_frame <= 1'b0;
100 end
101 else
102 begin
103 if (ssp_clk_divider[7:4] == 4'd1)
104 ssp_frame <= 1'b1;
105 if (ssp_clk_divider[7:4] == 4'd5)
106 ssp_frame <= 1'b0;
107 end
108 end
109
110
111 // Synchronize up the after-hysteresis signal, to produce DIN.
112 reg ssp_din;
113 always @(posedge ssp_clk)
114 ssp_din = after_hysteresis;
115
116 // Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
117 reg modulating_carrier;
118 always @(*)
119 if (mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
120 modulating_carrier <= 1'b0; // no modulation
121 else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
122 modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
123 else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
124 modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
125 else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
126 modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
127 else
128 modulating_carrier <= 1'b0; // yet unused
129
130
131 // Load modulation. Toggle only one of these, since we are already producing much deeper
132 // modulation than a real tag would.
133 assign pwr_hi = 1'b0; // HF antenna connected to GND
134 assign pwr_oe3 = 1'b0; // 10k Load
135 assign pwr_oe1 = modulating_carrier; // 33 Ohms Load
136 assign pwr_oe4 = modulating_carrier; // 33 Ohms Load
137
138 // This is all LF and doesn't matter
139 assign pwr_lo = 1'b0;
140 assign pwr_oe2 = 1'b0;
141
142
143 assign dbg = ssp_frame;
144
145 endmodule
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