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added: readed blocks (password mode) into tag.sectors[]. 'lf hitag sim' simulates...
[proxmark3-svn] / armsrc / hitag2.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Hitag2 emulation (preliminary test version)
7 //
8 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
9 //-----------------------------------------------------------------------------
10 // Hitag2 complete rewrite of the code
11 // - Fixed modulation/encoding issues
12 // - Rewrote code for transponder emulation
13 // - Added snooping of transponder communication
14 // - Added reader functionality
15 //
16 // (c) 2012 Roel Verdult
17 //-----------------------------------------------------------------------------
18
19 #include "proxmark3.h"
20 #include "apps.h"
21 #include "util.h"
22 #include "hitag2.h"
23 #include "string.h"
24
25 static bool bQuiet;
26
27 bool bCrypto;
28 bool bAuthenticating;
29 bool bPwd;
30
31 struct hitag2_tag {
32 uint32_t uid;
33 enum {
34 TAG_STATE_RESET = 0x01, // Just powered up, awaiting GetSnr
35 TAG_STATE_ACTIVATING = 0x02 , // In activation phase (password mode), sent UID, awaiting reader password
36 TAG_STATE_ACTIVATED = 0x03, // Activation complete, awaiting read/write commands
37 TAG_STATE_WRITING = 0x04, // In write command, awaiting sector contents to be written
38 } state;
39 unsigned int active_sector;
40 byte_t crypto_active;
41 uint64_t cs;
42 byte_t sectors[12][4];
43 };
44
45 static struct hitag2_tag tag = {
46 .state = TAG_STATE_RESET,
47 .sectors = { // Password mode: | Crypto mode:
48 [0] = { 0x02, 0x4e, 0x02, 0x20}, // UID | UID
49 [1] = { 0x4d, 0x49, 0x4b, 0x52}, // Password RWD | 32 bit LSB key
50 [2] = { 0x20, 0xf0, 0x4f, 0x4e}, // Reserved | 16 bit MSB key, 16 bit reserved
51 [3] = { 0x0e, 0xaa, 0x48, 0x54}, // Configuration, password TAG | Configuration, password TAG
52 [4] = { 0x46, 0x5f, 0x4f, 0x4b}, // Data: F_OK
53 [5] = { 0x55, 0x55, 0x55, 0x55}, // Data: UUUU
54 [6] = { 0xaa, 0xaa, 0xaa, 0xaa}, // Data: ....
55 [7] = { 0x55, 0x55, 0x55, 0x55}, // Data: UUUU
56 [8] = { 0x00, 0x00, 0x00, 0x00}, // RSK Low
57 [9] = { 0x00, 0x00, 0x00, 0x00}, // RSK High
58 [10] = { 0x00, 0x00, 0x00, 0x00}, // RCF
59 [11] = { 0x00, 0x00, 0x00, 0x00}, // SYNC
60 },
61 };
62
63 //#define TRACE_LENGTH 3000
64 //uint8_t *trace = (uint8_t *) BigBuf;
65 //int traceLen = 0;
66 //int rsamples = 0;
67
68 #define AUTH_TABLE_OFFSET FREE_BUFFER_OFFSET
69 #define AUTH_TABLE_LENGTH FREE_BUFFER_SIZE
70 byte_t* auth_table = (byte_t *)BigBuf+AUTH_TABLE_OFFSET;
71 size_t auth_table_pos = 0;
72 size_t auth_table_len = AUTH_TABLE_LENGTH;
73
74 byte_t password[4];
75 byte_t NrAr[8];
76 byte_t key[8];
77 uint64_t cipher_state;
78
79 /* Following is a modified version of cryptolib.com/ciphers/hitag2/ */
80 // Software optimized 48-bit Philips/NXP Mifare Hitag2 PCF7936/46/47/52 stream cipher algorithm by I.C. Wiener 2006-2007.
81 // For educational purposes only.
82 // No warranties or guarantees of any kind.
83 // This code is released into the public domain by its author.
84
85 // Basic macros:
86
87 #define u8 uint8_t
88 #define u32 uint32_t
89 #define u64 uint64_t
90 #define rev8(x) ((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7))
91 #define rev16(x) (rev8 (x)+(rev8 (x>> 8)<< 8))
92 #define rev32(x) (rev16(x)+(rev16(x>>16)<<16))
93 #define rev64(x) (rev32(x)+(rev32(x>>32)<<32))
94 #define bit(x,n) (((x)>>(n))&1)
95 #define bit32(x,n) ((((x)[(n)>>5])>>((n)))&1)
96 #define inv32(x,i,n) ((x)[(i)>>5]^=((u32)(n))<<((i)&31))
97 #define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))
98
99 // Single bit Hitag2 functions:
100
101 #define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))
102
103 static const u32 ht2_f4a = 0x2C79; // 0010 1100 0111 1001
104 static const u32 ht2_f4b = 0x6671; // 0110 0110 0111 0001
105 static const u32 ht2_f5c = 0x7907287B; // 0111 1001 0000 0111 0010 1000 0111 1011
106
107 static u32 _f20 (const u64 x)
108 {
109 u32 i5;
110
111 i5 = ((ht2_f4a >> i4 (x, 1, 2, 4, 5)) & 1)* 1
112 + ((ht2_f4b >> i4 (x, 7,11,13,14)) & 1)* 2
113 + ((ht2_f4b >> i4 (x,16,20,22,25)) & 1)* 4
114 + ((ht2_f4b >> i4 (x,27,28,30,32)) & 1)* 8
115 + ((ht2_f4a >> i4 (x,33,42,43,45)) & 1)*16;
116
117 return (ht2_f5c >> i5) & 1;
118 }
119
120 static u64 _hitag2_init (const u64 key, const u32 serial, const u32 IV)
121 {
122 u32 i;
123 u64 x = ((key & 0xFFFF) << 32) + serial;
124
125 for (i = 0; i < 32; i++)
126 {
127 x >>= 1;
128 x += (u64) (_f20 (x) ^ (((IV >> i) ^ (key >> (i+16))) & 1)) << 47;
129 }
130 return x;
131 }
132
133 static u64 _hitag2_round (u64 *state)
134 {
135 u64 x = *state;
136
137 x = (x >> 1) +
138 ((((x >> 0) ^ (x >> 2) ^ (x >> 3) ^ (x >> 6)
139 ^ (x >> 7) ^ (x >> 8) ^ (x >> 16) ^ (x >> 22)
140 ^ (x >> 23) ^ (x >> 26) ^ (x >> 30) ^ (x >> 41)
141 ^ (x >> 42) ^ (x >> 43) ^ (x >> 46) ^ (x >> 47)) & 1) << 47);
142
143 *state = x;
144 return _f20 (x);
145 }
146
147 static u32 _hitag2_byte (u64 * x)
148 {
149 u32 i, c;
150
151 for (i = 0, c = 0; i < 8; i++) c += (u32) _hitag2_round (x) << (i^7);
152 return c;
153 }
154
155 size_t nbytes(size_t nbits) {
156 return (nbits/8)+((nbits%8)>0);
157 }
158
159 int hitag2_reset(void)
160 {
161 tag.state = TAG_STATE_RESET;
162 tag.crypto_active = 0;
163 return 0;
164 }
165
166 int hitag2_init(void)
167 {
168 // memcpy(&tag, &resetdata, sizeof(tag));
169 hitag2_reset();
170 return 0;
171 }
172
173 static void hitag2_cipher_reset(struct hitag2_tag *tag, const byte_t *iv)
174 {
175 uint64_t key = ((uint64_t)tag->sectors[2][2]) |
176 ((uint64_t)tag->sectors[2][3] << 8) |
177 ((uint64_t)tag->sectors[1][0] << 16) |
178 ((uint64_t)tag->sectors[1][1] << 24) |
179 ((uint64_t)tag->sectors[1][2] << 32) |
180 ((uint64_t)tag->sectors[1][3] << 40);
181 uint32_t uid = ((uint32_t)tag->sectors[0][0]) |
182 ((uint32_t)tag->sectors[0][1] << 8) |
183 ((uint32_t)tag->sectors[0][2] << 16) |
184 ((uint32_t)tag->sectors[0][3] << 24);
185 uint32_t iv_ = (((uint32_t)(iv[0]))) |
186 (((uint32_t)(iv[1])) << 8) |
187 (((uint32_t)(iv[2])) << 16) |
188 (((uint32_t)(iv[3])) << 24);
189 tag->cs = _hitag2_init(rev64(key), rev32(uid), rev32(iv_));
190 }
191
192 static int hitag2_cipher_authenticate(uint64_t* cs, const byte_t *authenticator_is)
193 {
194 byte_t authenticator_should[4];
195 authenticator_should[0] = ~_hitag2_byte(cs);
196 authenticator_should[1] = ~_hitag2_byte(cs);
197 authenticator_should[2] = ~_hitag2_byte(cs);
198 authenticator_should[3] = ~_hitag2_byte(cs);
199 return (memcmp(authenticator_should, authenticator_is, 4) == 0);
200 }
201
202 static int hitag2_cipher_transcrypt(uint64_t* cs, byte_t *data, unsigned int bytes, unsigned int bits)
203 {
204 int i;
205 for(i=0; i<bytes; i++) data[i] ^= _hitag2_byte(cs);
206 for(i=0; i<bits; i++) data[bytes] ^= _hitag2_round(cs) << (7-i);
207 return 0;
208 }
209
210 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
211 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
212 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
213 // T0 = TIMER_CLOCK1 / 125000 = 192
214 #define T0 192
215
216 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
217 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
218
219 #define HITAG_FRAME_LEN 20
220 #define HITAG_T_STOP 36 /* T_EOF should be > 36 */
221 #define HITAG_T_LOW 8 /* T_LOW should be 4..10 */
222 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
223 #define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */
224 //#define HITAG_T_EOF 40 /* T_EOF should be > 36 */
225 #define HITAG_T_EOF 80 /* T_EOF should be > 36 */
226 #define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */
227 #define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */
228 #define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */
229
230 #define HITAG_T_TAG_ONE_HALF_PERIOD 10
231 #define HITAG_T_TAG_TWO_HALF_PERIOD 25
232 #define HITAG_T_TAG_THREE_HALF_PERIOD 41
233 #define HITAG_T_TAG_FOUR_HALF_PERIOD 57
234
235 #define HITAG_T_TAG_HALF_PERIOD 16
236 #define HITAG_T_TAG_FULL_PERIOD 32
237
238 #define HITAG_T_TAG_CAPTURE_ONE_HALF 13
239 #define HITAG_T_TAG_CAPTURE_TWO_HALF 25
240 #define HITAG_T_TAG_CAPTURE_THREE_HALF 41
241 #define HITAG_T_TAG_CAPTURE_FOUR_HALF 57
242
243
244 static void hitag_send_bit(int bit) {
245 LED_A_ON();
246 // Reset clock for the next bit
247 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
248
249 // Fixed modulation, earlier proxmark version used inverted signal
250 if(bit == 0) {
251 // Manchester: Unloaded, then loaded |__--|
252 LOW(GPIO_SSC_DOUT);
253 while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_HALF_PERIOD);
254 HIGH(GPIO_SSC_DOUT);
255 while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_FULL_PERIOD);
256 } else {
257 // Manchester: Loaded, then unloaded |--__|
258 HIGH(GPIO_SSC_DOUT);
259 while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_HALF_PERIOD);
260 LOW(GPIO_SSC_DOUT);
261 while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_FULL_PERIOD);
262 }
263 LED_A_OFF();
264 }
265
266 static void hitag_send_frame(const byte_t* frame, size_t frame_len)
267 {
268 // Send start of frame
269 for(size_t i=0; i<5; i++) {
270 hitag_send_bit(1);
271 }
272
273 // Send the content of the frame
274 for(size_t i=0; i<frame_len; i++) {
275 hitag_send_bit((frame[i/8] >> (7-(i%8)))&1);
276 }
277
278 // Drop the modulation
279 LOW(GPIO_SSC_DOUT);
280 }
281
282 void hitag2_handle_reader_command(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen)
283 {
284 byte_t rx_air[HITAG_FRAME_LEN];
285
286 // Copy the (original) received frame how it is send over the air
287 memcpy(rx_air,rx,nbytes(rxlen));
288
289 if(tag.crypto_active) {
290 hitag2_cipher_transcrypt(&(tag.cs),rx,rxlen/8,rxlen%8);
291 }
292
293 // Reset the transmission frame length
294 *txlen = 0;
295
296 // Try to find out which command was send by selecting on length (in bits)
297 switch (rxlen) {
298 // Received 11000 from the reader, request for UID, send UID
299 case 05: {
300 // Always send over the air in the clear plaintext mode
301 if(rx_air[0] != 0xC0) {
302 // Unknown frame ?
303 return;
304 }
305 *txlen = 32;
306 memcpy(tx,tag.sectors[0],4);
307 tag.crypto_active = 0;
308 }
309 break;
310
311 // Read/Write command: ..xx x..y yy with yyy == ~xxx, xxx is sector number
312 case 10: {
313 unsigned int sector = (~( ((rx[0]<<2)&0x04) | ((rx[1]>>6)&0x03) ) & 0x07);
314 // Verify complement of sector index
315 if(sector != ((rx[0]>>3)&0x07)) {
316 //DbpString("Transmission error (read/write)");
317 return;
318 }
319
320 switch (rx[0] & 0xC6) {
321 // Read command: 11xx x00y
322 case 0xC0:
323 memcpy(tx,tag.sectors[sector],4);
324 *txlen = 32;
325 break;
326
327 // Inverted Read command: 01xx x10y
328 case 0x44:
329 for (size_t i=0; i<4; i++) {
330 tx[i] = tag.sectors[sector][i] ^ 0xff;
331 }
332 *txlen = 32;
333 break;
334
335 // Write command: 10xx x01y
336 case 0x82:
337 // Prepare write, acknowledge by repeating command
338 memcpy(tx,rx,nbytes(rxlen));
339 *txlen = rxlen;
340 tag.active_sector = sector;
341 tag.state=TAG_STATE_WRITING;
342 break;
343
344 // Unknown command
345 default:
346 Dbprintf("Uknown command: %02x %02x",rx[0],rx[1]);
347 return;
348 break;
349 }
350 }
351 break;
352
353 // Writing data or Reader password
354 case 32: {
355 if(tag.state == TAG_STATE_WRITING) {
356 // These are the sector contents to be written. We don't have to do anything else.
357 memcpy(tag.sectors[tag.active_sector],rx,nbytes(rxlen));
358 tag.state=TAG_STATE_RESET;
359 return;
360 } else {
361 // Received RWD password, respond with configuration and our password
362 if(memcmp(rx,tag.sectors[1],4) != 0) {
363 DbpString("Reader password is wrong");
364 return;
365 }
366 *txlen = 32;
367 memcpy(tx,tag.sectors[3],4);
368 }
369 }
370 break;
371
372 // Received RWD authentication challenge and respnse
373 case 64: {
374 // Store the authentication attempt
375 if (auth_table_len < (AUTH_TABLE_LENGTH-8)) {
376 memcpy(auth_table+auth_table_len,rx,8);
377 auth_table_len += 8;
378 }
379
380 // Reset the cipher state
381 hitag2_cipher_reset(&tag,rx);
382 // Check if the authentication was correct
383 if(!hitag2_cipher_authenticate(&(tag.cs),rx+4)) {
384 // The reader failed to authenticate, do nothing
385 Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x Failed!",rx[0],rx[1],rx[2],rx[3],rx[4],rx[5],rx[6],rx[7]);
386 return;
387 }
388 // Succesful, but commented out reporting back to the Host, this may delay to much.
389 // Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x OK!",rx[0],rx[1],rx[2],rx[3],rx[4],rx[5],rx[6],rx[7]);
390
391 // Activate encryption algorithm for all further communication
392 tag.crypto_active = 1;
393
394 // Use the tag password as response
395 memcpy(tx,tag.sectors[3],4);
396 *txlen = 32;
397 }
398 break;
399 }
400
401 // LogTrace(rx,nbytes(rxlen),0,0,false);
402 // LogTrace(tx,nbytes(*txlen),0,0,true);
403
404 if(tag.crypto_active) {
405 hitag2_cipher_transcrypt(&(tag.cs), tx, *txlen/8, *txlen%8);
406 }
407 }
408
409 static void hitag_reader_send_bit(int bit) {
410 LED_A_ON();
411 // Reset clock for the next bit
412 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
413
414 // Binary puls length modulation (BPLM) is used to encode the data stream
415 // This means that a transmission of a one takes longer than that of a zero
416
417 // Enable modulation, which means, drop the the field
418 HIGH(GPIO_SSC_DOUT);
419
420 // Wait for 4-10 times the carrier period
421 while(AT91C_BASE_TC0->TC_CV < T0*6);
422 // SpinDelayUs(8*8);
423
424 // Disable modulation, just activates the field again
425 LOW(GPIO_SSC_DOUT);
426
427 if(bit == 0) {
428 // Zero bit: |_-|
429 while(AT91C_BASE_TC0->TC_CV < T0*22);
430 // SpinDelayUs(16*8);
431 } else {
432 // One bit: |_--|
433 while(AT91C_BASE_TC0->TC_CV < T0*28);
434 // SpinDelayUs(22*8);
435 }
436 LED_A_OFF();
437 }
438
439 static void hitag_reader_send_frame(const byte_t* frame, size_t frame_len)
440 {
441 // Send the content of the frame
442 for(size_t i=0; i<frame_len; i++) {
443 hitag_reader_send_bit((frame[i/8] >> (7-(i%8)))&1);
444 }
445 // Send EOF
446 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
447 // Enable modulation, which means, drop the the field
448 HIGH(GPIO_SSC_DOUT);
449 // Wait for 4-10 times the carrier period
450 while(AT91C_BASE_TC0->TC_CV < T0*6);
451 // Disable modulation, just activates the field again
452 LOW(GPIO_SSC_DOUT);
453 }
454
455 size_t blocknr;
456
457 bool hitag2_password(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {
458 // Reset the transmission frame length
459 *txlen = 0;
460
461 // Try to find out which command was send by selecting on length (in bits)
462 switch (rxlen) {
463 // No answer, try to resurrect
464 case 0: {
465 // Stop if there is no answer (after sending password)
466 if (bPwd) {
467 DbpString("Password failed!");
468 return false;
469 }
470 *txlen = 5;
471 memcpy(tx,"\xc0",nbytes(*txlen));
472 } break;
473
474 // Received UID, tag password
475 case 32: {
476 if (!bPwd) {
477 *txlen = 32;
478 memcpy(tx,password,4);
479 bPwd = true;
480 memcpy(tag.sectors[blocknr],rx,4);
481 blocknr++;
482 } else {
483
484 if(blocknr == 1){
485 //store password in block1, the TAG answers with Block3, but we need the password in memory
486 memcpy(tag.sectors[blocknr],tx,4);
487 }else{
488 memcpy(tag.sectors[blocknr],rx,4);
489 }
490
491 blocknr++;
492 if (blocknr > 7) {
493 DbpString("Read succesful!");
494 // We are done... for now
495 return false;
496 }
497 *txlen = 10;
498 tx[0] = 0xc0 | (blocknr << 3) | ((blocknr^7) >> 2);
499 tx[1] = ((blocknr^7) << 6);
500 }
501 } break;
502
503 // Unexpected response
504 default: {
505 Dbprintf("Uknown frame length: %d",rxlen);
506 return false;
507 } break;
508 }
509 return true;
510 }
511
512 bool hitag2_crypto(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {
513 // Reset the transmission frame length
514 *txlen = 0;
515
516 if(bCrypto) {
517 hitag2_cipher_transcrypt(&cipher_state,rx,rxlen/8,rxlen%8);
518 }
519
520 // Try to find out which command was send by selecting on length (in bits)
521 switch (rxlen) {
522 // No answer, try to resurrect
523 case 0: {
524 // Stop if there is no answer while we are in crypto mode (after sending NrAr)
525 if (bCrypto) {
526 DbpString("Authentication failed!");
527 return false;
528 }
529 *txlen = 5;
530 memcpy(tx,"\xc0",nbytes(*txlen));
531 } break;
532
533 // Received UID, crypto tag answer
534 case 32: {
535 if (!bCrypto) {
536 uint64_t ui64key = key[0] | ((uint64_t)key[1]) << 8 | ((uint64_t)key[2]) << 16 | ((uint64_t)key[3]) << 24 | ((uint64_t)key[4]) << 32 | ((uint64_t)key[5]) << 40;
537 uint32_t ui32uid = rx[0] | ((uint32_t)rx[1]) << 8 | ((uint32_t)rx[2]) << 16 | ((uint32_t)rx[3]) << 24;
538 cipher_state = _hitag2_init(rev64(ui64key), rev32(ui32uid), 0);
539 memset(tx,0x00,4);
540 memset(tx+4,0xff,4);
541 hitag2_cipher_transcrypt(&cipher_state,tx+4,4,0);
542 *txlen = 64;
543 bCrypto = true;
544 bAuthenticating = true;
545 } else {
546 // Check if we received answer tag (at)
547 if (bAuthenticating) {
548 bAuthenticating = false;
549 } else {
550 // Store the received block
551 memcpy(tag.sectors[blocknr],rx,4);
552 blocknr++;
553 }
554 if (blocknr > 7) {
555 DbpString("Read succesful!");
556 // We are done... for now
557 return false;
558 }
559 *txlen = 10;
560 tx[0] = 0xc0 | (blocknr << 3) | ((blocknr^7) >> 2);
561 tx[1] = ((blocknr^7) << 6);
562 }
563 } break;
564
565 // Unexpected response
566 default: {
567 Dbprintf("Uknown frame length: %d",rxlen);
568 return false;
569 } break;
570 }
571
572
573 if(bCrypto) {
574 // We have to return now to avoid double encryption
575 if (!bAuthenticating) {
576 hitag2_cipher_transcrypt(&cipher_state,tx,*txlen/8,*txlen%8);
577 }
578 }
579
580 return true;
581 }
582
583
584 bool hitag2_authenticate(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {
585 // Reset the transmission frame length
586 *txlen = 0;
587
588 // Try to find out which command was send by selecting on length (in bits)
589 switch (rxlen) {
590 // No answer, try to resurrect
591 case 0: {
592 // Stop if there is no answer while we are in crypto mode (after sending NrAr)
593 if (bCrypto) {
594 DbpString("Authentication failed!");
595 return false;
596 }
597 *txlen = 5;
598 memcpy(tx,"\xc0",nbytes(*txlen));
599 } break;
600
601 // Received UID, crypto tag answer
602 case 32: {
603 if (!bCrypto) {
604 *txlen = 64;
605 memcpy(tx,NrAr,8);
606 bCrypto = true;
607 } else {
608 DbpString("Authentication succesful!");
609 // We are done... for now
610 return false;
611 }
612 } break;
613
614 // Unexpected response
615 default: {
616 Dbprintf("Uknown frame length: %d",rxlen);
617 return false;
618 } break;
619 }
620
621 return true;
622 }
623
624 bool hitag2_test_auth_attempts(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {
625 // Reset the transmission frame length
626 *txlen = 0;
627
628 // Try to find out which command was send by selecting on length (in bits)
629 switch (rxlen) {
630 // No answer, try to resurrect
631 case 0: {
632 // Stop if there is no answer while we are in crypto mode (after sending NrAr)
633 if (bCrypto) {
634 Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x Failed!",NrAr[0],NrAr[1],NrAr[2],NrAr[3],NrAr[4],NrAr[5],NrAr[6],NrAr[7]);
635 bCrypto = false;
636 if ((auth_table_pos+8) == auth_table_len) {
637 return false;
638 }
639 auth_table_pos += 8;
640 memcpy(NrAr,auth_table+auth_table_pos,8);
641 }
642 *txlen = 5;
643 memcpy(tx,"\xc0",nbytes(*txlen));
644 } break;
645
646 // Received UID, crypto tag answer, or read block response
647 case 32: {
648 if (!bCrypto) {
649 *txlen = 64;
650 memcpy(tx,NrAr,8);
651 bCrypto = true;
652 } else {
653 Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x OK",NrAr[0],NrAr[1],NrAr[2],NrAr[3],NrAr[4],NrAr[5],NrAr[6],NrAr[7]);
654 bCrypto = false;
655 if ((auth_table_pos+8) == auth_table_len) {
656 return false;
657 }
658 auth_table_pos += 8;
659 memcpy(NrAr,auth_table+auth_table_pos,8);
660 }
661 } break;
662
663 default: {
664 Dbprintf("Uknown frame length: %d",rxlen);
665 return false;
666 } break;
667 }
668
669 return true;
670 }
671
672 void SnoopHitag(uint32_t type) {
673 int frame_count;
674 int response;
675 int overflow;
676 bool rising_edge;
677 bool reader_frame;
678 int lastbit;
679 bool bSkip;
680 int tag_sof;
681 byte_t rx[HITAG_FRAME_LEN];
682 size_t rxlen=0;
683
684 // Clean up trace and prepare it for storing frames
685 iso14a_set_tracing(TRUE);
686 iso14a_clear_trace();
687
688 auth_table_len = 0;
689 auth_table_pos = 0;
690 memset(auth_table, 0x00, AUTH_TABLE_LENGTH);
691
692 DbpString("Starting Hitag2 snoop");
693 LED_D_ON();
694
695 // Set up eavesdropping mode, frequency divisor which will drive the FPGA
696 // and analog mux selection.
697 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
698 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
699 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
700 RELAY_OFF();
701
702 // Configure output pin that is connected to the FPGA (for modulating)
703 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
704 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
705
706 // Disable modulation, we are going to eavesdrop, not modulate ;)
707 LOW(GPIO_SSC_DOUT);
708
709 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
710 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
711 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
712
713 // Disable timer during configuration
714 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
715
716 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
717 // external trigger rising edge, load RA on rising edge of TIOA.
718 uint32_t t1_channel_mode = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_BOTH | AT91C_TC_ABETRG | AT91C_TC_LDRA_BOTH;
719 AT91C_BASE_TC1->TC_CMR = t1_channel_mode;
720
721 // Enable and reset counter
722 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
723
724 // Reset the received frame, frame count and timing info
725 memset(rx,0x00,sizeof(rx));
726 frame_count = 0;
727 response = 0;
728 overflow = 0;
729 reader_frame = false;
730 lastbit = 1;
731 bSkip = true;
732 tag_sof = 4;
733
734 while(!BUTTON_PRESS()) {
735 // Watchdog hit
736 WDT_HIT();
737
738 // Receive frame, watch for at most T0*EOF periods
739 while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_EOF) {
740 // Check if rising edge in modulation is detected
741 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
742 // Retrieve the new timing values
743 int ra = (AT91C_BASE_TC1->TC_RA/T0);
744
745 // Find out if we are dealing with a rising or falling edge
746 rising_edge = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME) > 0;
747
748 // Shorter periods will only happen with reader frames
749 if (!reader_frame && rising_edge && ra < HITAG_T_TAG_CAPTURE_ONE_HALF) {
750 // Switch from tag to reader capture
751 LED_C_OFF();
752 reader_frame = true;
753 memset(rx,0x00,sizeof(rx));
754 rxlen = 0;
755 }
756
757 // Only handle if reader frame and rising edge, or tag frame and falling edge
758 if (reader_frame != rising_edge) {
759 overflow += ra;
760 continue;
761 }
762
763 // Add the buffered timing values of earlier captured edges which were skipped
764 ra += overflow;
765 overflow = 0;
766
767 if (reader_frame) {
768 LED_B_ON();
769 // Capture reader frame
770 if(ra >= HITAG_T_STOP) {
771 if (rxlen != 0) {
772 //DbpString("wierd0?");
773 }
774 // Capture the T0 periods that have passed since last communication or field drop (reset)
775 response = (ra - HITAG_T_LOW);
776 } else if(ra >= HITAG_T_1_MIN ) {
777 // '1' bit
778 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
779 rxlen++;
780 } else if(ra >= HITAG_T_0_MIN) {
781 // '0' bit
782 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
783 rxlen++;
784 } else {
785 // Ignore wierd value, is to small to mean anything
786 }
787 } else {
788 LED_C_ON();
789 // Capture tag frame (manchester decoding using only falling edges)
790 if(ra >= HITAG_T_EOF) {
791 if (rxlen != 0) {
792 //DbpString("wierd1?");
793 }
794 // Capture the T0 periods that have passed since last communication or field drop (reset)
795 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
796 response = ra-HITAG_T_TAG_HALF_PERIOD;
797 } else if(ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
798 // Manchester coding example |-_|_-|-_| (101)
799 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
800 rxlen++;
801 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
802 rxlen++;
803 } else if(ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
804 // Manchester coding example |_-|...|_-|-_| (0...01)
805 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
806 rxlen++;
807 // We have to skip this half period at start and add the 'one' the second time
808 if (!bSkip) {
809 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
810 rxlen++;
811 }
812 lastbit = !lastbit;
813 bSkip = !bSkip;
814 } else if(ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
815 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
816 if (tag_sof) {
817 // Ignore bits that are transmitted during SOF
818 tag_sof--;
819 } else {
820 // bit is same as last bit
821 rx[rxlen / 8] |= lastbit << (7-(rxlen%8));
822 rxlen++;
823 }
824 } else {
825 // Ignore wierd value, is to small to mean anything
826 }
827 }
828 }
829 }
830
831 // Check if frame was captured
832 if(rxlen > 0) {
833 frame_count++;
834 if (!LogTrace(rx,nbytes(rxlen),response,0,reader_frame)) {
835 DbpString("Trace full");
836 break;
837 }
838
839 // Check if we recognize a valid authentication attempt
840 if (nbytes(rxlen) == 8) {
841 // Store the authentication attempt
842 if (auth_table_len < (AUTH_TABLE_LENGTH-8)) {
843 memcpy(auth_table+auth_table_len,rx,8);
844 auth_table_len += 8;
845 }
846 }
847
848 // Reset the received frame and response timing info
849 memset(rx,0x00,sizeof(rx));
850 response = 0;
851 reader_frame = false;
852 lastbit = 1;
853 bSkip = true;
854 tag_sof = 4;
855 overflow = 0;
856
857 LED_B_OFF();
858 LED_C_OFF();
859 } else {
860 // Save the timer overflow, will be 0 when frame was received
861 overflow += (AT91C_BASE_TC1->TC_CV/T0);
862 }
863 // Reset the frame length
864 rxlen = 0;
865 // Reset the timer to restart while-loop that receives frames
866 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
867 }
868 LED_A_ON();
869 LED_B_OFF();
870 LED_C_OFF();
871 LED_D_OFF();
872 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
873 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
874 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
875 LED_A_OFF();
876
877 // Dbprintf("frame received: %d",frame_count);
878 // Dbprintf("Authentication Attempts: %d",(auth_table_len/8));
879 // DbpString("All done");
880 }
881
882 void SimulateHitagTag(bool tag_mem_supplied, byte_t* data) {
883 int frame_count;
884 int response;
885 int overflow;
886 byte_t rx[HITAG_FRAME_LEN];
887 size_t rxlen=0;
888 byte_t tx[HITAG_FRAME_LEN];
889 size_t txlen=0;
890 bool bQuitTraceFull = false;
891 bQuiet = false;
892
893 // Clean up trace and prepare it for storing frames
894 iso14a_set_tracing(TRUE);
895 iso14a_clear_trace();
896 auth_table_len = 0;
897 auth_table_pos = 0;
898 memset(auth_table, 0x00, AUTH_TABLE_LENGTH);
899
900 DbpString("Starting Hitag2 simulation");
901 LED_D_ON();
902 hitag2_init();
903
904 if (tag_mem_supplied) {
905 DbpString("Loading hitag2 memory...");
906 memcpy((byte_t*)tag.sectors,data,48);
907 }
908
909 uint32_t block = 0;
910 for (size_t i=0; i<12; i++) {
911 for (size_t j=0; j<4; j++) {
912 block <<= 8;
913 block |= tag.sectors[i][j];
914 }
915 Dbprintf("| %d | %08x |",i,block);
916 }
917
918 // Set up simulator mode, frequency divisor which will drive the FPGA
919 // and analog mux selection.
920 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
921 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
922 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
923 RELAY_OFF();
924
925 // Configure output pin that is connected to the FPGA (for modulating)
926 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
927 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
928
929 // Disable modulation at default, which means release resistance
930 LOW(GPIO_SSC_DOUT);
931
932 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
933 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
934
935 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
936 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
937 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
938
939 // Disable timer during configuration
940 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
941
942 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
943 // external trigger rising edge, load RA on rising edge of TIOA.
944 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
945
946 // Enable and reset counter
947 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
948
949 // Reset the received frame, frame count and timing info
950 memset(rx,0x00,sizeof(rx));
951 frame_count = 0;
952 response = 0;
953 overflow = 0;
954
955 while(!BUTTON_PRESS()) {
956 // Watchdog hit
957 WDT_HIT();
958
959 // Receive frame, watch for at most T0*EOF periods
960 while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_EOF) {
961 // Check if rising edge in modulation is detected
962 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
963 // Retrieve the new timing values
964 int ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow;
965 overflow = 0;
966
967 // Reset timer every frame, we have to capture the last edge for timing
968 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
969
970 LED_B_ON();
971
972 // Capture reader frame
973 if(ra >= HITAG_T_STOP) {
974 if (rxlen != 0) {
975 //DbpString("wierd0?");
976 }
977 // Capture the T0 periods that have passed since last communication or field drop (reset)
978 response = (ra - HITAG_T_LOW);
979 } else if(ra >= HITAG_T_1_MIN ) {
980 // '1' bit
981 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
982 rxlen++;
983 } else if(ra >= HITAG_T_0_MIN) {
984 // '0' bit
985 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
986 rxlen++;
987 } else {
988 // Ignore wierd value, is to small to mean anything
989 }
990 }
991 }
992
993 // Check if frame was captured
994 if(rxlen > 4) {
995 frame_count++;
996 if (!bQuiet) {
997 if (!LogTrace(rx,nbytes(rxlen),response,0,true)) {
998 DbpString("Trace full");
999 if (bQuitTraceFull) {
1000 break;
1001 } else {
1002 bQuiet = true;
1003 }
1004 }
1005 }
1006
1007 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1008 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1009
1010 // Process the incoming frame (rx) and prepare the outgoing frame (tx)
1011 hitag2_handle_reader_command(rx,rxlen,tx,&txlen);
1012
1013 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
1014 // not that since the clock counts since the rising edge, but T_Wait1 is
1015 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
1016 // periods. The gap time T_Low varies (4..10). All timer values are in
1017 // terms of T0 units
1018 while(AT91C_BASE_TC0->TC_CV < T0*(HITAG_T_WAIT_1-HITAG_T_LOW));
1019
1020 // Send and store the tag answer (if there is any)
1021 if (txlen) {
1022 // Transmit the tag frame
1023 hitag_send_frame(tx,txlen);
1024 // Store the frame in the trace
1025 if (!bQuiet) {
1026 if (!LogTrace(tx,nbytes(txlen),0,0,false)) {
1027 DbpString("Trace full");
1028 if (bQuitTraceFull) {
1029 break;
1030 } else {
1031 bQuiet = true;
1032 }
1033 }
1034 }
1035 }
1036
1037 // Reset the received frame and response timing info
1038 memset(rx,0x00,sizeof(rx));
1039 response = 0;
1040
1041 // Enable and reset external trigger in timer for capturing future frames
1042 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1043 LED_B_OFF();
1044 }
1045 // Reset the frame length
1046 rxlen = 0;
1047 // Save the timer overflow, will be 0 when frame was received
1048 overflow += (AT91C_BASE_TC1->TC_CV/T0);
1049 // Reset the timer to restart while-loop that receives frames
1050 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
1051 }
1052 LED_B_OFF();
1053 LED_D_OFF();
1054 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1055 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1056 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1057 // Dbprintf("frame received: %d",frame_count);
1058 // Dbprintf("Authentication Attempts: %d",(auth_table_len/8));
1059 // DbpString("All done");
1060 }
1061
1062 void ReaderHitag(hitag_function htf, hitag_data* htd) {
1063 int frame_count;
1064 int response;
1065 byte_t rx[HITAG_FRAME_LEN];
1066 size_t rxlen=0;
1067 byte_t txbuf[HITAG_FRAME_LEN];
1068 byte_t* tx = txbuf;
1069 size_t txlen=0;
1070 int lastbit;
1071 bool bSkip;
1072 int reset_sof;
1073 int tag_sof;
1074 int t_wait = HITAG_T_WAIT_MAX;
1075 bool bStop;
1076 bool bQuitTraceFull = false;
1077
1078 // Clean up trace and prepare it for storing frames
1079 iso14a_set_tracing(TRUE);
1080 iso14a_clear_trace();
1081 DbpString("Starting Hitag reader family");
1082
1083 // Check configuration
1084 switch(htf) {
1085 case RHT2F_PASSWORD: {
1086 Dbprintf("List identifier in password mode");
1087 memcpy(password,htd->pwd.password,4);
1088 blocknr = 0;
1089 bQuitTraceFull = false;
1090 bQuiet = false;
1091 bPwd = false;
1092 } break;
1093
1094 case RHT2F_AUTHENTICATE: {
1095 DbpString("Authenticating using nr,ar pair:");
1096 memcpy(NrAr,htd->auth.NrAr,8);
1097 Dbhexdump(8,NrAr,false);
1098 bQuiet = false;
1099 bCrypto = false;
1100 bAuthenticating = false;
1101 bQuitTraceFull = true;
1102 } break;
1103
1104 case RHT2F_CRYPTO: {
1105 DbpString("Authenticating using key:");
1106 memcpy(key,htd->crypto.key,6);
1107 Dbhexdump(6,key,false);
1108 blocknr = 0;
1109 bQuiet = false;
1110 bCrypto = false;
1111 bAuthenticating = false;
1112 bQuitTraceFull = true;
1113 } break;
1114
1115 case RHT2F_TEST_AUTH_ATTEMPTS: {
1116 Dbprintf("Testing %d authentication attempts",(auth_table_len/8));
1117 auth_table_pos = 0;
1118 memcpy(NrAr,auth_table,8);
1119 bQuitTraceFull = false;
1120 bQuiet = false;
1121 bCrypto = false;
1122 } break;
1123
1124 default: {
1125 Dbprintf("Error, unknown function: %d",htf);
1126 return;
1127 } break;
1128 }
1129
1130 LED_D_ON();
1131 hitag2_init();
1132
1133 // Configure output and enable pin that is connected to the FPGA (for modulating)
1134 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1135 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1136
1137 // Set fpga in edge detect with reader field, we can modulate as reader now
1138 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1139
1140 // Set Frequency divisor which will drive the FPGA and analog mux selection
1141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1142 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1143 RELAY_OFF();
1144
1145 // Disable modulation at default, which means enable the field
1146 LOW(GPIO_SSC_DOUT);
1147
1148 // Give it a bit of time for the resonant antenna to settle.
1149 SpinDelay(30);
1150
1151 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1152 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1153
1154 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1155 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1156 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1157
1158 // Disable timer during configuration
1159 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1160
1161 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1162 // external trigger rising edge, load RA on falling edge of TIOA.
1163 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
1164
1165 // Enable and reset counters
1166 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1167 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1168
1169 // Reset the received frame, frame count and timing info
1170 frame_count = 0;
1171 response = 0;
1172 lastbit = 1;
1173 bStop = false;
1174
1175 // Tag specific configuration settings (sof, timings, etc.)
1176 if (htf < 10){
1177 // hitagS settings
1178 reset_sof = 1;
1179 t_wait = 200;
1180 DbpString("Configured for hitagS reader");
1181 } else if (htf < 20) {
1182 // hitag1 settings
1183 reset_sof = 1;
1184 t_wait = 200;
1185 DbpString("Configured for hitag1 reader");
1186 } else if (htf < 30) {
1187 // hitag2 settings
1188 reset_sof = 4;
1189 t_wait = HITAG_T_WAIT_2;
1190 DbpString("Configured for hitag2 reader");
1191 } else {
1192 Dbprintf("Error, unknown hitag reader type: %d",htf);
1193 return;
1194 }
1195
1196 while(!bStop && !BUTTON_PRESS()) {
1197 // Watchdog hit
1198 WDT_HIT();
1199
1200 // Check if frame was captured and store it
1201 if(rxlen > 0) {
1202 frame_count++;
1203 if (!bQuiet) {
1204 if (!LogTrace(rx,nbytes(rxlen),response,0,false)) {
1205 DbpString("Trace full");
1206 if (bQuitTraceFull) {
1207 break;
1208 } else {
1209 bQuiet = true;
1210 }
1211 }
1212 }
1213 }
1214
1215 // By default reset the transmission buffer
1216 tx = txbuf;
1217 switch(htf) {
1218 case RHT2F_PASSWORD: {
1219 bStop = !hitag2_password(rx,rxlen,tx,&txlen);
1220 } break;
1221 case RHT2F_AUTHENTICATE: {
1222 bStop = !hitag2_authenticate(rx,rxlen,tx,&txlen);
1223 } break;
1224 case RHT2F_CRYPTO: {
1225 bStop = !hitag2_crypto(rx,rxlen,tx,&txlen);
1226 } break;
1227 case RHT2F_TEST_AUTH_ATTEMPTS: {
1228 bStop = !hitag2_test_auth_attempts(rx,rxlen,tx,&txlen);
1229 } break;
1230 default: {
1231 Dbprintf("Error, unknown function: %d",htf);
1232 return;
1233 } break;
1234 }
1235
1236 // Send and store the reader command
1237 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1238 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1239
1240 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1241 // Since the clock counts since the last falling edge, a 'one' means that the
1242 // falling edge occured halfway the period. with respect to this falling edge,
1243 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1244 // All timer values are in terms of T0 units
1245 while(AT91C_BASE_TC0->TC_CV < T0*(t_wait+(HITAG_T_TAG_HALF_PERIOD*lastbit)));
1246
1247 // Transmit the reader frame
1248 hitag_reader_send_frame(tx,txlen);
1249
1250 // Enable and reset external trigger in timer for capturing future frames
1251 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1252
1253 // Add transmitted frame to total count
1254 if(txlen > 0) {
1255 frame_count++;
1256 if (!bQuiet) {
1257 // Store the frame in the trace
1258 if (!LogTrace(tx,nbytes(txlen),HITAG_T_WAIT_2,0,true)) {
1259 if (bQuitTraceFull) {
1260 break;
1261 } else {
1262 bQuiet = true;
1263 }
1264 }
1265 }
1266 }
1267
1268 // Reset values for receiving frames
1269 memset(rx,0x00,sizeof(rx));
1270 rxlen = 0;
1271 lastbit = 1;
1272 bSkip = true;
1273 tag_sof = reset_sof;
1274 response = 0;
1275
1276 // Receive frame, watch for at most T0*EOF periods
1277 while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_WAIT_MAX) {
1278 // Check if falling edge in tag modulation is detected
1279 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1280 // Retrieve the new timing values
1281 int ra = (AT91C_BASE_TC1->TC_RA/T0);
1282
1283 // Reset timer every frame, we have to capture the last edge for timing
1284 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
1285
1286 LED_B_ON();
1287
1288 // Capture tag frame (manchester decoding using only falling edges)
1289 if(ra >= HITAG_T_EOF) {
1290 if (rxlen != 0) {
1291 //DbpString("wierd1?");
1292 }
1293 // Capture the T0 periods that have passed since last communication or field drop (reset)
1294 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
1295 response = ra-HITAG_T_TAG_HALF_PERIOD;
1296 } else if(ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
1297 // Manchester coding example |-_|_-|-_| (101)
1298 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
1299 rxlen++;
1300 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
1301 rxlen++;
1302 } else if(ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
1303 // Manchester coding example |_-|...|_-|-_| (0...01)
1304 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
1305 rxlen++;
1306 // We have to skip this half period at start and add the 'one' the second time
1307 if (!bSkip) {
1308 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
1309 rxlen++;
1310 }
1311 lastbit = !lastbit;
1312 bSkip = !bSkip;
1313 } else if(ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
1314 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
1315 if (tag_sof) {
1316 // Ignore bits that are transmitted during SOF
1317 tag_sof--;
1318 } else {
1319 // bit is same as last bit
1320 rx[rxlen / 8] |= lastbit << (7-(rxlen%8));
1321 rxlen++;
1322 }
1323 } else {
1324 // Ignore wierd value, is to small to mean anything
1325 }
1326 }
1327
1328 // We can break this loop if we received the last bit from a frame
1329 if (AT91C_BASE_TC1->TC_CV > T0*HITAG_T_EOF) {
1330 if (rxlen>0) break;
1331 }
1332 }
1333 }
1334 LED_B_OFF();
1335 LED_D_OFF();
1336 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1337 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1338 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1339
1340 // Dbprintf("frame received: %d",frame_count);
1341 // DbpString("All done");
1342 }
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