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1 //-----------------------------------------------------------------------------
2 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
3 // and the ARM. In the low-frequency modes it passes the data straight
4 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
5 // frequency modes, the FPGA might perform some demodulation first, to
6 // reduce the amount of data that we must send to the ARM.
7 //
8 // I am not really an FPGA/ASIC designer, so I am sure that a lot of this
9 // could be improved.
10 //
11 // Jonathan Westhues, March 2006
12 // Added ISO14443-A support by Gerhard de Koning Gans, April 2008
13 //-----------------------------------------------------------------------------
14
15 `include "lo_read.v"
16 `include "lo_simulate.v"
17 `include "hi_read_tx.v"
18 `include "hi_read_rx_xcorr.v"
19 `include "hi_simulate.v"
20 `include "hi_iso14443a.v"
21 `include "util.v"
22
23 module fpga(
24 spcki, miso, mosi, ncs,
25 pck0i, ck_1356meg, ck_1356megb,
26 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
27 adc_d, adc_clk, adc_noe,
28 ssp_frame, ssp_din, ssp_dout, ssp_clk,
29 cross_hi, cross_lo,
30 dbg
31 );
32 input spcki, mosi, ncs;
33 output miso;
34 input pck0i, ck_1356meg, ck_1356megb;
35 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
36 input [7:0] adc_d;
37 output adc_clk, adc_noe;
38 input ssp_dout;
39 output ssp_frame, ssp_din, ssp_clk;
40 input cross_hi, cross_lo;
41 output dbg;
42
43 //assign pck0 = pck0i;
44 IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
45 .O(pck0),
46 .I(pck0i)
47 );
48 //assign spck = spcki;
49 IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
50 .O(spck),
51 .I(spcki)
52 );
53 //-----------------------------------------------------------------------------
54 // The SPI receiver. This sets up the configuration word, which the rest of
55 // the logic looks at to determine how to connect the A/D and the coil
56 // drivers (i.e., which section gets it). Also assign some symbolic names
57 // to the configuration bits, for use below.
58 //-----------------------------------------------------------------------------
59
60 reg [15:0] shift_reg;
61 reg [7:0] divisor;
62 reg [7:0] conf_word;
63
64 // We switch modes between transmitting to the 13.56 MHz tag and receiving
65 // from it, which means that we must make sure that we can do so without
66 // glitching, or else we will glitch the transmitted carrier.
67 always @(posedge ncs)
68 begin
69 case(shift_reg[15:12])
70 4'b0001: conf_word <= shift_reg[7:0];
71 4'b0010: divisor <= shift_reg[7:0];
72 endcase
73 end
74
75 always @(posedge spck)
76 begin
77 if(~ncs)
78 begin
79 shift_reg[15:1] <= shift_reg[14:0];
80 shift_reg[0] <= mosi;
81 end
82 end
83
84 wire [2:0] major_mode;
85 assign major_mode = conf_word[7:5];
86
87 // For the low-frequency configuration:
88 wire lo_is_125khz;
89 assign lo_is_125khz = conf_word[3];
90
91 // For the high-frequency transmit configuration: modulation depth, either
92 // 100% (just quite driving antenna, steady LOW), or shallower (tri-state
93 // some fraction of the buffers)
94 wire hi_read_tx_shallow_modulation;
95 assign hi_read_tx_shallow_modulation = conf_word[0];
96
97 // For the high-frequency receive correlator: frequency against which to
98 // correlate.
99 wire hi_read_rx_xcorr_848;
100 assign hi_read_rx_xcorr_848 = conf_word[0];
101 // and whether to drive the coil (reader) or just short it (snooper)
102 wire hi_read_rx_xcorr_snoop;
103 assign hi_read_rx_xcorr_snoop = conf_word[1];
104
105 // For the high-frequency simulated tag: what kind of modulation to use.
106 wire [2:0] hi_simulate_mod_type;
107 assign hi_simulate_mod_type = conf_word[2:0];
108
109 //-----------------------------------------------------------------------------
110 // And then we instantiate the modules corresponding to each of the FPGA's
111 // major modes, and use muxes to connect the outputs of the active mode to
112 // the output pins.
113 //-----------------------------------------------------------------------------
114
115 lo_read lr(
116 pck0, ck_1356meg, ck_1356megb,
117 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
118 adc_d, lr_adc_clk,
119 lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
120 cross_hi, cross_lo,
121 lr_dbg,
122 lo_is_125khz, divisor
123 );
124
125 lo_simulate ls(
126 pck0, ck_1356meg, ck_1356megb,
127 ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
128 adc_d, ls_adc_clk,
129 ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
130 cross_hi, cross_lo,
131 ls_dbg
132 );
133
134 hi_read_tx ht(
135 pck0, ck_1356meg, ck_1356megb,
136 ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
137 adc_d, ht_adc_clk,
138 ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
139 cross_hi, cross_lo,
140 ht_dbg,
141 hi_read_tx_shallow_modulation
142 );
143
144 hi_read_rx_xcorr hrxc(
145 pck0, ck_1356meg, ck_1356megb,
146 hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
147 adc_d, hrxc_adc_clk,
148 hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
149 cross_hi, cross_lo,
150 hrxc_dbg,
151 hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop
152 );
153
154 hi_simulate hs(
155 pck0, ck_1356meg, ck_1356megb,
156 hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
157 adc_d, hs_adc_clk,
158 hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
159 cross_hi, cross_lo,
160 hs_dbg,
161 hi_simulate_mod_type
162 );
163
164 hi_iso14443a hisn(
165 pck0, ck_1356meg, ck_1356megb,
166 hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
167 adc_d, hisn_adc_clk,
168 hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
169 cross_hi, cross_lo,
170 hisn_dbg,
171 hi_simulate_mod_type
172 );
173
174 // Major modes:
175 // 000 -- LF reader (generic)
176 // 001 -- LF simulated tag (generic)
177 // 010 -- HF reader, transmitting to tag; modulation depth selectable
178 // 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
179 // 100 -- HF simulated tag
180 // 101 -- HF ISO14443-A
181 // 110 -- unused
182 // 111 -- everything off
183
184 mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1'b0, 1'b0);
185 mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1'b0, 1'b0);
186 mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0);
187 mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1'b0, 1'b0);
188 mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1'b0, 1'b0);
189 mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1'b0, 1'b0);
190 mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1'b0, 1'b0);
191 mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1'b0, 1'b0);
192 mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1'b0, 1'b0);
193 mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1'b0, 1'b0);
194 mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0);
195
196 // In all modes, let the ADC's outputs be enabled.
197 assign adc_noe = 1'b0;
198
199 endmodule
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