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1 //-----------------------------------------------------------------------------
2 //
3 // Jonathan Westhues, April 2006
4 //-----------------------------------------------------------------------------
5
6 module hi_read_rx_xcorr(
7 pck0, ck_1356meg, ck_1356megb,
8 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
9 adc_d, adc_clk,
10 ssp_frame, ssp_din, ssp_dout, ssp_clk,
11 cross_hi, cross_lo,
12 dbg,
13 xcorr_is_848, snoop
14 );
15 input pck0, ck_1356meg, ck_1356megb;
16 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
17 input [7:0] adc_d;
18 output adc_clk;
19 input ssp_dout;
20 output ssp_frame, ssp_din, ssp_clk;
21 input cross_hi, cross_lo;
22 output dbg;
23 input xcorr_is_848, snoop;
24
25 // Carrier is steady on through this, unless we're snooping.
26 assign pwr_hi = ck_1356megb & (~snoop);
27 assign pwr_oe1 = 1'b0;
28 assign pwr_oe3 = 1'b0;
29 assign pwr_oe4 = 1'b0;
30
31 wire adc_clk = ck_1356megb;
32
33 reg fc_div_2;
34 always @(negedge ck_1356megb)
35 fc_div_2 <= fc_div_2 + 1;
36
37 // When we're a reader, we just need to do the BPSK demod; but when we're an
38 // eavesdropper, we also need to pick out the commands sent by the reader,
39 // using AM. Do this the same way that we do it for the simulated tag.
40 reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
41 reg [11:0] has_been_low_for;
42 always @(negedge adc_clk)
43 begin
44 if(& adc_d[7:0]) after_hysteresis <= 1'b1;
45 else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
46
47 if(after_hysteresis)
48 begin
49 has_been_low_for <= 7'b0;
50 end
51 else
52 begin
53 if(has_been_low_for == 12'd4095)
54 begin
55 has_been_low_for <= 12'd0;
56 after_hysteresis <= 1'b1;
57 end
58 else
59 has_been_low_for <= has_been_low_for + 1;
60 end
61 end
62
63 // Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
64 // so we need a 6-bit counter.
65 reg [5:0] corr_i_cnt;
66 // And a couple of registers in which to accumulate the correlations.
67 // we would add at most 32 times adc_d, the result can be held in 13 bits.
68 // Need one additional bit because it can be negative as well
69 reg signed [13:0] corr_i_accum;
70 reg signed [13:0] corr_q_accum;
71 reg signed [7:0] corr_i_out;
72 reg signed [7:0] corr_q_out;
73 // clock and frame signal for communication to ARM
74 reg ssp_clk;
75 reg ssp_frame;
76
77
78 always @(negedge adc_clk)
79 begin
80 if (xcorr_is_848 | fc_div_2)
81 corr_i_cnt <= corr_i_cnt + 1;
82 end
83
84
85 // ADC data appears on the rising edge, so sample it on the falling edge
86 always @(negedge adc_clk)
87 begin
88 // These are the correlators: we correlate against in-phase and quadrature
89 // versions of our reference signal, and keep the (signed) result to
90 // send out later over the SSP.
91 if(corr_i_cnt == 6'd0)
92 begin
93 if(snoop)
94 begin
95 // Send only 7 most significant bits of tag signal (signed), LSB is reader signal:
96 corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
97 corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
98 after_hysteresis_prev_prev <= after_hysteresis;
99 end
100 else
101 begin
102 // 8 most significant bits of tag signal
103 corr_i_out <= corr_i_accum[13:6];
104 corr_q_out <= corr_q_accum[13:6];
105 end
106
107 corr_i_accum <= adc_d;
108 corr_q_accum <= adc_d;
109 end
110 else
111 begin
112 if(corr_i_cnt[3])
113 corr_i_accum <= corr_i_accum - adc_d;
114 else
115 corr_i_accum <= corr_i_accum + adc_d;
116
117 if(corr_i_cnt[3] == corr_i_cnt[2]) // phase shifted by pi/2
118 corr_q_accum <= corr_q_accum + adc_d;
119 else
120 corr_q_accum <= corr_q_accum - adc_d;
121
122 end
123
124 // The logic in hi_simulate.v reports 4 samples per bit. We report two
125 // (I, Q) pairs per bit, so we should do 2 samples per pair.
126 if(corr_i_cnt == 6'd32)
127 after_hysteresis_prev <= after_hysteresis;
128
129 // Then the result from last time is serialized and send out to the ARM.
130 // We get one report each cycle, and each report is 16 bits, so the
131 // ssp_clk should be the adc_clk divided by 64/16 = 4.
132
133 if(corr_i_cnt[1:0] == 2'b10)
134 ssp_clk <= 1'b0;
135
136 if(corr_i_cnt[1:0] == 2'b00)
137 begin
138 ssp_clk <= 1'b1;
139 // Don't shift if we just loaded new data, obviously.
140 if(corr_i_cnt != 7'd0)
141 begin
142 corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
143 corr_q_out[7:1] <= corr_q_out[6:0];
144 end
145 end
146
147 // set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
148 // (send two frames with 8 Bits each)
149 if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
150 ssp_frame = 1'b1;
151 else
152 ssp_frame = 1'b0;
153
154 end
155
156 assign ssp_din = corr_i_out[7];
157
158 assign dbg = corr_i_cnt[3];
159
160 // Unused.
161 assign pwr_lo = 1'b0;
162 assign pwr_oe2 = 1'b0;
163
164 endmodule
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