Experimental HitagS support
[proxmark3-svn] / armsrc / hitagS.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // HitagS emulation (preliminary test version)
7 //
8 // (c) 2016 Oguzhan Cicek, Hendrik Schwartke, Ralf Spenneberg
9 // <info@os-s.de>
10 //-----------------------------------------------------------------------------
11 // Some code was copied from Hitag2.c
12 //-----------------------------------------------------------------------------
13
14
15 #include <stdio.h>
16 #include <stdlib.h>
17 #include "proxmark3.h"
18 #include "apps.h"
19 #include "util.h"
20 #include "hitagS.h"
21 #include "hitag2.h"
22 #include "string.h"
23 #include "BigBuf.h"
24
25 #define CRC_PRESET 0xFF
26 #define CRC_POLYNOM 0x1D
27
28 #define u8 uint8_t
29 #define u32 uint32_t
30 #define u64 uint64_t
31 #define rev8(x) ((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7))
32 #define rev16(x) (rev8 (x)+(rev8 (x>> 8)<< 8))
33 #define rev32(x) (rev16(x)+(rev16(x>>16)<<16))
34 #define rev64(x) (rev32(x)+(rev32(x>>32)<<32))
35 #define bit(x,n) (((x)>>(n))&1)
36 #define bit32(x,n) ((((x)[(n)>>5])>>((n)))&1)
37 #define inv32(x,i,n) ((x)[(i)>>5]^=((u32)(n))<<((i)&31))
38 #define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))
39
40 static bool bQuiet;
41 static bool bSuccessful;
42 static struct hitagS_tag tag;
43 static byte_t page_to_be_written = 0;
44 static int block_data_left = 0;
45 typedef enum modulation {
46 AC2K = 0, AC4K, MC4K, MC8K
47 } MOD;
48 static MOD m = AC2K; //used modulation
49 static uint32_t temp_uid;
50 static int temp2 = 0;
51 static int sof_bits; //number of start-of-frame bits
52 static byte_t pwdh0, pwdl0, pwdl1; //password bytes
53 static uint32_t rnd = 0x74124485; //randomnumber
54 static int test = 0;
55 size_t blocknr;
56 bool end=false;
57
58 // Single bit Hitag2 functions:
59 #define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))
60 static const u32 ht2_f4a = 0x2C79; // 0010 1100 0111 1001
61 static const u32 ht2_f4b = 0x6671; // 0110 0110 0111 0001
62 static const u32 ht2_f5c = 0x7907287B; // 0111 1001 0000 0111 0010 1000 0111 1011
63 #define ht2bs_4a(a,b,c,d) (~(((a|b)&c)^(a|d)^b))
64 #define ht2bs_4b(a,b,c,d) (~(((d|c)&(a^b))^(d|a|b)))
65 #define ht2bs_5c(a,b,c,d,e) (~((((((c^e)|d)&a)^b)&(c^b))^(((d^e)|a)&((d^b)|c))))
66 #define uf20bs u32
67
68 static u32 f20(const u64 x) {
69 u32 i5;
70
71 i5 = ((ht2_f4a >> i4(x, 1, 2, 4, 5)) & 1) * 1
72 + ((ht2_f4b >> i4(x, 7, 11, 13, 14)) & 1) * 2
73 + ((ht2_f4b >> i4(x, 16, 20, 22, 25)) & 1) * 4
74 + ((ht2_f4b >> i4(x, 27, 28, 30, 32)) & 1) * 8
75 + ((ht2_f4a >> i4(x, 33, 42, 43, 45)) & 1) * 16;
76
77 return (ht2_f5c >> i5) & 1;
78 }
79 static u64 hitag2_round(u64 *state) {
80 u64 x = *state;
81
82 x = (x >> 1)
83 + ((((x >> 0) ^ (x >> 2) ^ (x >> 3) ^ (x >> 6) ^ (x >> 7) ^ (x >> 8)
84 ^ (x >> 16) ^ (x >> 22) ^ (x >> 23) ^ (x >> 26) ^ (x >> 30)
85 ^ (x >> 41) ^ (x >> 42) ^ (x >> 43) ^ (x >> 46) ^ (x >> 47))
86 & 1) << 47);
87
88 *state = x;
89 return f20(x);
90 }
91 static u64 hitag2_init(const u64 key, const u32 serial, const u32 IV) {
92 u32 i;
93 u64 x = ((key & 0xFFFF) << 32) + serial;
94 for (i = 0; i < 32; i++) {
95 x >>= 1;
96 x += (u64) (f20(x) ^ (((IV >> i) ^ (key >> (i + 16))) & 1)) << 47;
97 }
98 return x;
99 }
100 static u32 hitag2_byte(u64 *x) {
101 u32 i, c;
102
103 for (i = 0, c = 0; i < 8; i++)
104 c += (u32) hitag2_round(x) << (i ^ 7);
105 return c;
106 }
107
108 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
109 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
110 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
111 // T0 = TIMER_CLOCK1 / 125000 = 192
112 #define T0 192
113
114 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
115 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
116
117 #define HITAG_FRAME_LEN 20
118 #define HITAG_T_STOP 36 /* T_EOF should be > 36 */
119 #define HITAG_T_LOW 8 /* T_LOW should be 4..10 */
120 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
121 #define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */
122 //#define HITAG_T_EOF 40 /* T_EOF should be > 36 */
123 #define HITAG_T_EOF 80 /* T_EOF should be > 36 */
124 #define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */
125 #define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */
126 #define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */
127
128 #define HITAG_T_TAG_ONE_HALF_PERIOD 10
129 #define HITAG_T_TAG_TWO_HALF_PERIOD 25
130 #define HITAG_T_TAG_THREE_HALF_PERIOD 41
131 #define HITAG_T_TAG_FOUR_HALF_PERIOD 57
132
133 #define HITAG_T_TAG_HALF_PERIOD 16
134 #define HITAG_T_TAG_FULL_PERIOD 32
135
136 #define HITAG_T_TAG_CAPTURE_ONE_HALF 13
137 #define HITAG_T_TAG_CAPTURE_TWO_HALF 25
138 #define HITAG_T_TAG_CAPTURE_THREE_HALF 41
139 #define HITAG_T_TAG_CAPTURE_FOUR_HALF 57
140
141 #define DEBUG 0
142
143 /*
144 * Implementation of the crc8 calculation from Hitag S
145 * from http://www.proxmark.org/files/Documents/125%20kHz%20-%20Hitag/HitagS.V11.pdf
146 */
147 void calc_crc(unsigned char * crc, unsigned char data, unsigned char Bitcount) {
148 *crc ^= data; // crc = crc (exor) data
149 do {
150 if (*crc & 0x80) // if (MSB-CRC == 1)
151 {
152 *crc <<= 1; // CRC = CRC Bit-shift left
153 *crc ^= CRC_POLYNOM; // CRC = CRC (exor) CRC_POLYNOM
154 } else {
155 *crc <<= 1; // CRC = CRC Bit-shift left
156 }
157 } while (--Bitcount);
158 }
159
160 static void hitag_send_bit(int bit) {
161 LED_A_ON();
162 // Reset clock for the next bit
163 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
164
165 switch (m) {
166 case AC2K:
167 if (bit == 0) {
168 // AC Coding --__
169 HIGH(GPIO_SSC_DOUT);
170 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
171 ;
172 LOW(GPIO_SSC_DOUT);
173 while (AT91C_BASE_TC0->TC_CV < T0 * 64)
174 ;
175 } else {
176 // AC coding -_-_
177 HIGH(GPIO_SSC_DOUT);
178 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
179 ;
180 LOW(GPIO_SSC_DOUT);
181 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
182 ;
183 HIGH(GPIO_SSC_DOUT);
184 while (AT91C_BASE_TC0->TC_CV < T0 * 48)
185 ;
186 LOW(GPIO_SSC_DOUT);
187 while (AT91C_BASE_TC0->TC_CV < T0 * 64)
188 ;;
189 }
190 LED_A_OFF();
191 break;
192 case AC4K:
193 if (bit == 0) {
194 // AC Coding --__
195 HIGH(GPIO_SSC_DOUT);
196 while (AT91C_BASE_TC0->TC_CV < T0 * HITAG_T_TAG_HALF_PERIOD)
197 ;
198 LOW(GPIO_SSC_DOUT);
199 while (AT91C_BASE_TC0->TC_CV < T0 * HITAG_T_TAG_FULL_PERIOD)
200 ;
201 } else {
202 // AC coding -_-_
203 HIGH(GPIO_SSC_DOUT);
204 while (AT91C_BASE_TC0->TC_CV < T0 * 8)
205 ;
206 LOW(GPIO_SSC_DOUT);
207 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
208 ;
209 HIGH(GPIO_SSC_DOUT);
210 while (AT91C_BASE_TC0->TC_CV < T0 * 24)
211 ;
212 LOW(GPIO_SSC_DOUT);
213 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
214 ;;
215 }
216 LED_A_OFF();
217 break;
218 case MC4K:
219 if (bit == 0) {
220 // Manchester: Unloaded, then loaded |__--|
221 LOW(GPIO_SSC_DOUT);
222 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
223 ;
224 HIGH(GPIO_SSC_DOUT);
225 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
226 ;
227 } else {
228 // Manchester: Loaded, then unloaded |--__|
229 HIGH(GPIO_SSC_DOUT);
230 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
231 ;
232 LOW(GPIO_SSC_DOUT);
233 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
234 ;
235 }
236 LED_A_OFF();
237 break;
238 case MC8K:
239 if (bit == 0) {
240 // Manchester: Unloaded, then loaded |__--|
241 LOW(GPIO_SSC_DOUT);
242 while (AT91C_BASE_TC0->TC_CV < T0 * 8)
243 ;
244 HIGH(GPIO_SSC_DOUT);
245 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
246 ;
247 } else {
248 // Manchester: Loaded, then unloaded |--__|
249 HIGH(GPIO_SSC_DOUT);
250 while (AT91C_BASE_TC0->TC_CV < T0 * 8)
251 ;
252 LOW(GPIO_SSC_DOUT);
253 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
254 ;
255 }
256 LED_A_OFF();
257 break;
258 default:
259 break;
260 }
261 }
262
263 static void hitag_send_frame(const byte_t* frame, size_t frame_len) {
264 // Send start of frame
265
266 for (size_t i = 0; i < sof_bits; i++) {
267 hitag_send_bit(1);
268 }
269
270 // Send the content of the frame
271 for (size_t i = 0; i < frame_len; i++) {
272 hitag_send_bit((frame[i / 8] >> (7 - (i % 8))) & 1);
273 }
274 // Drop the modulation
275 LOW(GPIO_SSC_DOUT);
276 }
277
278 static void hitag_reader_send_bit(int bit) {
279 //Dbprintf("BIT: %d",bit);
280 LED_A_ON();
281 // Reset clock for the next bit
282 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
283
284 // Binary puls length modulation (BPLM) is used to encode the data stream
285 // This means that a transmission of a one takes longer than that of a zero
286
287 // Enable modulation, which means, drop the the field
288 HIGH(GPIO_SSC_DOUT);
289 if (test == 1) {
290 // Wait for 4-10 times the carrier period
291 while (AT91C_BASE_TC0->TC_CV < T0 * 6)
292 ;
293 // SpinDelayUs(8*8);
294
295 // Disable modulation, just activates the field again
296 LOW(GPIO_SSC_DOUT);
297
298 if (bit == 0) {
299 // Zero bit: |_-|
300 while (AT91C_BASE_TC0->TC_CV < T0 * 11)
301 ;
302 // SpinDelayUs(16*8);
303 } else {
304 // One bit: |_--|
305 while (AT91C_BASE_TC0->TC_CV < T0 * 14)
306 ;
307 // SpinDelayUs(22*8);
308 }
309 } else {
310 // Wait for 4-10 times the carrier period
311 while (AT91C_BASE_TC0->TC_CV < T0 * 6)
312 ;
313 // SpinDelayUs(8*8);
314
315 // Disable modulation, just activates the field again
316 LOW(GPIO_SSC_DOUT);
317
318 if (bit == 0) {
319 // Zero bit: |_-|
320 while (AT91C_BASE_TC0->TC_CV < T0 * 22)
321 ;
322 // SpinDelayUs(16*8);
323 } else {
324 // One bit: |_--|
325 while (AT91C_BASE_TC0->TC_CV < T0 * 28)
326 ;
327 // SpinDelayUs(22*8);
328 }
329 }
330
331 LED_A_OFF();
332 }
333
334 static void hitag_reader_send_frame(const byte_t* frame, size_t frame_len) {
335 // Send the content of the frame
336 for (size_t i = 0; i < frame_len; i++) {
337 if (frame[0] == 0xf8) {
338 //Dbprintf("BIT: %d",(frame[i / 8] >> (7 - (i % 8))) & 1);
339 }
340 hitag_reader_send_bit((frame[i / 8] >> (7 - (i % 8))) & 1);
341 }
342 // Send EOF
343 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
344 // Enable modulation, which means, drop the the field
345 HIGH(GPIO_SSC_DOUT);
346 // Wait for 4-10 times the carrier period
347 while (AT91C_BASE_TC0->TC_CV < T0 * 6)
348 ;
349 // Disable modulation, just activates the field again
350 LOW(GPIO_SSC_DOUT);
351 }
352
353 /*
354 * to check if the right uid was selected
355 */
356 static int check_select(byte_t* rx, uint32_t uid) {
357 unsigned char resp[48];
358 int i;
359 uint32_t ans = 0x0;
360 for (i = 0; i < 48; i++)
361 resp[i] = (rx[i / 8] >> (7 - (i % 8))) & 0x1;
362 for (i = 0; i < 32; i++)
363 ans += resp[5 + i] << (31 - i);
364 /*if (rx[0] == 0x01 && rx[1] == 0x15 && rx[2] == 0xc1 && rx[3] == 0x14
365 && rx[4] == 0x65 && rx[5] == 0x38)
366 Dbprintf("got uid %X", ans);*/
367 temp_uid = ans;
368 if (ans == tag.uid)
369 return 1;
370 return 0;
371 }
372
373 /*
374 * handles all commands from a reader
375 */
376 static void hitagS_handle_reader_command(byte_t* rx, const size_t rxlen,
377 byte_t* tx, size_t* txlen) {
378 byte_t rx_air[HITAG_FRAME_LEN];
379 byte_t page;
380 int i;
381 u64 state;
382 unsigned char crc;
383
384 // Copy the (original) received frame how it is send over the air
385 memcpy(rx_air, rx, nbytes(rxlen));
386 // Reset the transmission frame length
387 *txlen = 0;
388 // Try to find out which command was send by selecting on length (in bits)
389 switch (rxlen) {
390 case 5: {
391 //UID request with a selected response protocol mode
392 tag.pstate = READY;
393 tag.tstate = NO_OP;
394 if ((rx[0] & 0xf0) == 0x30) {
395 tag.mode = STANDARD;
396 sof_bits = 1;
397 m = AC2K;
398 }
399 if ((rx[0] & 0xf0) == 0xc0) {
400 tag.mode = ADVANCED;
401 sof_bits = 3;
402 m = AC2K;
403 }
404
405 if ((rx[0] & 0xf0) == 0xd0) {
406 tag.mode = FAST_ADVANCED;
407 sof_bits = 3;
408 m = AC4K;
409 }
410 //send uid as a response
411 *txlen = 32;
412 for (i = 0; i < 4; i++)
413 tx[i] = (tag.uid >> (24 - (i * 8))) & 0xff;
414 }
415 break;
416 case 45: {
417 //select command from reader received
418 if (check_select(rx, tag.uid) == 1) {
419 //if the right tag was selected
420 *txlen = 32;
421 switch (tag.mode) {
422 case STANDARD:
423 sof_bits = 1;
424 m = MC4K;
425 break;
426 case ADVANCED:
427 sof_bits = 6;
428 m = MC4K;
429 break;
430 case FAST_ADVANCED:
431 sof_bits = 6;
432 m = MC8K;
433 break;
434 default:
435 break;
436 }
437
438 //send configuration
439 for (i = 0; i < 4; i++)
440 tx[i] = (tag.pages[0][1] >> (i * 8)) & 0xff;
441 tx[3] = 0xff;
442 if (tag.mode != STANDARD) {
443 *txlen = 40;
444 crc = CRC_PRESET;
445 for (i = 0; i < 4; i++)
446 calc_crc(&crc, tx[i], 8);
447 tx[4] = crc;
448 }
449 }
450 }
451 break;
452 case 64: {
453 //challenge message received
454 Dbprintf("Challenge for UID: %X", temp_uid);
455 temp2++;
456 *txlen = 32;
457 state = hitag2_init(rev64(tag.key), rev32(tag.pages[0][0]),
458 rev32(((rx[3] << 24) + (rx[2] << 16) + (rx[1] << 8) + rx[0])));
459 Dbprintf(
460 ",{0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X}",
461 rx[0], rx[1], rx[2], rx[3], rx[4], rx[5], rx[6], rx[7]);
462 switch (tag.mode) {
463 case STANDARD:
464 sof_bits = 1;
465 m = MC4K;
466 break;
467 case ADVANCED:
468 sof_bits = 6;
469 m = MC4K;
470 break;
471 case FAST_ADVANCED:
472 sof_bits = 6;
473 m = MC8K;
474 break;
475 default:
476 break;
477 }
478
479 for (i = 0; i < 4; i++)
480 hitag2_byte(&state);
481 //send con2,pwdh0,pwdl0,pwdl1 encrypted as a response
482 tx[0] = hitag2_byte(&state) ^ ((tag.pages[0][1] >> 16) & 0xff);
483 tx[1] = hitag2_byte(&state) ^ tag.pwdh0;
484 tx[2] = hitag2_byte(&state) ^ tag.pwdl0;
485 tx[3] = hitag2_byte(&state) ^ tag.pwdl1;
486 if (tag.mode != STANDARD) {
487 //add crc8
488 *txlen = 40;
489 crc = CRC_PRESET;
490 calc_crc(&crc, ((tag.pages[0][1] >> 16) & 0xff), 8);
491 calc_crc(&crc, tag.pwdh0, 8);
492 calc_crc(&crc, tag.pwdl0, 8);
493 calc_crc(&crc, tag.pwdl1, 8);
494 tx[4] = (crc ^ hitag2_byte(&state));
495 }
496 /*
497 * some readers do not allow to authenticate multiple times in a row with the same tag.
498 * use this to change the uid between authentications.
499 */
500
501 /*
502 if (temp2 % 2 == 0) {
503 tag.uid = 0x11223344;
504 tag.pages[0][0] = 0x44332211;
505 } else {
506 tag.uid = 0x55667788;
507 tag.pages[0][0] = 0x88776655;
508 }
509 */
510 }
511 case 40:
512 //data received to be written
513 if (tag.tstate == WRITING_PAGE_DATA) {
514 tag.tstate = NO_OP;
515 tag.pages[page_to_be_written / 4][page_to_be_written % 4] = (rx[0]
516 << 0) + (rx[1] << 8) + (rx[2] << 16) + (rx[3] << 24);
517 //send ack
518 *txlen = 2;
519 tx[0] = 0x40;
520 page_to_be_written = 0;
521 switch (tag.mode) {
522 case STANDARD:
523 sof_bits = 1;
524 m = MC4K;
525 break;
526 case ADVANCED:
527 sof_bits = 6;
528 m = MC4K;
529 break;
530 case FAST_ADVANCED:
531 sof_bits = 6;
532 m = MC8K;
533 break;
534 default:
535 break;
536 }
537 } else if (tag.tstate == WRITING_BLOCK_DATA) {
538 tag.pages[page_to_be_written / 4][page_to_be_written % 4] = (rx[0]
539 << 24) + (rx[1] << 16) + (rx[2] << 8) + rx[3];
540 //send ack
541 *txlen = 2;
542 tx[0] = 0x40;
543 switch (tag.mode) {
544 case STANDARD:
545 sof_bits = 1;
546 m = MC4K;
547 break;
548 case ADVANCED:
549 sof_bits = 6;
550 m = MC4K;
551 break;
552 case FAST_ADVANCED:
553 sof_bits = 6;
554 m = MC8K;
555 break;
556 default:
557 break;
558 }
559 page_to_be_written++;
560 block_data_left--;
561 if (block_data_left == 0) {
562 tag.tstate = NO_OP;
563 page_to_be_written = 0;
564 }
565 }
566 break;
567 case 20: {
568 //write page, write block, read page or read block command received
569 if ((rx[0] & 0xf0) == 0xc0) //read page
570 {
571 //send page data
572 page = ((rx[0] & 0x0f) * 16) + ((rx[1] & 0xf0) / 16);
573 *txlen = 32;
574 tx[0] = (tag.pages[page / 4][page % 4]) & 0xff;
575 tx[1] = (tag.pages[page / 4][page % 4] >> 8) & 0xff;
576 tx[2] = (tag.pages[page / 4][page % 4] >> 16) & 0xff;
577 tx[3] = (tag.pages[page / 4][page % 4] >> 24) & 0xff;
578 if (tag.LKP && page == 1)
579 tx[3] = 0xff;
580
581 switch (tag.mode) {
582 case STANDARD:
583 sof_bits = 1;
584 m = MC4K;
585 break;
586 case ADVANCED:
587 sof_bits = 6;
588 m = MC4K;
589 break;
590 case FAST_ADVANCED:
591 sof_bits = 6;
592 m = MC8K;
593 break;
594 default:
595 break;
596 }
597
598 if (tag.mode != STANDARD) {
599 //add crc8
600 *txlen = 40;
601 crc = CRC_PRESET;
602 for (i = 0; i < 4; i++)
603 calc_crc(&crc, tx[i], 8);
604 tx[4] = crc;
605 }
606
607 if (tag.LKP && (page == 2 || page == 3)) {
608 //if reader asks for key or password and the LKP-mark is set do not respond
609 sof_bits = 0;
610 *txlen = 0;
611 }
612 } else if ((rx[0] & 0xf0) == 0xd0) //read block
613 {
614 page = ((rx[0] & 0x0f) * 16) + ((rx[1] & 0xf0) / 16);
615 *txlen = 32 * 4;
616 //send page,...,page+3 data
617 for (i = 0; i < 4; i++) {
618 tx[0 + i * 4] = (tag.pages[page / 4][page % 4]) & 0xff;
619 tx[1 + i * 4] = (tag.pages[page / 4][page % 4] >> 8) & 0xff;
620 tx[2 + i * 4] = (tag.pages[page / 4][page % 4] >> 16) & 0xff;
621 tx[3 + i * 4] = (tag.pages[page / 4][page % 4] >> 24) & 0xff;
622 page++;
623 }
624
625 switch (tag.mode) {
626 case STANDARD:
627 sof_bits = 1;
628 m = MC4K;
629 break;
630 case ADVANCED:
631 sof_bits = 6;
632 m = MC4K;
633 break;
634 case FAST_ADVANCED:
635 sof_bits = 6;
636 m = MC8K;
637 break;
638 default:
639 break;
640 }
641
642 if (tag.mode != STANDARD) {
643 //add crc8
644 *txlen = 32 * 4 + 8;
645 crc = CRC_PRESET;
646 for (i = 0; i < 16; i++)
647 calc_crc(&crc, tx[i], 8);
648 tx[16] = crc;
649 }
650
651 if ((page - 4) % 4 != 0 || (tag.LKP && (page - 4) == 0)) {
652 sof_bits = 0;
653 *txlen = 0;
654 }
655 } else if ((rx[0] & 0xf0) == 0x80) //write page
656 {
657 page = ((rx[0] & 0x0f) * 16) + ((rx[1] & 0xf0) / 16);
658
659 switch (tag.mode) {
660 case STANDARD:
661 sof_bits = 1;
662 m = MC4K;
663 break;
664 case ADVANCED:
665 sof_bits = 6;
666 m = MC4K;
667 break;
668 case FAST_ADVANCED:
669 sof_bits = 6;
670 m = MC8K;
671 break;
672 default:
673 break;
674 }
675 if ((tag.LCON && page == 1)
676 || (tag.LKP && (page == 2 || page == 3))) {
677 //deny
678 *txlen = 0;
679 } else {
680 //allow
681 *txlen = 2;
682 tx[0] = 0x40;
683 page_to_be_written = page;
684 tag.tstate = WRITING_PAGE_DATA;
685 }
686
687 } else if ((rx[0] & 0xf0) == 0x90) //write block
688 {
689 page = ((rx[0] & 0x0f) * 6) + ((rx[1] & 0xf0) / 16);
690 switch (tag.mode) {
691 case STANDARD:
692 sof_bits = 1;
693 m = MC4K;
694 break;
695 case ADVANCED:
696 sof_bits = 6;
697 m = MC4K;
698 break;
699 case FAST_ADVANCED:
700 sof_bits = 6;
701 m = MC8K;
702 break;
703 default:
704 break;
705 }
706 if (page % 4 != 0 || page == 0) {
707 //deny
708 *txlen = 0;
709 } else {
710 //allow
711 *txlen = 2;
712 tx[0] = 0x40;
713 page_to_be_written = page;
714 block_data_left = 4;
715 tag.tstate = WRITING_BLOCK_DATA;
716 }
717 }
718 }
719 break;
720 default:
721
722 break;
723 }
724 }
725
726 /*
727 * to autenticate to a tag with the given key or challenge
728 */
729 static int hitagS_handle_tag_auth(hitag_function htf,uint64_t key, uint64_t NrAr, byte_t* rx, const size_t rxlen, byte_t* tx,
730 size_t* txlen) {
731 byte_t rx_air[HITAG_FRAME_LEN];
732 int response_bit[200];
733 int i, j, z, k;
734 unsigned char mask = 1;
735 unsigned char uid[32];
736 byte_t uid1 = 0x00, uid2 = 0x00, uid3 = 0x00, uid4 = 0x00;
737 unsigned char crc;
738 u64 state;
739 byte_t auth_ks[4];
740 byte_t conf_pages[3];
741 memcpy(rx_air, rx, nbytes(rxlen));
742 *txlen = 0;
743
744 if (tag.pstate == READY && rxlen >= 67) {
745 //received uid
746 if(end==true) {
747 Dbprintf("authentication failed!");
748 return -1;
749 }
750 z = 0;
751 for (i = 0; i < 10; i++) {
752 for (j = 0; j < 8; j++) {
753 response_bit[z] = 0;
754 if ((rx[i] & ((mask << 7) >> j)) != 0)
755 response_bit[z] = 1;
756 z++;
757 }
758 }
759 k = 0;
760 for (i = 5; i < z; i += 2) {
761 uid[k] = response_bit[i];
762 k++;
763 if (k > 31)
764 break;
765 }
766 uid1 = (uid[0] << 7) | (uid[1] << 6) | (uid[2] << 5) | (uid[3] << 4)
767 | (uid[4] << 3) | (uid[5] << 2) | (uid[6] << 1) | uid[7];
768 uid2 = (uid[8] << 7) | (uid[9] << 6) | (uid[10] << 5) | (uid[11] << 4)
769 | (uid[12] << 3) | (uid[13] << 2) | (uid[14] << 1) | uid[15];
770 uid3 = (uid[16] << 7) | (uid[17] << 6) | (uid[18] << 5) | (uid[19] << 4)
771 | (uid[20] << 3) | (uid[21] << 2) | (uid[22] << 1) | uid[23];
772 uid4 = (uid[24] << 7) | (uid[25] << 6) | (uid[26] << 5) | (uid[27] << 4)
773 | (uid[28] << 3) | (uid[29] << 2) | (uid[30] << 1) | uid[31];
774 if (DEBUG)
775 Dbprintf("UID: %02X %02X %02X %02X", uid1, uid2, uid3, uid4);
776 tag.uid = (uid4 << 24 | uid3 << 16 | uid2 << 8 | uid1);
777
778 //select uid
779 *txlen = 45;
780 crc = CRC_PRESET;
781 calc_crc(&crc, 0x00, 5);
782 calc_crc(&crc, uid1, 8);
783 calc_crc(&crc, uid2, 8);
784 calc_crc(&crc, uid3, 8);
785 calc_crc(&crc, uid4, 8);
786 for (i = 0; i < 100; i++) {
787 response_bit[i] = 0;
788 }
789 for (i = 0; i < 5; i++) {
790 response_bit[i] = 0;
791 }
792 for (i = 5; i < 37; i++) {
793 response_bit[i] = uid[i - 5];
794 }
795 for (j = 0; j < 8; j++) {
796 response_bit[i] = 0;
797 if ((crc & ((mask << 7) >> j)) != 0)
798 response_bit[i] = 1;
799 i++;
800 }
801 k = 0;
802 for (i = 0; i < 6; i++) {
803 tx[i] = (response_bit[k] << 7) | (response_bit[k + 1] << 6)
804 | (response_bit[k + 2] << 5) | (response_bit[k + 3] << 4)
805 | (response_bit[k + 4] << 3) | (response_bit[k + 5] << 2)
806 | (response_bit[k + 6] << 1) | response_bit[k + 7];
807 k += 8;
808 }
809 tag.pstate = INIT;
810 } else if (tag.pstate == INIT && rxlen == 44) {
811 // received configuration after select command
812 z = 0;
813 for (i = 0; i < 6; i++) {
814 for (j = 0; j < 8; j++) {
815 response_bit[z] = 0;
816 if ((rx[i] & ((mask << 7) >> j)) != 0)
817 response_bit[z] = 1;
818 z++;
819 }
820 }
821 conf_pages[0] = ((response_bit[4] << 7) | (response_bit[5] << 6)
822 | (response_bit[6] << 5) | (response_bit[7] << 4)
823 | (response_bit[8] << 3) | (response_bit[9] << 2)
824 | (response_bit[10] << 1) | response_bit[11]);
825 //check wich memorysize this tag has
826 if (response_bit[10] == 0 && response_bit[11] == 0)
827 tag.max_page = 32 / 32;
828 if (response_bit[10] == 0 && response_bit[11] == 1)
829 tag.max_page = 256 / 32;
830 if (response_bit[10] == 1 && response_bit[11] == 0)
831 tag.max_page = 2048 / 32;
832 conf_pages[1] = ((response_bit[12] << 7) | (response_bit[13] << 6)
833 | (response_bit[14] << 5) | (response_bit[15] << 4)
834 | (response_bit[16] << 3) | (response_bit[17] << 2)
835 | (response_bit[18] << 1) | response_bit[19]);
836 tag.auth = response_bit[12];
837 tag.TTFC = response_bit[13];
838 //tag.TTFDR in response_bit[14] and response_bit[15]
839 //tag.TTFM in response_bit[16] and response_bit[17]
840 tag.LCON = response_bit[18];
841 tag.LKP = response_bit[19];
842 conf_pages[2] = ((response_bit[20] << 7) | (response_bit[21] << 6)
843 | (response_bit[22] << 5) | (response_bit[23] << 4)
844 | (response_bit[24] << 3) | (response_bit[25] << 2)
845 | (response_bit[26] << 1) | response_bit[27]);
846 tag.LCK7 = response_bit[20];
847 tag.LCK6 = response_bit[21];
848 tag.LCK5 = response_bit[22];
849 tag.LCK4 = response_bit[23];
850 tag.LCK3 = response_bit[24];
851 tag.LCK2 = response_bit[25];
852 tag.LCK1 = response_bit[26];
853 tag.LCK0 = response_bit[27];
854
855 if (DEBUG)
856 Dbprintf("conf0: %02X conf1: %02X conf2: %02X", conf_pages[0],
857 conf_pages[1], conf_pages[2]);
858 if (tag.auth == 1) {
859 //if the tag is in authentication mode try the key or challenge
860 *txlen = 64;
861 if(end!=true){
862 if(htf==02||htf==04){ //RHTS_KEY //WHTS_KEY
863 state = hitag2_init(rev64(key), rev32(tag.uid),
864 rev32(rnd));
865
866 for (i = 0; i < 4; i++) {
867 auth_ks[i] = hitag2_byte(&state) ^ 0xff;
868 }
869 *txlen = 64;
870 tx[0] = rnd & 0xff;
871 tx[1] = (rnd >> 8) & 0xff;
872 tx[2] = (rnd >> 16) & 0xff;
873 tx[3] = (rnd >> 24) & 0xff;
874
875 tx[4] = auth_ks[0];
876 tx[5] = auth_ks[1];
877 tx[6] = auth_ks[2];
878 tx[7] = auth_ks[3];
879 if (DEBUG)
880 Dbprintf("%02X %02X %02X %02X %02X %02X %02X %02X", tx[0],
881 tx[1], tx[2], tx[3], tx[4], tx[5], tx[6], tx[7]);
882 } else if(htf==01 || htf==03) { //RHTS_CHALLENGE //WHTS_CHALLENGE
883 for (i = 0; i < 8; i++)
884 tx[i]=((NrAr>>(56-(i*8)))&0xff);
885 }
886 end=true;
887 tag.pstate = AUTHENTICATE;
888 } else {
889 Dbprintf("authentication failed!");
890 return -1;
891 }
892 } else if (tag.auth == 0) {
893 tag.pstate = SELECTED;
894 }
895
896 } else if (tag.pstate == AUTHENTICATE && rxlen == 44) {
897 //encrypted con2,password received.
898 crc = CRC_PRESET;
899 calc_crc(&crc, 0x80, 1);
900 calc_crc(&crc, ((rx[0] & 0x0f) * 16 + ((rx[1] & 0xf0) / 16)), 8);
901 calc_crc(&crc, ((rx[1] & 0x0f) * 16 + ((rx[2] & 0xf0) / 16)), 8);
902 calc_crc(&crc, ((rx[2] & 0x0f) * 16 + ((rx[3] & 0xf0) / 16)), 8);
903 calc_crc(&crc, ((rx[3] & 0x0f) * 16 + ((rx[4] & 0xf0) / 16)), 8);
904 if (DEBUG) {
905 Dbprintf("UID:::%X", tag.uid);
906 Dbprintf("RND:::%X", rnd);
907 }
908
909 //decrypt password
910 pwdh0=0;
911 pwdl0=0;
912 pwdl1=0;
913 if(htf==02 || htf==04){ //RHTS_KEY //WHTS_KEY
914 {
915 state = hitag2_init(rev64(key), rev32(tag.uid), rev32(rnd));
916 for (i = 0; i < 5; i++)
917 hitag2_byte(&state);
918 pwdh0 = ((rx[1] & 0x0f) * 16 + ((rx[2] & 0xf0) / 16))
919 ^ hitag2_byte(&state);
920 pwdl0 = ((rx[2] & 0x0f) * 16 + ((rx[3] & 0xf0) / 16))
921 ^ hitag2_byte(&state);
922 pwdl1 = ((rx[3] & 0x0f) * 16 + ((rx[4] & 0xf0) / 16))
923 ^ hitag2_byte(&state);
924 }
925
926 if (DEBUG)
927 Dbprintf("pwdh0 %02X pwdl0 %02X pwdl1 %02X", pwdh0, pwdl0, pwdl1);
928
929
930 //Dbprintf("%X %02X", rnd, ((rx[4] & 0x0f) * 16) + ((rx[5] & 0xf0) / 16));
931 //rnd += 1;
932 }
933 tag.pstate = SELECTED; //tag is now ready for read/write commands
934 }
935 return 0;
936
937 }
938
939 /*
940 * Emulates a Hitag S Tag with the given data from the .hts file
941 */
942 void SimulateHitagSTag(bool tag_mem_supplied, byte_t* data) {
943 int frame_count;
944 int response;
945 int overflow;
946 int i, j;
947 byte_t rx[HITAG_FRAME_LEN];
948 size_t rxlen = 0;
949 //bool bQuitTraceFull = false;
950 bQuiet = false;
951 byte_t txbuf[HITAG_FRAME_LEN];
952 byte_t* tx = txbuf;
953 size_t txlen = 0;
954 BigBuf_free();
955
956 // Clean up trace and prepare it for storing frames
957 set_tracing(TRUE);
958 clear_trace();
959
960 DbpString("Starting HitagS simulation");
961 LED_D_ON();
962
963 tag.pstate = READY;
964 tag.tstate = NO_OP;
965 for (i = 0; i < 16; i++)
966 for (j = 0; j < 4; j++)
967 tag.pages[i][j] = 0x0;
968 //read tag data into memory
969 if (tag_mem_supplied) {
970 DbpString("Loading hitagS memory...");
971 memcpy((byte_t*)tag.pages,data,4*64);
972 }
973 tag.uid=(uint32_t)tag.pages[0];
974 Dbprintf("Hitag S simulation started");
975 tag.key=(intptr_t)tag.pages[3];
976 tag.key<<=16;
977 tag.key+=((tag.pages[2][0])<<8)+tag.pages[2][1];
978 tag.pwdl0=tag.pages[2][3];
979 tag.pwdl1=tag.pages[2][2];
980 tag.pwdh0=tag.pages[1][0];
981 //con0
982 tag.max_page=64;
983 if((tag.pages[1][3]&0x2)==0 && (tag.pages[1][3]&0x1)==1)
984 tag.max_page=8;
985 if((tag.pages[1][3]&0x2)==0 && (tag.pages[1][3]&0x1)==0)
986 tag.max_page=0;
987 //con1
988 tag.auth=0;
989 if((tag.pages[1][2]&0x80)==1)
990 tag.auth=1;
991 tag.LCON=0;
992 if((tag.pages[1][2]&0x2)==1)
993 tag.LCON=1;
994 tag.LKP=0;
995 if((tag.pages[1][2]&0x1)==1)
996 tag.LKP=1;
997 //con2
998 //0=read write 1=read only
999 tag.LCK7=0;
1000 if((tag.pages[1][1]&0x80)==1)
1001 tag.LCK7=1;
1002 tag.LCK6=0;
1003 if((tag.pages[1][1]&0x40)==1)
1004 tag.LCK6=1;
1005 tag.LCK5=0;
1006 if((tag.pages[1][1]&0x20)==1)
1007 tag.LCK5=1;
1008 tag.LCK4=0;
1009 if((tag.pages[1][1]&0x10)==1)
1010 tag.LCK4=1;
1011 tag.LCK3=0;
1012 if((tag.pages[1][1]&0x8)==1)
1013 tag.LCK3=1;
1014 tag.LCK2=0;
1015 if((tag.pages[1][1]&0x4)==1)
1016 tag.LCK2=1;
1017 tag.LCK1=0;
1018 if((tag.pages[1][1]&0x2)==1)
1019 tag.LCK1=1;
1020 tag.LCK0=0;
1021 if((tag.pages[1][1]&0x1)==1)
1022 tag.LCK0=1;
1023
1024 // Set up simulator mode, frequency divisor which will drive the FPGA
1025 // and analog mux selection.
1026 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1027 FpgaWriteConfWord(
1028 FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1029 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1030 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1031 RELAY_OFF();
1032
1033 // Configure output pin that is connected to the FPGA (for modulating)
1034 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1035 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1036
1037 // Disable modulation at default, which means release resistance
1038 LOW(GPIO_SSC_DOUT);
1039
1040 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1041 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1042
1043 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
1044 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1045 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1046
1047 // Disable timer during configuration
1048 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1049
1050 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1051 // external trigger rising edge, load RA on rising edge of TIOA.
1052 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1053 | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
1054
1055 // Reset the received frame, frame count and timing info
1056 memset(rx, 0x00, sizeof(rx));
1057 frame_count = 0;
1058 response = 0;
1059 overflow = 0;
1060
1061 // Enable and reset counter
1062 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1063
1064 while (!BUTTON_PRESS()) {
1065 // Watchdog hit
1066 WDT_HIT();
1067
1068 // Receive frame, watch for at most T0*EOF periods
1069 while (AT91C_BASE_TC1->TC_CV < T0 * HITAG_T_EOF) {
1070 // Check if rising edge in modulation is detected
1071 if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1072 // Retrieve the new timing values
1073 int ra = (AT91C_BASE_TC1->TC_RA / T0) + overflow;
1074 overflow = 0;
1075
1076 // Reset timer every frame, we have to capture the last edge for timing
1077 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1078
1079 LED_B_ON();
1080
1081 // Capture reader frame
1082 if (ra >= HITAG_T_STOP) {
1083 if (rxlen != 0) {
1084 //DbpString("wierd0?");
1085 }
1086 // Capture the T0 periods that have passed since last communication or field drop (reset)
1087 response = (ra - HITAG_T_LOW);
1088 } else if (ra >= HITAG_T_1_MIN) {
1089 // '1' bit
1090 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1091 rxlen++;
1092 } else if (ra >= HITAG_T_0_MIN) {
1093 // '0' bit
1094 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1095 rxlen++;
1096 } else {
1097 // Ignore wierd value, is to small to mean anything
1098 }
1099 }
1100 }
1101
1102 // Check if frame was captured
1103 if (rxlen > 0) {
1104 frame_count++;
1105 if (!bQuiet) {
1106 if (!LogTraceHitag(rx, rxlen, response, 0, true)) {
1107 DbpString("Trace full");
1108 clear_trace();
1109 }
1110 }
1111
1112 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1113 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1114
1115 // Process the incoming frame (rx) and prepare the outgoing frame (tx)
1116 hitagS_handle_reader_command(rx, rxlen, tx, &txlen);
1117
1118 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
1119 // not that since the clock counts since the rising edge, but T_Wait1 is
1120 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
1121 // periods. The gap time T_Low varies (4..10). All timer values are in
1122 // terms of T0 units
1123 while (AT91C_BASE_TC0->TC_CV < T0 * (HITAG_T_WAIT_1 - HITAG_T_LOW))
1124 ;
1125
1126 // Send and store the tag answer (if there is any)
1127 if (txlen > 0) {
1128 // Transmit the tag frame
1129 hitag_send_frame(tx, txlen);
1130 // Store the frame in the trace
1131 if (!bQuiet) {
1132 if (!LogTraceHitag(tx, txlen, 0, 0, false)) {
1133 DbpString("Trace full");
1134 clear_trace();
1135 }
1136 }
1137 }
1138
1139 // Reset the received frame and response timing info
1140 memset(rx, 0x00, sizeof(rx));
1141 response = 0;
1142
1143 // Enable and reset external trigger in timer for capturing future frames
1144 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1145 LED_B_OFF();
1146 }
1147 // Reset the frame length
1148 rxlen = 0;
1149 // Save the timer overflow, will be 0 when frame was received
1150 overflow += (AT91C_BASE_TC1->TC_CV / T0);
1151 // Reset the timer to restart while-loop that receives frames
1152 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
1153 }
1154 LED_B_OFF();
1155 LED_D_OFF();
1156 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1157 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1158 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1159 }
1160
1161 /*
1162 * Authenticates to the Tag with the given key or challenge.
1163 * If the key was given the password will be decrypted.
1164 * Reads every page of a hitag S transpoder.
1165 */
1166 void ReadHitagS(hitag_function htf, hitag_data* htd) {
1167 int i, j, z, k;
1168 int frame_count;
1169 int response_bit[200];
1170 int response;
1171 byte_t rx[HITAG_FRAME_LEN];
1172 size_t rxlen = 0;
1173 byte_t txbuf[HITAG_FRAME_LEN];
1174 byte_t* tx = txbuf;
1175 size_t txlen = 0;
1176 int lastbit;
1177 bool bSkip;
1178 int reset_sof;
1179 int tag_sof;
1180 int t_wait = HITAG_T_WAIT_MAX;
1181 bool bStop;
1182 bool bQuitTraceFull = false;
1183 int sendNum = 0;
1184 unsigned char mask = 1;
1185 unsigned char crc;
1186 unsigned char pageData[32];
1187 page_to_be_written = 0;
1188
1189 //read given key/challenge
1190 byte_t NrAr_[8];
1191 uint64_t key=0;
1192 uint64_t NrAr=0;
1193 byte_t key_[6];
1194 switch(htf) {
1195 case 01: { //RHTS_CHALLENGE
1196 DbpString("Authenticating using nr,ar pair:");
1197 memcpy(NrAr_,htd->auth.NrAr,8);
1198 Dbhexdump(8,NrAr_,false);
1199 NrAr=NrAr_[7] | ((uint64_t)NrAr_[6]) << 8 | ((uint64_t)NrAr_[5]) << 16 | ((uint64_t)NrAr_[4]) << 24 | ((uint64_t)NrAr_[3]) << 32 |
1200 ((uint64_t)NrAr_[2]) << 40| ((uint64_t)NrAr_[1]) << 48 | ((uint64_t)NrAr_[0]) << 56;
1201 } break;
1202 case 02: { //RHTS_KEY
1203 DbpString("Authenticating using key:");
1204 memcpy(key_,htd->crypto.key,6);
1205 Dbhexdump(6,key_,false);
1206 key=key_[5] | ((uint64_t)key_[4]) << 8 | ((uint64_t)key_[3]) << 16 | ((uint64_t)key_[2]) << 24 | ((uint64_t)key_[1]) << 32 | ((uint64_t)key_[0]) << 40;
1207 } break;
1208 default: {
1209 Dbprintf("Error , unknown function: %d",htf);
1210 return;
1211 } break;
1212 }
1213
1214
1215
1216 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1217 // Reset the return status
1218 bSuccessful = false;
1219
1220 // Clean up trace and prepare it for storing frames
1221 set_tracing(TRUE);
1222 clear_trace();
1223
1224 bQuiet = false;
1225 bQuitTraceFull = true;
1226
1227 LED_D_ON();
1228
1229 // Configure output and enable pin that is connected to the FPGA (for modulating)
1230 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1231 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1232
1233 // Set fpga in edge detect with reader field, we can modulate as reader now
1234 FpgaWriteConfWord(
1235 FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1236
1237 // Set Frequency divisor which will drive the FPGA and analog mux selection
1238 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1239 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1240 RELAY_OFF();
1241
1242 // Disable modulation at default, which means enable the field
1243 LOW(GPIO_SSC_DOUT);
1244
1245 // Give it a bit of time for the resonant antenna to settle.
1246 SpinDelay(30);
1247
1248 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1249 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1250
1251 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1252 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1253 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1254
1255 // Disable timer during configuration
1256 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1257
1258 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1259 // external trigger rising edge, load RA on falling edge of TIOA.
1260 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1261
1262 | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
1263
1264 // Enable and reset counters
1265 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1266 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1267
1268 // Reset the received frame, frame count and timing info
1269 frame_count = 0;
1270 response = 0;
1271 lastbit = 1;
1272 bStop = false;
1273
1274 reset_sof = 1;
1275 t_wait = 200;
1276
1277 while (!bStop && !BUTTON_PRESS()) {
1278 // Watchdog hit
1279 WDT_HIT();
1280
1281 // Check if frame was captured and store it
1282 if (rxlen > 0) {
1283 frame_count++;
1284 if (!bQuiet) {
1285 if (!LogTraceHitag(rx, rxlen, response, 0, false)) {
1286 DbpString("Trace full");
1287 if (bQuitTraceFull) {
1288 break;
1289 } else {
1290 bQuiet = true;
1291 }
1292 }
1293 }
1294 }
1295
1296 // By default reset the transmission buffer
1297 tx = txbuf;
1298 txlen = 0;
1299
1300 if (rxlen == 0) {
1301 //start authentication
1302 txlen = 5;
1303 memcpy(tx, "\xc0", nbytes(txlen));
1304 tag.pstate = READY;
1305 tag.tstate = NO_OP;
1306 } else if (tag.pstate != SELECTED) {
1307 if (hitagS_handle_tag_auth(htf, key,NrAr,rx, rxlen, tx, &txlen) == -1)
1308 bStop = !false;
1309 }
1310 if (tag.pstate == SELECTED && tag.tstate == NO_OP && rxlen > 0) {
1311 //send read request
1312 tag.tstate = READING_PAGE;
1313 txlen = 20;
1314 crc = CRC_PRESET;
1315 tx[0] = 0xc0 + (sendNum / 16);
1316 calc_crc(&crc, tx[0], 8);
1317 calc_crc(&crc, 0x00 + ((sendNum % 16) * 16), 4);
1318 tx[1] = 0x00 + ((sendNum % 16) * 16) + (crc / 16);
1319 tx[2] = 0x00 + (crc % 16) * 16;
1320 } else if (tag.pstate == SELECTED && tag.tstate == READING_PAGE
1321 && rxlen > 0) {
1322 //save received data
1323 z = 0;
1324 for (i = 0; i < 5; i++) {
1325 for (j = 0; j < 8; j++) {
1326 response_bit[z] = 0;
1327 if ((rx[i] & ((mask << 7) >> j)) != 0)
1328 response_bit[z] = 1;
1329 z++;
1330 }
1331 }
1332 k = 0;
1333 for (i = 4; i < 36; i++) {
1334 pageData[k] = response_bit[i];
1335 k++;
1336 }
1337 for (i = 0; i < 4; i++)
1338 tag.pages[sendNum / 4][sendNum % 4] = 0x0;
1339 for (i = 0; i < 4; i++) {
1340 tag.pages[sendNum / 4][sendNum % 4] += ((pageData[i * 8] << 7)
1341 | (pageData[1 + (i * 8)] << 6)
1342 | (pageData[2 + (i * 8)] << 5)
1343 | (pageData[3 + (i * 8)] << 4)
1344 | (pageData[4 + (i * 8)] << 3)
1345 | (pageData[5 + (i * 8)] << 2)
1346 | (pageData[6 + (i * 8)] << 1) | pageData[7 + (i * 8)])
1347 << (i * 8);
1348 }
1349 if (tag.auth && tag.LKP && sendNum == 1) {
1350 Dbprintf("Page[%2d]: %02X %02X %02X %02X", sendNum, pwdh0,
1351 (tag.pages[sendNum / 4][sendNum % 4] >> 16) & 0xff,
1352 (tag.pages[sendNum / 4][sendNum % 4] >> 8) & 0xff,
1353 tag.pages[sendNum / 4][sendNum % 4] & 0xff);
1354 } else {
1355 Dbprintf("Page[%2d]: %02X %02X %02X %02X", sendNum,
1356 (tag.pages[sendNum / 4][sendNum % 4] >> 24) & 0xff,
1357 (tag.pages[sendNum / 4][sendNum % 4] >> 16) & 0xff,
1358 (tag.pages[sendNum / 4][sendNum % 4] >> 8) & 0xff,
1359 tag.pages[sendNum / 4][sendNum % 4] & 0xff);
1360 }
1361
1362 sendNum++;
1363 //display key and password if possible
1364 if (sendNum == 2 && tag.auth == 1 && tag.LKP) {
1365 if (htf == 02) { //RHTS_KEY
1366 Dbprintf("Page[ 2]: %02X %02X %02X %02X",
1367 (byte_t)(key >> 8) & 0xff,
1368 (byte_t) key & 0xff, pwdl1, pwdl0);
1369 Dbprintf("Page[ 3]: %02X %02X %02X %02X",
1370 (byte_t)(key >> 40) & 0xff,
1371 (byte_t)(key >> 32) & 0xff,
1372 (byte_t)(key >> 24) & 0xff,
1373 (byte_t)(key >> 16) & 0xff);
1374 } else {
1375 //if the authentication is done with a challenge the key and password are unknown
1376 Dbprintf("Page[ 2]: __ __ __ __");
1377 Dbprintf("Page[ 3]: __ __ __ __");
1378 }
1379 }
1380
1381 txlen = 20;
1382 crc = CRC_PRESET;
1383 tx[0] = 0xc0 + (sendNum / 16);
1384 calc_crc(&crc, tx[0], 8);
1385 calc_crc(&crc, 0x00 + ((sendNum % 16) * 16), 4);
1386 tx[1] = 0x00 + ((sendNum % 16) * 16) + (crc / 16);
1387 tx[2] = 0x00 + (crc % 16) * 16;
1388 if (sendNum >= tag.max_page) {
1389 bStop = !false;
1390 }
1391 }
1392
1393 // Send and store the reader command
1394 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1395 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1396
1397 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1398 // Since the clock counts since the last falling edge, a 'one' means that the
1399 // falling edge occured halfway the period. with respect to this falling edge,
1400 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1401 // All timer values are in terms of T0 units
1402
1403 while (AT91C_BASE_TC0->TC_CV
1404 < T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit)))
1405 ;
1406
1407 // Transmit the reader frame
1408 hitag_reader_send_frame(tx, txlen);
1409
1410 // Enable and reset external trigger in timer for capturing future frames
1411 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1412
1413 // Add transmitted frame to total count
1414 if (txlen > 0) {
1415 frame_count++;
1416 if (!bQuiet) {
1417 // Store the frame in the trace
1418 if (!LogTraceHitag(tx, txlen, HITAG_T_WAIT_2, 0, true)) {
1419 if (bQuitTraceFull) {
1420 DbpString("Trace full");
1421 break;
1422 } else {
1423 bQuiet = true;
1424 }
1425 }
1426 }
1427 }
1428
1429 // Reset values for receiving frames
1430 memset(rx, 0x00, sizeof(rx));
1431 rxlen = 0;
1432 lastbit = 1;
1433 bSkip = true;
1434 tag_sof = reset_sof;
1435 response = 0;
1436
1437 // Receive frame, watch for at most T0*EOF periods
1438 while (AT91C_BASE_TC1->TC_CV < T0 * HITAG_T_WAIT_MAX) {
1439 // Check if falling edge in tag modulation is detected
1440 if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1441 // Retrieve the new timing values
1442 int ra = (AT91C_BASE_TC1->TC_RA / T0);
1443
1444 // Reset timer every frame, we have to capture the last edge for timing
1445 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
1446
1447 LED_B_ON();
1448
1449 // Capture tag frame (manchester decoding using only falling edges)
1450 if (ra >= HITAG_T_EOF) {
1451 if (rxlen != 0) {
1452 //DbpString("wierd1?");
1453 }
1454 // Capture the T0 periods that have passed since last communication or field drop (reset)
1455 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
1456 response = ra - HITAG_T_TAG_HALF_PERIOD;
1457 } else if (ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
1458 // Manchester coding example |-_|_-|-_| (101)
1459 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1460 rxlen++;
1461 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1462 rxlen++;
1463 } else if (ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
1464 // Manchester coding example |_-|...|_-|-_| (0...01)
1465 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1466 rxlen++;
1467 // We have to skip this half period at start and add the 'one' the second time
1468 if (!bSkip) {
1469 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1470 rxlen++;
1471 }
1472 lastbit = !lastbit;
1473 bSkip = !bSkip;
1474 } else if (ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
1475 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
1476 if (tag_sof) {
1477 // Ignore bits that are transmitted during SOF
1478 tag_sof--;
1479 } else {
1480 // bit is same as last bit
1481 rx[rxlen / 8] |= lastbit << (7 - (rxlen % 8));
1482 rxlen++;
1483 }
1484 } else {
1485 // Ignore wierd value, is to small to mean anything
1486 }
1487 }
1488
1489 // We can break this loop if we received the last bit from a frame
1490 if (AT91C_BASE_TC1->TC_CV > T0 * HITAG_T_EOF) {
1491 if (rxlen > 0)
1492 break;
1493 }
1494 }
1495 }
1496 end=false;
1497 LED_B_OFF();
1498 LED_D_OFF();
1499 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1500 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1501 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1502 cmd_send(CMD_ACK, bSuccessful, 0, 0, 0, 0);
1503 }
1504
1505 /*
1506 * Authenticates to the Tag with the given Key or Challenge.
1507 * Writes the given 32Bit data into page_
1508 */
1509 void WritePageHitagS(hitag_function htf, hitag_data* htd,int page_) {
1510 int frame_count;
1511 int response;
1512 byte_t rx[HITAG_FRAME_LEN];
1513 size_t rxlen = 0;
1514 byte_t txbuf[HITAG_FRAME_LEN];
1515 byte_t* tx = txbuf;
1516 size_t txlen = 0;
1517 int lastbit;
1518 bool bSkip;
1519 int reset_sof;
1520 int tag_sof;
1521 int t_wait = HITAG_T_WAIT_MAX;
1522 bool bStop;
1523 bool bQuitTraceFull = false;
1524 int page = page_;
1525 unsigned char crc;
1526 byte_t data[4]= {0,0,0,0};
1527
1528 //read given key/challenge, the page and the data
1529 byte_t NrAr_[8];
1530 uint64_t key=0;
1531 uint64_t NrAr=0;
1532 byte_t key_[6];
1533 switch(htf) {
1534 case 03: { //WHTS_CHALLENGE
1535 memcpy(data,htd->auth.data,4);
1536 DbpString("Authenticating using nr,ar pair:");
1537 memcpy(NrAr_,htd->auth.NrAr,8);
1538 Dbhexdump(8,NrAr_,false);
1539 NrAr=NrAr_[7] | ((uint64_t)NrAr_[6]) << 8 | ((uint64_t)NrAr_[5]) << 16 | ((uint64_t)NrAr_[4]) << 24 | ((uint64_t)NrAr_[3]) << 32 |
1540 ((uint64_t)NrAr_[2]) << 40| ((uint64_t)NrAr_[1]) << 48 | ((uint64_t)NrAr_[0]) << 56;
1541 } break;
1542 case 04: { //WHTS_KEY
1543 memcpy(data,htd->crypto.data,4);
1544 DbpString("Authenticating using key:");
1545 memcpy(key_,htd->crypto.key,6);
1546 Dbhexdump(6,key_,false);
1547 key=key_[5] | ((uint64_t)key_[4]) << 8 | ((uint64_t)key_[3]) << 16 | ((uint64_t)key_[2]) << 24 | ((uint64_t)key_[1]) << 32 | ((uint64_t)key_[0]) << 40;
1548 } break;
1549 default: {
1550 Dbprintf("Error , unknown function: %d",htf);
1551 return;
1552 } break;
1553 }
1554
1555 Dbprintf("Page: %d",page_);
1556 Dbprintf("DATA: %02X %02X %02X %02X", data[0], data[1], data[2], data[3]);
1557 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1558 // Reset the return status
1559 bSuccessful = false;
1560
1561 tag.pstate = READY;
1562 tag.tstate = NO_OP;
1563
1564 // Clean up trace and prepare it for storing frames
1565 set_tracing(TRUE);
1566 clear_trace();
1567
1568 bQuiet = false;
1569 bQuitTraceFull = true;
1570
1571 LED_D_ON();
1572
1573 // Configure output and enable pin that is connected to the FPGA (for modulating)
1574 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1575 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1576
1577 // Set fpga in edge detect with reader field, we can modulate as reader now
1578 FpgaWriteConfWord(
1579 FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1580
1581 // Set Frequency divisor which will drive the FPGA and analog mux selection
1582 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1583 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1584 RELAY_OFF();
1585
1586 // Disable modulation at default, which means enable the field
1587 LOW(GPIO_SSC_DOUT);
1588
1589 // Give it a bit of time for the resonant antenna to settle.
1590 SpinDelay(30);
1591
1592 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1593 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1594
1595 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1596 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1597 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1598
1599 // Disable timer during configuration
1600 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1601
1602 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1603 // external trigger rising edge, load RA on falling edge of TIOA.
1604 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1605 | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG
1606 | AT91C_TC_LDRA_FALLING;
1607
1608 // Enable and reset counters
1609 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1610 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1611
1612 // Reset the received frame, frame count and timing info
1613 frame_count = 0;
1614 response = 0;
1615 lastbit = 1;
1616 bStop = false;
1617
1618 reset_sof = 1;
1619 t_wait = 200;
1620
1621 while (!bStop && !BUTTON_PRESS()) {
1622 // Watchdog hit
1623 WDT_HIT();
1624
1625 // Check if frame was captured and store it
1626 if (rxlen > 0) {
1627 frame_count++;
1628 if (!bQuiet) {
1629 if (!LogTraceHitag(rx, rxlen, response, 0, false)) {
1630 DbpString("Trace full");
1631 if (bQuitTraceFull) {
1632 break;
1633 } else {
1634 bQuiet = true;
1635 }
1636 }
1637 }
1638 }
1639
1640 //check for valid input
1641 if (page == 0) {
1642 Dbprintf(
1643 "usage: lf hitag writer [03 | 04] [CHALLENGE | KEY] [page] [byte0] [byte1] [byte2] [byte3]");
1644 bStop = !false;
1645 }
1646
1647 // By default reset the transmission buffer
1648 tx = txbuf;
1649 txlen = 0;
1650
1651 if (rxlen == 0 && tag.tstate == WRITING_PAGE_ACK) {
1652 //no write access on this page
1653 Dbprintf("no write access on page %d", page_);
1654 bStop = !false;
1655 } else if (rxlen == 0 && tag.tstate != WRITING_PAGE_DATA) {
1656 //start the authetication
1657 txlen = 5;
1658 memcpy(tx, "\xc0", nbytes(txlen));
1659 tag.pstate = READY;
1660 tag.tstate = NO_OP;
1661 } else if (tag.pstate != SELECTED) {
1662 //try to authenticate with the given key or challenge
1663 if (hitagS_handle_tag_auth(htf,key,NrAr,rx, rxlen, tx, &txlen) == -1)
1664 bStop = !false;
1665 }
1666 if (tag.pstate == SELECTED && tag.tstate == NO_OP && rxlen > 0) {
1667 //check if the given page exists
1668 if (page > tag.max_page) {
1669 Dbprintf("page number too big");
1670 bStop = !false;
1671 }
1672 //ask Tag for write permission
1673 tag.tstate = WRITING_PAGE_ACK;
1674 txlen = 20;
1675 crc = CRC_PRESET;
1676 tx[0] = 0x90 + (page / 16);
1677 calc_crc(&crc, tx[0], 8);
1678 calc_crc(&crc, 0x00 + ((page % 16) * 16), 4);
1679 tx[1] = 0x00 + ((page % 16) * 16) + (crc / 16);
1680 tx[2] = 0x00 + (crc % 16) * 16;
1681 } else if (tag.pstate == SELECTED && tag.tstate == WRITING_PAGE_ACK
1682 && rxlen == 6 && rx[0] == 0xf4) {
1683 //ACK recieved to write the page. send data
1684 tag.tstate = WRITING_PAGE_DATA;
1685 txlen = 40;
1686 crc = CRC_PRESET;
1687 calc_crc(&crc, data[3], 8);
1688 calc_crc(&crc, data[2], 8);
1689 calc_crc(&crc, data[1], 8);
1690 calc_crc(&crc, data[0], 8);
1691 tx[0] = data[3];
1692 tx[1] = data[2];
1693 tx[2] = data[1];
1694 tx[3] = data[0];
1695 tx[4] = crc;
1696 } else if (tag.pstate == SELECTED && tag.tstate == WRITING_PAGE_DATA
1697 && rxlen == 6 && rx[0] == 0xf4) {
1698 //received ACK
1699 Dbprintf("Successful!");
1700 bStop = !false;
1701 }
1702
1703 // Send and store the reader command
1704 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1705 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1706
1707 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1708 // Since the clock counts since the last falling edge, a 'one' means that the
1709 // falling edge occured halfway the period. with respect to this falling edge,
1710 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1711 // All timer values are in terms of T0 units
1712
1713 while (AT91C_BASE_TC0->TC_CV
1714 < T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit)))
1715 ;
1716
1717 // Transmit the reader frame
1718 hitag_reader_send_frame(tx, txlen);
1719
1720 // Enable and reset external trigger in timer for capturing future frames
1721 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1722
1723 // Add transmitted frame to total count
1724 if (txlen > 0) {
1725 frame_count++;
1726 if (!bQuiet) {
1727 // Store the frame in the trace
1728 if (!LogTraceHitag(tx, txlen, HITAG_T_WAIT_2, 0, true)) {
1729 if (bQuitTraceFull) {
1730 DbpString("Trace full");
1731 break;
1732 } else {
1733 bQuiet = true;
1734 }
1735 }
1736 }
1737 }
1738
1739 // Reset values for receiving frames
1740 memset(rx, 0x00, sizeof(rx));
1741 rxlen = 0;
1742 lastbit = 1;
1743 bSkip = true;
1744 tag_sof = reset_sof;
1745 response = 0;
1746
1747 // Receive frame, watch for at most T0*EOF periods
1748 while (AT91C_BASE_TC1->TC_CV < T0 * HITAG_T_WAIT_MAX) {
1749 // Check if falling edge in tag modulation is detected
1750 if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1751 // Retrieve the new timing values
1752 int ra = (AT91C_BASE_TC1->TC_RA / T0);
1753
1754 // Reset timer every frame, we have to capture the last edge for timing
1755 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
1756
1757 LED_B_ON();
1758
1759 // Capture tag frame (manchester decoding using only falling edges)
1760 if (ra >= HITAG_T_EOF) {
1761 if (rxlen != 0) {
1762 //DbpString("wierd1?");
1763 }
1764 // Capture the T0 periods that have passed since last communication or field drop (reset)
1765 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
1766 response = ra - HITAG_T_TAG_HALF_PERIOD;
1767 } else if (ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
1768 // Manchester coding example |-_|_-|-_| (101)
1769 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1770 rxlen++;
1771 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1772 rxlen++;
1773 } else if (ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
1774 // Manchester coding example |_-|...|_-|-_| (0...01)
1775 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1776 rxlen++;
1777 // We have to skip this half period at start and add the 'one' the second time
1778 if (!bSkip) {
1779 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1780 rxlen++;
1781 }
1782 lastbit = !lastbit;
1783 bSkip = !bSkip;
1784 } else if (ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
1785 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
1786 if (tag_sof) {
1787 // Ignore bits that are transmitted during SOF
1788 tag_sof--;
1789 } else {
1790 // bit is same as last bit
1791 rx[rxlen / 8] |= lastbit << (7 - (rxlen % 8));
1792 rxlen++;
1793 }
1794 } else {
1795 // Ignore wierd value, is to small to mean anything
1796 }
1797 }
1798
1799 // We can break this loop if we received the last bit from a frame
1800 if (AT91C_BASE_TC1->TC_CV > T0 * HITAG_T_EOF) {
1801 if (rxlen > 0)
1802 break;
1803 }
1804 }
1805 }
1806 end=false;
1807 LED_B_OFF();
1808 LED_D_OFF();
1809 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1810 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1811 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1812 cmd_send(CMD_ACK, bSuccessful, 0, 0, 0, 0);
1813 }
1814
1815 /*
1816 * Tries to authenticate to a Hitag S Transponder with the given challenges from a .cc file.
1817 * Displays all Challenges that failed.
1818 * When collecting Challenges to break the key it is possible that some data
1819 * is not received correctly due to Antenna problems. This function
1820 * detects these challenges.
1821 */
1822 void check_challenges(bool file_given, byte_t* data) {
1823 int i, j, z, k;
1824 byte_t uid_byte[4];
1825 int frame_count;
1826 int response;
1827 byte_t rx[HITAG_FRAME_LEN];
1828 byte_t unlocker[60][8];
1829 int u1 = 0;
1830 size_t rxlen = 0;
1831 byte_t txbuf[HITAG_FRAME_LEN];
1832 byte_t* tx = txbuf;
1833 size_t txlen = 0;
1834 int lastbit;
1835 bool bSkip;
1836 int reset_sof;
1837 int tag_sof;
1838 int t_wait = HITAG_T_WAIT_MAX;
1839 int STATE = 0;
1840 bool bStop;
1841 bool bQuitTraceFull = false;
1842 int response_bit[200];
1843 unsigned char mask = 1;
1844 unsigned char uid[32];
1845 unsigned char crc;
1846
1847 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1848 // Reset the return status
1849 bSuccessful = false;
1850
1851 // Clean up trace and prepare it for storing frames
1852 set_tracing(TRUE);
1853 clear_trace();
1854
1855 bQuiet = false;
1856 bQuitTraceFull = true;
1857
1858 LED_D_ON();
1859
1860 // Configure output and enable pin that is connected to the FPGA (for modulating)
1861 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1862 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1863
1864 // Set fpga in edge detect with reader field, we can modulate as reader now
1865 FpgaWriteConfWord(
1866 FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1867
1868 // Set Frequency divisor which will drive the FPGA and analog mux selection
1869 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1870 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1871 RELAY_OFF();
1872
1873 // Disable modulation at default, which means enable the field
1874 LOW(GPIO_SSC_DOUT);
1875
1876 // Give it a bit of time for the resonant antenna to settle.
1877 SpinDelay(30);
1878
1879 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1880 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1881
1882 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1883 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1884 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1885
1886 // Disable timer during configuration
1887 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1888
1889 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1890 // external trigger rising edge, load RA on falling edge of TIOA.
1891 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1892
1893 | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
1894
1895 // Enable and reset counters
1896 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1897 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1898
1899 // Reset the received frame, frame count and timing info
1900 frame_count = 0;
1901 response = 0;
1902 lastbit = 1;
1903 bStop = false;
1904
1905 reset_sof = 1;
1906 t_wait = 200;
1907
1908 if (file_given) {
1909 DbpString("Loading challenges...");
1910 memcpy((byte_t*)unlocker,data,60*8);
1911 }
1912
1913 while (file_given && !bStop && !BUTTON_PRESS()) {
1914 // Watchdog hit
1915 WDT_HIT();
1916
1917 // Check if frame was captured and store it
1918 if (rxlen > 0) {
1919 frame_count++;
1920 if (!bQuiet) {
1921 if (!LogTraceHitag(rx, rxlen, response, 0, false)) {
1922 DbpString("Trace full");
1923 if (bQuitTraceFull) {
1924 break;
1925 } else {
1926 bQuiet = true;
1927 }
1928 }
1929 }
1930 }
1931
1932 tx = txbuf;
1933 txlen = 0;
1934 if (rxlen == 0) {
1935 if (STATE == 2)
1936 // challenge failed
1937 Dbprintf("Challenge failed: %02X %02X %02X %02X %02X %02X %02X %02X",
1938 unlocker[u1 - 1][0], unlocker[u1 - 1][1],
1939 unlocker[u1 - 1][2], unlocker[u1 - 1][3],
1940 unlocker[u1 - 1][4], unlocker[u1 - 1][5],
1941 unlocker[u1 - 1][6], unlocker[u1 - 1][7]);
1942 STATE = 0;
1943 txlen = 5;
1944 //start new authentication
1945 memcpy(tx, "\xc0", nbytes(txlen));
1946 } else if (rxlen >= 67 && STATE == 0) {
1947 //received uid
1948 z = 0;
1949 for (i = 0; i < 10; i++) {
1950 for (j = 0; j < 8; j++) {
1951 response_bit[z] = 0;
1952 if ((rx[i] & ((mask << 7) >> j)) != 0)
1953 response_bit[z] = 1;
1954 z++;
1955 }
1956 }
1957 k = 0;
1958 for (i = 5; i < z; i += 2) {
1959 uid[k] = response_bit[i];
1960 k++;
1961 if (k > 31)
1962 break;
1963 }
1964 uid_byte[0] = (uid[0] << 7) | (uid[1] << 6) | (uid[2] << 5)
1965 | (uid[3] << 4) | (uid[4] << 3) | (uid[5] << 2)
1966 | (uid[6] << 1) | uid[7];
1967 uid_byte[1] = (uid[8] << 7) | (uid[9] << 6) | (uid[10] << 5)
1968 | (uid[11] << 4) | (uid[12] << 3) | (uid[13] << 2)
1969 | (uid[14] << 1) | uid[15];
1970 uid_byte[2] = (uid[16] << 7) | (uid[17] << 6) | (uid[18] << 5)
1971 | (uid[19] << 4) | (uid[20] << 3) | (uid[21] << 2)
1972 | (uid[22] << 1) | uid[23];
1973 uid_byte[3] = (uid[24] << 7) | (uid[25] << 6) | (uid[26] << 5)
1974 | (uid[27] << 4) | (uid[28] << 3) | (uid[29] << 2)
1975 | (uid[30] << 1) | uid[31];
1976 //Dbhexdump(10, rx, rxlen);
1977 STATE = 1;
1978 txlen = 45;
1979 crc = CRC_PRESET;
1980 calc_crc(&crc, 0x00, 5);
1981 calc_crc(&crc, uid_byte[0], 8);
1982 calc_crc(&crc, uid_byte[1], 8);
1983 calc_crc(&crc, uid_byte[2], 8);
1984 calc_crc(&crc, uid_byte[3], 8);
1985 for (i = 0; i < 100; i++) {
1986 response_bit[i] = 0;
1987 }
1988 for (i = 0; i < 5; i++) {
1989 response_bit[i] = 0;
1990 }
1991 for (i = 5; i < 37; i++) {
1992 response_bit[i] = uid[i - 5];
1993 }
1994 for (j = 0; j < 8; j++) {
1995 response_bit[i] = 0;
1996 if ((crc & ((mask << 7) >> j)) != 0)
1997 response_bit[i] = 1;
1998 i++;
1999 }
2000 k = 0;
2001 for (i = 0; i < 6; i++) {
2002 tx[i] = (response_bit[k] << 7) | (response_bit[k + 1] << 6)
2003 | (response_bit[k + 2] << 5)
2004 | (response_bit[k + 3] << 4)
2005 | (response_bit[k + 4] << 3)
2006 | (response_bit[k + 5] << 2)
2007 | (response_bit[k + 6] << 1) | response_bit[k + 7];
2008 k += 8;
2009 }
2010
2011 } else if (STATE == 1 && rxlen == 44) {
2012 //received configuration
2013 STATE = 2;
2014 z = 0;
2015 for (i = 0; i < 6; i++) {
2016 for (j = 0; j < 8; j++) {
2017 response_bit[z] = 0;
2018 if ((rx[i] & ((mask << 7) >> j)) != 0)
2019 response_bit[z] = 1;
2020 z++;
2021 }
2022 }
2023 txlen = 64;
2024
2025 if (u1 >= (sizeof(unlocker) / sizeof(unlocker[0])))
2026 bStop = !false;
2027 for (i = 0; i < 8; i++)
2028 tx[i] = unlocker[u1][i];
2029 u1++;
2030
2031 } else if (STATE == 2 && rxlen >= 44) {
2032 STATE = 0;
2033 }
2034
2035 // Send and store the reader command
2036 // Disable timer 1 with external trigger to avoid triggers during our own modulation
2037 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
2038
2039 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
2040 // Since the clock counts since the last falling edge, a 'one' means that the
2041 // falling edge occured halfway the period. with respect to this falling edge,
2042 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
2043 // All timer values are in terms of T0 units
2044
2045 while (AT91C_BASE_TC0->TC_CV
2046 < T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit)))
2047 ;
2048
2049 // Transmit the reader frame
2050 hitag_reader_send_frame(tx, txlen);
2051
2052 // Enable and reset external trigger in timer for capturing future frames
2053 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
2054
2055 // Add transmitted frame to total count
2056 if (txlen > 0) {
2057 frame_count++;
2058 if (!bQuiet) {
2059 // Store the frame in the trace
2060 if (!LogTraceHitag(tx, txlen, HITAG_T_WAIT_2, 0, true)) {
2061 if (bQuitTraceFull) {
2062 DbpString("Trace full");
2063 break;
2064 } else {
2065 bQuiet = true;
2066 }
2067 }
2068 }
2069 }
2070
2071 // Reset values for receiving frames
2072 memset(rx, 0x00, sizeof(rx));
2073 rxlen = 0;
2074 lastbit = 1;
2075 bSkip = true;
2076 tag_sof = reset_sof;
2077 response = 0;
2078
2079 // Receive frame, watch for at most T0*EOF periods
2080 while (AT91C_BASE_TC1->TC_CV < T0 * HITAG_T_WAIT_MAX) {
2081 // Check if falling edge in tag modulation is detected
2082 if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
2083 // Retrieve the new timing values
2084 int ra = (AT91C_BASE_TC1->TC_RA / T0);
2085
2086 // Reset timer every frame, we have to capture the last edge for timing
2087 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
2088
2089 LED_B_ON();
2090
2091 // Capture tag frame (manchester decoding using only falling edges)
2092 if (ra >= HITAG_T_EOF) {
2093 if (rxlen != 0) {
2094 //DbpString("wierd1?");
2095 }
2096 // Capture the T0 periods that have passed since last communication or field drop (reset)
2097 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
2098 response = ra - HITAG_T_TAG_HALF_PERIOD;
2099 } else if (ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
2100 // Manchester coding example |-_|_-|-_| (101)
2101 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
2102 rxlen++;
2103 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
2104 rxlen++;
2105 } else if (ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
2106 // Manchester coding example |_-|...|_-|-_| (0...01)
2107 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
2108 rxlen++;
2109 // We have to skip this half period at start and add the 'one' the second time
2110 if (!bSkip) {
2111 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
2112 rxlen++;
2113 }
2114 lastbit = !lastbit;
2115 bSkip = !bSkip;
2116 } else if (ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
2117 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
2118 if (tag_sof) {
2119 // Ignore bits that are transmitted during SOF
2120 tag_sof--;
2121 } else {
2122 // bit is same as last bit
2123 rx[rxlen / 8] |= lastbit << (7 - (rxlen % 8));
2124 rxlen++;
2125 }
2126 } else {
2127 // Ignore wierd value, is to small to mean anything
2128 }
2129 }
2130
2131 // We can break this loop if we received the last bit from a frame
2132 if (AT91C_BASE_TC1->TC_CV > T0 * HITAG_T_EOF) {
2133 if (rxlen > 0)
2134 break;
2135 }
2136 }
2137 }
2138 LED_B_OFF();
2139 LED_D_OFF();
2140 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
2141 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
2142 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2143 cmd_send(CMD_ACK, bSuccessful, 0, 0, 0, 0);
2144 }
2145
2146
2147
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