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1 /*
2 * LEGIC RF simulation code
3 *
4 * (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
5 */
6
7 #include <proxmark3.h>
8
9 #include "apps.h"
10 #include "legicrf.h"
11 #include "unistd.h"
12 #include "stdint.h"
13
14 #include "legic_prng.h"
15 #include "crc.h"
16
17 static struct legic_frame {
18 int bits;
19 uint32_t data;
20 } current_frame;
21
22 static crc_t legic_crc;
23
24 AT91PS_TC timer;
25
26 static void setup_timer(void)
27 {
28 /* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
29 * this it won't be terribly accurate but should be good enough.
30 */
31 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
32 timer = AT91C_BASE_TC1;
33 timer->TC_CCR = AT91C_TC_CLKDIS;
34 timer->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK3;
35 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
36
37 /* At TIMER_CLOCK3 (MCK/32) */
38 #define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */
39 #define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
40 #define RWD_TIME_PAUSE 30 /* 20us */
41 #define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
42 #define TAG_TIME_BIT 150 /* 100us for every bit */
43 #define TAG_TIME_WAIT 490 /* time from RWD frame end to tag frame start, experimentally determined */
44
45 }
46
47 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
48
49 /* Send a frame in reader mode, the FPGA must have been set up by
50 * LegicRfReader
51 */
52 static void frame_send_rwd(uint32_t data, int bits)
53 {
54 /* Start clock */
55 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
57
58 int i;
59 for(i=0; i<bits; i++) {
60 int starttime = timer->TC_CV;
61 int pause_end = starttime + RWD_TIME_PAUSE, bit_end;
62 int bit = data & 1;
63 data = data >> 1;
64
65 if(bit ^ legic_prng_get_bit()) {
66 bit_end = starttime + RWD_TIME_1;
67 } else {
68 bit_end = starttime + RWD_TIME_0;
69 }
70
71 /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is
72 * RWD_TIME_x, where x is the bit to be transmitted */
73 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
74 while(timer->TC_CV < pause_end) ;
75 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
76 legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */
77
78 while(timer->TC_CV < bit_end) ;
79 }
80
81 {
82 /* One final pause to mark the end of the frame */
83 int pause_end = timer->TC_CV + RWD_TIME_PAUSE;
84 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
85 while(timer->TC_CV < pause_end) ;
86 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
87 }
88
89 /* Reset the timer, to measure time until the start of the tag frame */
90 timer->TC_CCR = AT91C_TC_SWTRG;
91 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
92 }
93
94 /* Receive a frame from the card in reader emulation mode, the FPGA and
95 * timer must have been set up by LegicRfReader and frame_send_rwd.
96 *
97 * The LEGIC RF protocol from card to reader does not include explicit
98 * frame start/stop information or length information. The reader must
99 * know beforehand how many bits it wants to receive. (Notably: a card
100 * sending a stream of 0-bits is indistinguishable from no card present.)
101 *
102 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
103 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
104 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
105 * for edges. Count the edges in each bit interval. If they are approximately
106 * 0 this was a 0-bit, if they are approximately equal to the number of edges
107 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
108 * timer that's still running from frame_send_rwd in order to get a synchronization
109 * with the frame that we just sent.
110 *
111 * FIXME: Because we're relying on the hysteresis to just do the right thing
112 * the range is severely reduced (and you'll probably also need a good antenna).
113 * So this should be fixed some time in the future for a proper receiver.
114 */
115 static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt)
116 {
117 uint32_t the_bit = 1; /* Use a bitmask to save on shifts */
118 uint32_t data=0;
119 int i, old_level=0, edges=0;
120 int next_bit_at = TAG_TIME_WAIT;
121
122
123 if(bits > 16)
124 bits = 16;
125
126 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
127 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
128
129 /* we have some time now, precompute the cipher
130 * since we cannot compute it on the fly while reading */
131 legic_prng_forward(2);
132
133 if(crypt)
134 {
135 for(i=0; i<bits; i++) {
136 data |= legic_prng_get_bit() << i;
137 legic_prng_forward(1);
138 }
139 }
140
141 while(timer->TC_CV < next_bit_at) ;
142
143 next_bit_at += TAG_TIME_BIT;
144
145 for(i=0; i<bits; i++) {
146 edges = 0;
147
148 while(timer->TC_CV < next_bit_at) {
149 int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
150 if(level != old_level)
151 edges++;
152 old_level = level;
153 }
154 next_bit_at += TAG_TIME_BIT;
155
156 if(edges > 20 && edges < 60) { /* expected are 42 edges */
157 data ^= the_bit;
158 }
159
160 the_bit <<= 1;
161 }
162
163 f->data = data;
164 f->bits = bits;
165
166 /* Reset the timer, to synchronize the next frame */
167 timer->TC_CCR = AT91C_TC_SWTRG;
168 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
169 }
170
171 static void frame_clean(struct legic_frame * const f)
172 {
173 f->data = 0;
174 f->bits = 0;
175 }
176
177 static uint32_t perform_setup_phase_rwd(int iv)
178 {
179
180 /* Switch on carrier and let the tag charge for 1ms */
181 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
182 SpinDelay(1);
183
184 legic_prng_init(0); /* no keystream yet */
185 frame_send_rwd(iv, 7);
186 legic_prng_init(iv);
187
188 frame_clean(&current_frame);
189 frame_receive_rwd(&current_frame, 6, 1);
190 legic_prng_forward(1); /* we wait anyways */
191 while(timer->TC_CV < 387) ; /* ~ 258us */
192 frame_send_rwd(0x19, 6);
193
194 return current_frame.data;
195 }
196
197 static void LegicCommonInit(void) {
198 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
199 FpgaSetupSsc();
200 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
201
202 /* Bitbang the transmitter */
203 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
204 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
205 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
206
207 setup_timer();
208
209 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
210 }
211
212 static void switch_off_tag_rwd(void)
213 {
214 /* Switch off carrier, make sure tag is reset */
215 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
216 SpinDelay(10);
217
218 WDT_HIT();
219 }
220 /* calculate crc for a legic command */
221 static int LegicCRC(int byte_index, int value, int cmd_sz) {
222 crc_clear(&legic_crc);
223 crc_update(&legic_crc, 1, 1); /* CMD_READ */
224 crc_update(&legic_crc, byte_index, cmd_sz-1);
225 crc_update(&legic_crc, value, 8);
226 return crc_finish(&legic_crc);
227 }
228
229 int legic_read_byte(int byte_index, int cmd_sz) {
230 int byte;
231
232 legic_prng_forward(4); /* we wait anyways */
233 while(timer->TC_CV < 387) ; /* ~ 258us + 100us*delay */
234
235 frame_send_rwd(1 | (byte_index << 1), cmd_sz);
236 frame_clean(&current_frame);
237
238 frame_receive_rwd(&current_frame, 12, 1);
239
240 byte = current_frame.data & 0xff;
241 if( LegicCRC(byte_index, byte, cmd_sz) != (current_frame.data >> 8) ) {
242 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", LegicCRC(byte_index, current_frame.data & 0xff, cmd_sz), current_frame.data >> 8);
243 return -1;
244 }
245
246 return byte;
247 }
248
249 /* legic_write_byte() is not included, however it's trivial to implement
250 * and here are some hints on what remains to be done:
251 *
252 * * assemble a write_cmd_frame with crc and send it
253 * * wait until the tag sends back an ACK ('1' bit unencrypted)
254 * * forward the prng based on the timing
255 */
256
257
258 void LegicRfReader(int offset, int bytes) {
259 int byte_index=0, cmd_sz=0, card_sz=0;
260
261 LegicCommonInit();
262
263 memset(BigBuf, 0, 1024);
264
265 DbpString("setting up legic card");
266 uint32_t tag_type = perform_setup_phase_rwd(0x55);
267 switch(tag_type) {
268 case 0x1d:
269 DbpString("MIM 256 card found, reading card ...");
270 cmd_sz = 9;
271 card_sz = 256;
272 break;
273 case 0x3d:
274 DbpString("MIM 1024 card found, reading card ...");
275 cmd_sz = 11;
276 card_sz = 1024;
277 break;
278 default:
279 Dbprintf("Unknown card format: %x",tag_type);
280 switch_off_tag_rwd();
281 return;
282 }
283 if(bytes == -1) {
284 bytes = card_sz;
285 }
286 if(bytes+offset >= card_sz) {
287 bytes = card_sz-offset;
288 }
289
290 switch_off_tag_rwd(); //we lost to mutch time with dprintf
291 perform_setup_phase_rwd(0x55);
292
293 while(byte_index < bytes) {
294 int r = legic_read_byte(byte_index+offset, cmd_sz);
295 if(r == -1) {
296 Dbprintf("aborting");
297 switch_off_tag_rwd();
298 return;
299 }
300 ((uint8_t*)BigBuf)[byte_index] = r;
301 byte_index++;
302 }
303 switch_off_tag_rwd();
304 Dbprintf("Card read, use 'hf legic decode' or 'data hexsamples %d' to view results", (bytes+7) & ~7);
305 }
306
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