fix 'hf mf perso' result feedback (#920)
[proxmark3-svn] / armsrc / fpgaloader.h
1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, April 2006
3 // iZsh <izsh at fail0verflow.com>, 2014
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // Routines to load the FPGA image, and then to configure the FPGA's major
10 // mode once it is configured.
11 //-----------------------------------------------------------------------------
12
13 #ifndef __FPGALOADER_H
14 #define __FPGALOADER_H
15
16 #include <stdint.h>
17 #include <stdbool.h>
18
19 void FpgaSendCommand(uint16_t cmd, uint16_t v);
20 void FpgaWriteConfWord(uint16_t v);
21 void FpgaDownloadAndGo(int bitstream_version);
22 void FpgaSetupSsc(uint16_t mode);
23 void SetupSpi(int mode);
24 bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count);
25 void Fpga_print_status();
26 int FpgaGetCurrent();
27 void FpgaEnableTracing(void);
28 void FpgaDisableTracing(void);
29 #define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
30 #define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
31 void SetAdcMuxFor(uint32_t whichGpio);
32
33 // definitions for multiple FPGA config files support
34 #define FPGA_BITSTREAM_LF 1
35 #define FPGA_BITSTREAM_HF 2
36
37 // Definitions for the FPGA commands.
38 // BOTH
39 #define FPGA_CMD_SET_CONFREG (1<<12)
40 // LF
41 #define FPGA_CMD_SET_DIVISOR (2<<12)
42 #define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD (3<<12)
43
44 // HF
45 #define FPGA_CMD_TRACE_ENABLE (2<<12)
46
47 // Definitions for the FPGA configuration word.
48 // LF
49 #define FPGA_MAJOR_MODE_LF_ADC (0<<6)
50 #define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<6)
51 #define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<6)
52 // HF
53 #define FPGA_MAJOR_MODE_HF_READER (0<<6)
54 #define FPGA_MAJOR_MODE_HF_SIMULATOR (1<<6)
55 #define FPGA_MAJOR_MODE_HF_ISO14443A (2<<6)
56 #define FPGA_MAJOR_MODE_HF_SNOOP (3<<6)
57 #define FPGA_MAJOR_MODE_HF_GET_TRACE (4<<6)
58 // BOTH
59 #define FPGA_MAJOR_MODE_OFF (7<<6)
60
61 // Options for LF_ADC
62 #define FPGA_LF_ADC_READER_FIELD (1<<0)
63
64 // Options for LF_EDGE_DETECT
65 #define FPGA_LF_EDGE_DETECT_READER_FIELD (1<<0)
66 #define FPGA_LF_EDGE_DETECT_TOGGLE_MODE (2<<0)
67
68 // Options for the HF reader
69 #define FPGA_HF_READER_MODE_RECEIVE_IQ (0<<0)
70 #define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE (1<<0)
71 #define FPGA_HF_READER_MODE_RECEIVE_PHASE (2<<0)
72 #define FPGA_HF_READER_MODE_SEND_FULL_MOD (3<<0)
73 #define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD (4<<0)
74 #define FPGA_HF_READER_MODE_SNOOP_IQ (5<<0)
75 #define FPGA_HF_READER_MODE_SNOOP_AMPLITUDE (6<<0)
76 #define FPGA_HF_READER_MODE_SNOOP_PHASE (7<<0)
77 #define FPGA_HF_READER_MODE_SEND_JAM (8<<0)
78
79 #define FPGA_HF_READER_SUBCARRIER_848_KHZ (0<<4)
80 #define FPGA_HF_READER_SUBCARRIER_424_KHZ (1<<4)
81 #define FPGA_HF_READER_SUBCARRIER_212_KHZ (2<<4)
82
83 // Options for the HF simulated tag, how to modulate
84 #define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
85 #define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
86 #define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0)
87 #define FPGA_HF_SIMULATOR_MODULATE_424K (4<<0)
88 #define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5//101
89
90 // Options for ISO14443A
91 #define FPGA_HF_ISO14443A_SNIFFER (0<<0)
92 #define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)
93 #define FPGA_HF_ISO14443A_TAGSIM_MOD (2<<0)
94 #define FPGA_HF_ISO14443A_READER_LISTEN (3<<0)
95 #define FPGA_HF_ISO14443A_READER_MOD (4<<0)
96
97 #endif
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