]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of https://github.com/Proxmark/proxmark3
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19
20
21 /**
22 * Function to do a modulation and then get samples.
23 * @param delay_off
24 * @param period_0
25 * @param period_1
26 * @param command
27 */
28 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
29 {
30
31 int divisor_used = 95; // 125 KHz
32 // see if 'h' was specified
33
34 if (command[strlen((char *) command) - 1] == 'h')
35 divisor_used = 88; // 134.8 KHz
36
37 sample_config sc = { 0,0,1, divisor_used, 0};
38 setSamplingConfig(&sc);
39
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
43 SpinDelay(2500);
44
45 LFSetupFPGAForADC(sc.divisor, 1);
46
47 // And a little more time for the tag to fully power up
48 SpinDelay(2000);
49
50 // now modulate the reader field
51 while(*command != '\0' && *command != ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
53 LED_D_OFF();
54 SpinDelayUs(delay_off);
55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
56
57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
58 LED_D_ON();
59 if(*(command++) == '0')
60 SpinDelayUs(period_0);
61 else
62 SpinDelayUs(period_1);
63 }
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
65 LED_D_OFF();
66 SpinDelayUs(delay_off);
67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
68
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
70
71 // now do the read
72 DoAcquisition_config(false);
73 }
74
75 /* blank r/w tag data stream
76 ...0000000000000000 01111111
77 1010101010101010101010101010101010101010101010101010101010101010
78 0011010010100001
79 01111111
80 101010101010101[0]000...
81
82 [5555fe852c5555555555555555fe0000]
83 */
84 void ReadTItag(void)
85 {
86 // some hardcoded initial params
87 // when we read a TI tag we sample the zerocross line at 2Mhz
88 // TI tags modulate a 1 as 16 cycles of 123.2Khz
89 // TI tags modulate a 0 as 16 cycles of 134.2Khz
90 #define FSAMPLE 2000000
91 #define FREQLO 123200
92 #define FREQHI 134200
93
94 signed char *dest = (signed char *)BigBuf_get_addr();
95 uint16_t n = BigBuf_max_traceLen();
96 // 128 bit shift register [shift3:shift2:shift1:shift0]
97 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
98
99 int i, cycles=0, samples=0;
100 // how many sample points fit in 16 cycles of each frequency
101 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
102 // when to tell if we're close enough to one freq or another
103 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
104
105 // TI tags charge at 134.2Khz
106 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
107 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
108
109 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
110 // connects to SSP_DIN and the SSP_DOUT logic level controls
111 // whether we're modulating the antenna (high)
112 // or listening to the antenna (low)
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
114
115 // get TI tag data into the buffer
116 AcquireTiType();
117
118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
119
120 for (i=0; i<n-1; i++) {
121 // count cycles by looking for lo to hi zero crossings
122 if ( (dest[i]<0) && (dest[i+1]>0) ) {
123 cycles++;
124 // after 16 cycles, measure the frequency
125 if (cycles>15) {
126 cycles=0;
127 samples=i-samples; // number of samples in these 16 cycles
128
129 // TI bits are coming to us lsb first so shift them
130 // right through our 128 bit right shift register
131 shift0 = (shift0>>1) | (shift1 << 31);
132 shift1 = (shift1>>1) | (shift2 << 31);
133 shift2 = (shift2>>1) | (shift3 << 31);
134 shift3 >>= 1;
135
136 // check if the cycles fall close to the number
137 // expected for either the low or high frequency
138 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
139 // low frequency represents a 1
140 shift3 |= (1<<31);
141 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
142 // high frequency represents a 0
143 } else {
144 // probably detected a gay waveform or noise
145 // use this as gaydar or discard shift register and start again
146 shift3 = shift2 = shift1 = shift0 = 0;
147 }
148 samples = i;
149
150 // for each bit we receive, test if we've detected a valid tag
151
152 // if we see 17 zeroes followed by 6 ones, we might have a tag
153 // remember the bits are backwards
154 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
155 // if start and end bytes match, we have a tag so break out of the loop
156 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
157 cycles = 0xF0B; //use this as a flag (ugly but whatever)
158 break;
159 }
160 }
161 }
162 }
163 }
164
165 // if flag is set we have a tag
166 if (cycles!=0xF0B) {
167 DbpString("Info: No valid tag detected.");
168 } else {
169 // put 64 bit data into shift1 and shift0
170 shift0 = (shift0>>24) | (shift1 << 8);
171 shift1 = (shift1>>24) | (shift2 << 8);
172
173 // align 16 bit crc into lower half of shift2
174 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
175
176 // if r/w tag, check ident match
177 if (shift3 & (1<<15) ) {
178 DbpString("Info: TI tag is rewriteable");
179 // only 15 bits compare, last bit of ident is not valid
180 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
181 DbpString("Error: Ident mismatch!");
182 } else {
183 DbpString("Info: TI tag ident is valid");
184 }
185 } else {
186 DbpString("Info: TI tag is readonly");
187 }
188
189 // WARNING the order of the bytes in which we calc crc below needs checking
190 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
191 // bytes in reverse or something
192 // calculate CRC
193 uint32_t crc=0;
194
195 crc = update_crc16(crc, (shift0)&0xff);
196 crc = update_crc16(crc, (shift0>>8)&0xff);
197 crc = update_crc16(crc, (shift0>>16)&0xff);
198 crc = update_crc16(crc, (shift0>>24)&0xff);
199 crc = update_crc16(crc, (shift1)&0xff);
200 crc = update_crc16(crc, (shift1>>8)&0xff);
201 crc = update_crc16(crc, (shift1>>16)&0xff);
202 crc = update_crc16(crc, (shift1>>24)&0xff);
203
204 Dbprintf("Info: Tag data: %x%08x, crc=%x",
205 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
206 if (crc != (shift2&0xffff)) {
207 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
208 } else {
209 DbpString("Info: CRC is good");
210 }
211 }
212 }
213
214 void WriteTIbyte(uint8_t b)
215 {
216 int i = 0;
217
218 // modulate 8 bits out to the antenna
219 for (i=0; i<8; i++)
220 {
221 if (b&(1<<i)) {
222 // stop modulating antenna
223 LOW(GPIO_SSC_DOUT);
224 SpinDelayUs(1000);
225 // modulate antenna
226 HIGH(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 } else {
229 // stop modulating antenna
230 LOW(GPIO_SSC_DOUT);
231 SpinDelayUs(300);
232 // modulate antenna
233 HIGH(GPIO_SSC_DOUT);
234 SpinDelayUs(1700);
235 }
236 }
237 }
238
239 void AcquireTiType(void)
240 {
241 int i, j, n;
242 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
243 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
244 #define TIBUFLEN 1250
245
246 // clear buffer
247 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
248 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
249
250 // Set up the synchronous serial port
251 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
252 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
253
254 // steal this pin from the SSP and use it to control the modulation
255 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
256 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
257
258 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
259 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
260
261 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
262 // 48/2 = 24 MHz clock must be divided by 12
263 AT91C_BASE_SSC->SSC_CMR = 12;
264
265 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
266 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
267 AT91C_BASE_SSC->SSC_TCMR = 0;
268 AT91C_BASE_SSC->SSC_TFMR = 0;
269
270 LED_D_ON();
271
272 // modulate antenna
273 HIGH(GPIO_SSC_DOUT);
274
275 // Charge TI tag for 50ms.
276 SpinDelay(50);
277
278 // stop modulating antenna and listen
279 LOW(GPIO_SSC_DOUT);
280
281 LED_D_OFF();
282
283 i = 0;
284 for(;;) {
285 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
286 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
287 i++; if(i >= TIBUFLEN) break;
288 }
289 WDT_HIT();
290 }
291
292 // return stolen pin to SSP
293 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
294 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
295
296 char *dest = (char *)BigBuf_get_addr();
297 n = TIBUFLEN*32;
298 // unpack buffer
299 for (i=TIBUFLEN-1; i>=0; i--) {
300 for (j=0; j<32; j++) {
301 if(BigBuf[i] & (1 << j)) {
302 dest[--n] = 1;
303 } else {
304 dest[--n] = -1;
305 }
306 }
307 }
308 }
309
310 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
311 // if crc provided, it will be written with the data verbatim (even if bogus)
312 // if not provided a valid crc will be computed from the data and written.
313 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
314 {
315 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
316 if(crc == 0) {
317 crc = update_crc16(crc, (idlo)&0xff);
318 crc = update_crc16(crc, (idlo>>8)&0xff);
319 crc = update_crc16(crc, (idlo>>16)&0xff);
320 crc = update_crc16(crc, (idlo>>24)&0xff);
321 crc = update_crc16(crc, (idhi)&0xff);
322 crc = update_crc16(crc, (idhi>>8)&0xff);
323 crc = update_crc16(crc, (idhi>>16)&0xff);
324 crc = update_crc16(crc, (idhi>>24)&0xff);
325 }
326 Dbprintf("Writing to tag: %x%08x, crc=%x",
327 (unsigned int) idhi, (unsigned int) idlo, crc);
328
329 // TI tags charge at 134.2Khz
330 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
331 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
332 // connects to SSP_DIN and the SSP_DOUT logic level controls
333 // whether we're modulating the antenna (high)
334 // or listening to the antenna (low)
335 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
336 LED_A_ON();
337
338 // steal this pin from the SSP and use it to control the modulation
339 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
340 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
341
342 // writing algorithm:
343 // a high bit consists of a field off for 1ms and field on for 1ms
344 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
345 // initiate a charge time of 50ms (field on) then immediately start writing bits
346 // start by writing 0xBB (keyword) and 0xEB (password)
347 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
348 // finally end with 0x0300 (write frame)
349 // all data is sent lsb firts
350 // finish with 15ms programming time
351
352 // modulate antenna
353 HIGH(GPIO_SSC_DOUT);
354 SpinDelay(50); // charge time
355
356 WriteTIbyte(0xbb); // keyword
357 WriteTIbyte(0xeb); // password
358 WriteTIbyte( (idlo )&0xff );
359 WriteTIbyte( (idlo>>8 )&0xff );
360 WriteTIbyte( (idlo>>16)&0xff );
361 WriteTIbyte( (idlo>>24)&0xff );
362 WriteTIbyte( (idhi )&0xff );
363 WriteTIbyte( (idhi>>8 )&0xff );
364 WriteTIbyte( (idhi>>16)&0xff );
365 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
366 WriteTIbyte( (crc )&0xff ); // crc lo
367 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
368 WriteTIbyte(0x00); // write frame lo
369 WriteTIbyte(0x03); // write frame hi
370 HIGH(GPIO_SSC_DOUT);
371 SpinDelay(50); // programming time
372
373 LED_A_OFF();
374
375 // get TI tag data into the buffer
376 AcquireTiType();
377
378 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
379 DbpString("Now use tiread to check");
380 }
381
382 void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)
383 {
384 int i;
385 uint8_t *tab = BigBuf_get_addr();
386
387 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
388 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
389
390 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
391
392 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
393 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
394
395 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
396 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
397
398 i = 0;
399 for(;;) {
400 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
401 if(BUTTON_PRESS()) {
402 DbpString("Stopped");
403 return;
404 }
405 WDT_HIT();
406 }
407
408 if (ledcontrol)
409 LED_D_ON();
410
411 if(tab[i])
412 OPEN_COIL();
413 else
414 SHORT_COIL();
415
416 if (ledcontrol)
417 LED_D_OFF();
418
419 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
420 if(BUTTON_PRESS()) {
421 DbpString("Stopped");
422 return;
423 }
424 WDT_HIT();
425 }
426
427 i++;
428 if(i == period) {
429 i = 0;
430 if (gap) {
431 SHORT_COIL();
432 SpinDelayUs(gap);
433 }
434 }
435 }
436 }
437
438 #define DEBUG_FRAME_CONTENTS 1
439 void SimulateTagLowFrequencyBidir(int divisor, int t0)
440 {
441 }
442
443 // compose fc/8 fc/10 waveform
444 static void fc(int c, int *n) {
445 uint8_t *dest = BigBuf_get_addr();
446 int idx;
447
448 // for when we want an fc8 pattern every 4 logical bits
449 if(c==0) {
450 dest[((*n)++)]=1;
451 dest[((*n)++)]=1;
452 dest[((*n)++)]=0;
453 dest[((*n)++)]=0;
454 dest[((*n)++)]=0;
455 dest[((*n)++)]=0;
456 dest[((*n)++)]=0;
457 dest[((*n)++)]=0;
458 }
459 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
460 if(c==8) {
461 for (idx=0; idx<6; idx++) {
462 dest[((*n)++)]=1;
463 dest[((*n)++)]=1;
464 dest[((*n)++)]=0;
465 dest[((*n)++)]=0;
466 dest[((*n)++)]=0;
467 dest[((*n)++)]=0;
468 dest[((*n)++)]=0;
469 dest[((*n)++)]=0;
470 }
471 }
472
473 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
474 if(c==10) {
475 for (idx=0; idx<5; idx++) {
476 dest[((*n)++)]=1;
477 dest[((*n)++)]=1;
478 dest[((*n)++)]=1;
479 dest[((*n)++)]=0;
480 dest[((*n)++)]=0;
481 dest[((*n)++)]=0;
482 dest[((*n)++)]=0;
483 dest[((*n)++)]=0;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 }
487 }
488 }
489
490 // prepare a waveform pattern in the buffer based on the ID given then
491 // simulate a HID tag until the button is pressed
492 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
493 {
494 int n=0, i=0;
495 /*
496 HID tag bitstream format
497 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
498 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
499 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
500 A fc8 is inserted before every 4 bits
501 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
502 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
503 */
504
505 if (hi>0xFFF) {
506 DbpString("Tags can only have 44 bits.");
507 return;
508 }
509 fc(0,&n);
510 // special start of frame marker containing invalid bit sequences
511 fc(8, &n); fc(8, &n); // invalid
512 fc(8, &n); fc(10, &n); // logical 0
513 fc(10, &n); fc(10, &n); // invalid
514 fc(8, &n); fc(10, &n); // logical 0
515
516 WDT_HIT();
517 // manchester encode bits 43 to 32
518 for (i=11; i>=0; i--) {
519 if ((i%4)==3) fc(0,&n);
520 if ((hi>>i)&1) {
521 fc(10, &n); fc(8, &n); // low-high transition
522 } else {
523 fc(8, &n); fc(10, &n); // high-low transition
524 }
525 }
526
527 WDT_HIT();
528 // manchester encode bits 31 to 0
529 for (i=31; i>=0; i--) {
530 if ((i%4)==3) fc(0,&n);
531 if ((lo>>i)&1) {
532 fc(10, &n); fc(8, &n); // low-high transition
533 } else {
534 fc(8, &n); fc(10, &n); // high-low transition
535 }
536 }
537
538 if (ledcontrol)
539 LED_A_ON();
540 SimulateTagLowFrequency(n, 0, ledcontrol);
541
542 if (ledcontrol)
543 LED_A_OFF();
544 }
545
546 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
547 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
548 {
549 uint8_t *dest = BigBuf_get_addr();
550 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
551 size_t size = 0;
552 uint32_t hi2=0, hi=0, lo=0;
553 int idx=0;
554 // Configure to go in 125Khz listen mode
555 LFSetupFPGAForADC(95, true);
556
557 while(!BUTTON_PRESS()) {
558
559 WDT_HIT();
560 if (ledcontrol) LED_A_ON();
561
562 DoAcquisition_default(-1,true);
563 // FSK demodulator
564 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
565 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
566
567 if (idx>0 && lo>0){
568 // final loop, go over previously decoded manchester data and decode into usable tag ID
569 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
570 if (hi2 != 0){ //extra large HID tags
571 Dbprintf("TAG ID: %x%08x%08x (%d)",
572 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
573 }else { //standard HID tags <38 bits
574 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
575 uint8_t bitlen = 0;
576 uint32_t fc = 0;
577 uint32_t cardnum = 0;
578 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
579 uint32_t lo2=0;
580 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
581 uint8_t idx3 = 1;
582 while(lo2 > 1){ //find last bit set to 1 (format len bit)
583 lo2=lo2 >> 1;
584 idx3++;
585 }
586 bitlen = idx3+19;
587 fc =0;
588 cardnum=0;
589 if(bitlen == 26){
590 cardnum = (lo>>1)&0xFFFF;
591 fc = (lo>>17)&0xFF;
592 }
593 if(bitlen == 37){
594 cardnum = (lo>>1)&0x7FFFF;
595 fc = ((hi&0xF)<<12)|(lo>>20);
596 }
597 if(bitlen == 34){
598 cardnum = (lo>>1)&0xFFFF;
599 fc= ((hi&1)<<15)|(lo>>17);
600 }
601 if(bitlen == 35){
602 cardnum = (lo>>1)&0xFFFFF;
603 fc = ((hi&1)<<11)|(lo>>21);
604 }
605 }
606 else { //if bit 38 is not set then 37 bit format is used
607 bitlen= 37;
608 fc =0;
609 cardnum=0;
610 if(bitlen==37){
611 cardnum = (lo>>1)&0x7FFFF;
612 fc = ((hi&0xF)<<12)|(lo>>20);
613 }
614 }
615 //Dbprintf("TAG ID: %x%08x (%d)",
616 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
617 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
618 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
619 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
620 }
621 if (findone){
622 if (ledcontrol) LED_A_OFF();
623 *high = hi;
624 *low = lo;
625 return;
626 }
627 // reset
628 hi2 = hi = lo = 0;
629 }
630 WDT_HIT();
631 }
632 DbpString("Stopped");
633 if (ledcontrol) LED_A_OFF();
634 }
635
636 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
637 {
638 uint8_t *dest = BigBuf_get_addr();
639
640 size_t size=0, idx=0;
641 int clk=0, invert=0, errCnt=0, maxErr=20;
642 uint64_t lo=0;
643 // Configure to go in 125Khz listen mode
644 LFSetupFPGAForADC(95, true);
645
646 while(!BUTTON_PRESS()) {
647
648 WDT_HIT();
649 if (ledcontrol) LED_A_ON();
650
651 DoAcquisition_default(-1,true);
652 size = BigBuf_max_traceLen();
653 //Dbprintf("DEBUG: Buffer got");
654 //askdemod and manchester decode
655 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
656 //Dbprintf("DEBUG: ASK Got");
657 WDT_HIT();
658
659 if (errCnt>=0){
660 lo = Em410xDecode(dest, &size, &idx);
661 //Dbprintf("DEBUG: EM GOT");
662 if (lo>0){
663 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
664 (uint32_t)(lo>>32),
665 (uint32_t)lo,
666 (uint32_t)(lo&0xFFFF),
667 (uint32_t)((lo>>16LL) & 0xFF),
668 (uint32_t)(lo & 0xFFFFFF));
669 }
670 if (findone){
671 if (ledcontrol) LED_A_OFF();
672 *high=lo>>32;
673 *low=lo & 0xFFFFFFFF;
674 return;
675 }
676 } else{
677 //Dbprintf("DEBUG: No Tag");
678 }
679 WDT_HIT();
680 lo = 0;
681 clk=0;
682 invert=0;
683 errCnt=0;
684 size=0;
685 }
686 DbpString("Stopped");
687 if (ledcontrol) LED_A_OFF();
688 }
689
690 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
691 {
692 uint8_t *dest = BigBuf_get_addr();
693 int idx=0;
694 uint32_t code=0, code2=0;
695 uint8_t version=0;
696 uint8_t facilitycode=0;
697 uint16_t number=0;
698 // Configure to go in 125Khz listen mode
699 LFSetupFPGAForADC(95, true);
700
701 while(!BUTTON_PRESS()) {
702 WDT_HIT();
703 if (ledcontrol) LED_A_ON();
704 DoAcquisition_default(-1,true);
705 //fskdemod and get start index
706 WDT_HIT();
707 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
708 if (idx>0){
709 //valid tag found
710
711 //Index map
712 //0 10 20 30 40 50 60
713 //| | | | | | |
714 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
715 //-----------------------------------------------------------------------------
716 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
717 //
718 //XSF(version)facility:codeone+codetwo
719 //Handle the data
720 if(findone){ //only print binary if we are doing one
721 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
722 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
723 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
724 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
725 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
726 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
727 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
728 }
729 code = bytebits_to_byte(dest+idx,32);
730 code2 = bytebits_to_byte(dest+idx+32,32);
731 version = bytebits_to_byte(dest+idx+27,8); //14,4
732 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
733 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
734
735 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
736 // if we're only looking for one tag
737 if (findone){
738 if (ledcontrol) LED_A_OFF();
739 //LED_A_OFF();
740 *high=code;
741 *low=code2;
742 return;
743 }
744 code=code2=0;
745 version=facilitycode=0;
746 number=0;
747 idx=0;
748 }
749 WDT_HIT();
750 }
751 DbpString("Stopped");
752 if (ledcontrol) LED_A_OFF();
753 }
754
755 /*------------------------------
756 * T5555/T5557/T5567 routines
757 *------------------------------
758 */
759
760 /* T55x7 configuration register definitions */
761 #define T55x7_POR_DELAY 0x00000001
762 #define T55x7_ST_TERMINATOR 0x00000008
763 #define T55x7_PWD 0x00000010
764 #define T55x7_MAXBLOCK_SHIFT 5
765 #define T55x7_AOR 0x00000200
766 #define T55x7_PSKCF_RF_2 0
767 #define T55x7_PSKCF_RF_4 0x00000400
768 #define T55x7_PSKCF_RF_8 0x00000800
769 #define T55x7_MODULATION_DIRECT 0
770 #define T55x7_MODULATION_PSK1 0x00001000
771 #define T55x7_MODULATION_PSK2 0x00002000
772 #define T55x7_MODULATION_PSK3 0x00003000
773 #define T55x7_MODULATION_FSK1 0x00004000
774 #define T55x7_MODULATION_FSK2 0x00005000
775 #define T55x7_MODULATION_FSK1a 0x00006000
776 #define T55x7_MODULATION_FSK2a 0x00007000
777 #define T55x7_MODULATION_MANCHESTER 0x00008000
778 #define T55x7_MODULATION_BIPHASE 0x00010000
779 #define T55x7_BITRATE_RF_8 0
780 #define T55x7_BITRATE_RF_16 0x00040000
781 #define T55x7_BITRATE_RF_32 0x00080000
782 #define T55x7_BITRATE_RF_40 0x000C0000
783 #define T55x7_BITRATE_RF_50 0x00100000
784 #define T55x7_BITRATE_RF_64 0x00140000
785 #define T55x7_BITRATE_RF_100 0x00180000
786 #define T55x7_BITRATE_RF_128 0x001C0000
787
788 /* T5555 (Q5) configuration register definitions */
789 #define T5555_ST_TERMINATOR 0x00000001
790 #define T5555_MAXBLOCK_SHIFT 0x00000001
791 #define T5555_MODULATION_MANCHESTER 0
792 #define T5555_MODULATION_PSK1 0x00000010
793 #define T5555_MODULATION_PSK2 0x00000020
794 #define T5555_MODULATION_PSK3 0x00000030
795 #define T5555_MODULATION_FSK1 0x00000040
796 #define T5555_MODULATION_FSK2 0x00000050
797 #define T5555_MODULATION_BIPHASE 0x00000060
798 #define T5555_MODULATION_DIRECT 0x00000070
799 #define T5555_INVERT_OUTPUT 0x00000080
800 #define T5555_PSK_RF_2 0
801 #define T5555_PSK_RF_4 0x00000100
802 #define T5555_PSK_RF_8 0x00000200
803 #define T5555_USE_PWD 0x00000400
804 #define T5555_USE_AOR 0x00000800
805 #define T5555_BITRATE_SHIFT 12
806 #define T5555_FAST_WRITE 0x00004000
807 #define T5555_PAGE_SELECT 0x00008000
808
809 /*
810 * Relevant times in microsecond
811 * To compensate antenna falling times shorten the write times
812 * and enlarge the gap ones.
813 */
814 #define START_GAP 30*8 // 10 - 50fc 250
815 #define WRITE_GAP 20*8 // 8 - 30fc
816 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
817 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
818
819 // VALUES TAKEN FROM EM4x function: SendForward
820 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
821 // WRITE_GAP = 128; (16*8)
822 // WRITE_1 = 256 32*8; (32*8)
823
824 // These timings work for 4469/4269/4305 (with the 55*8 above)
825 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
826
827 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
828
829 // Write one bit to card
830 void T55xxWriteBit(int bit)
831 {
832 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
833 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
834 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
835 if (!bit)
836 SpinDelayUs(WRITE_0);
837 else
838 SpinDelayUs(WRITE_1);
839 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
840 SpinDelayUs(WRITE_GAP);
841 }
842
843 // Write one card block in page 0, no lock
844 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
845 {
846 uint32_t i = 0;
847
848 // Set up FPGA, 125kHz
849 // Wait for config.. (192+8190xPOW)x8 == 67ms
850 LFSetupFPGAForADC(0, true);
851
852 // Now start writting
853 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
854 SpinDelayUs(START_GAP);
855
856 // Opcode
857 T55xxWriteBit(1);
858 T55xxWriteBit(0); //Page 0
859 if (PwdMode == 1){
860 // Pwd
861 for (i = 0x80000000; i != 0; i >>= 1)
862 T55xxWriteBit(Pwd & i);
863 }
864 // Lock bit
865 T55xxWriteBit(0);
866
867 // Data
868 for (i = 0x80000000; i != 0; i >>= 1)
869 T55xxWriteBit(Data & i);
870
871 // Block
872 for (i = 0x04; i != 0; i >>= 1)
873 T55xxWriteBit(Block & i);
874
875 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
876 // so wait a little more)
877 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
878 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
879 SpinDelay(20);
880 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
881 }
882
883 // Read one card block in page 0
884 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
885 {
886 uint32_t i = 0;
887 uint8_t *dest = BigBuf_get_addr();
888 uint16_t bufferlength = BigBuf_max_traceLen();
889 if ( bufferlength > T55xx_SAMPLES_SIZE )
890 bufferlength = T55xx_SAMPLES_SIZE;
891
892 memset(dest, 0x80, bufferlength);
893
894 // Set up FPGA, 125kHz
895 // Wait for config.. (192+8190xPOW)x8 == 67ms
896 LFSetupFPGAForADC(0, true);
897 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
898 SpinDelayUs(START_GAP);
899
900 // Opcode
901 T55xxWriteBit(1);
902 T55xxWriteBit(0); //Page 0
903 if (PwdMode == 1){
904 // Pwd
905 for (i = 0x80000000; i != 0; i >>= 1)
906 T55xxWriteBit(Pwd & i);
907 }
908 // Lock bit
909 T55xxWriteBit(0);
910 // Block
911 for (i = 0x04; i != 0; i >>= 1)
912 T55xxWriteBit(Block & i);
913
914 // Turn field on to read the response
915 TurnReadLFOn();
916
917 // Now do the acquisition
918 i = 0;
919 for(;;) {
920 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
921 AT91C_BASE_SSC->SSC_THR = 0x43;
922 LED_D_ON();
923 }
924 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
925 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
926 ++i;
927 LED_D_OFF();
928 if (i >= bufferlength) break;
929 }
930 }
931
932 cmd_send(CMD_ACK,0,0,0,0,0);
933 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
934 LED_D_OFF();
935 }
936
937 // Read card traceability data (page 1)
938 void T55xxReadTrace(void){
939
940 uint32_t i = 0;
941 uint8_t *dest = BigBuf_get_addr();
942 uint16_t bufferlength = BigBuf_max_traceLen();
943 if ( bufferlength > T55xx_SAMPLES_SIZE )
944 bufferlength = T55xx_SAMPLES_SIZE;
945
946 memset(dest, 0x80, bufferlength);
947
948 LFSetupFPGAForADC(0, true);
949 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
950 SpinDelayUs(START_GAP);
951
952 // Opcode
953 T55xxWriteBit(1);
954 T55xxWriteBit(1); //Page 1
955
956 // Turn field on to read the response
957 TurnReadLFOn();
958
959 // Now do the acquisition
960 for(;;) {
961 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
962 AT91C_BASE_SSC->SSC_THR = 0x43;
963 LED_D_ON();
964 }
965 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
966 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
967 ++i;
968 LED_D_OFF();
969
970 if (i >= bufferlength) break;
971 }
972 }
973
974 cmd_send(CMD_ACK,0,0,0,0,0);
975 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
976 LED_D_OFF();
977 }
978
979 void TurnReadLFOn(){
980 //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
981 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
982 // Give it a bit of time for the resonant antenna to settle.
983 //SpinDelay(30);
984 SpinDelayUs(9*150);
985 }
986
987 /*-------------- Cloning routines -----------*/
988 // Copy HID id to card and setup block 0 config
989 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
990 {
991 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
992 int last_block = 0;
993
994 if (longFMT){
995 // Ensure no more than 84 bits supplied
996 if (hi2>0xFFFFF) {
997 DbpString("Tags can only have 84 bits.");
998 return;
999 }
1000 // Build the 6 data blocks for supplied 84bit ID
1001 last_block = 6;
1002 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1003 for (int i=0;i<4;i++) {
1004 if (hi2 & (1<<(19-i)))
1005 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1006 else
1007 data1 |= (1<<((3-i)*2)); // 0 -> 01
1008 }
1009
1010 data2 = 0;
1011 for (int i=0;i<16;i++) {
1012 if (hi2 & (1<<(15-i)))
1013 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1014 else
1015 data2 |= (1<<((15-i)*2)); // 0 -> 01
1016 }
1017
1018 data3 = 0;
1019 for (int i=0;i<16;i++) {
1020 if (hi & (1<<(31-i)))
1021 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1022 else
1023 data3 |= (1<<((15-i)*2)); // 0 -> 01
1024 }
1025
1026 data4 = 0;
1027 for (int i=0;i<16;i++) {
1028 if (hi & (1<<(15-i)))
1029 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1030 else
1031 data4 |= (1<<((15-i)*2)); // 0 -> 01
1032 }
1033
1034 data5 = 0;
1035 for (int i=0;i<16;i++) {
1036 if (lo & (1<<(31-i)))
1037 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1038 else
1039 data5 |= (1<<((15-i)*2)); // 0 -> 01
1040 }
1041
1042 data6 = 0;
1043 for (int i=0;i<16;i++) {
1044 if (lo & (1<<(15-i)))
1045 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1046 else
1047 data6 |= (1<<((15-i)*2)); // 0 -> 01
1048 }
1049 }
1050 else {
1051 // Ensure no more than 44 bits supplied
1052 if (hi>0xFFF) {
1053 DbpString("Tags can only have 44 bits.");
1054 return;
1055 }
1056
1057 // Build the 3 data blocks for supplied 44bit ID
1058 last_block = 3;
1059
1060 data1 = 0x1D000000; // load preamble
1061
1062 for (int i=0;i<12;i++) {
1063 if (hi & (1<<(11-i)))
1064 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1065 else
1066 data1 |= (1<<((11-i)*2)); // 0 -> 01
1067 }
1068
1069 data2 = 0;
1070 for (int i=0;i<16;i++) {
1071 if (lo & (1<<(31-i)))
1072 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1073 else
1074 data2 |= (1<<((15-i)*2)); // 0 -> 01
1075 }
1076
1077 data3 = 0;
1078 for (int i=0;i<16;i++) {
1079 if (lo & (1<<(15-i)))
1080 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1081 else
1082 data3 |= (1<<((15-i)*2)); // 0 -> 01
1083 }
1084 }
1085
1086 LED_D_ON();
1087 // Program the data blocks for supplied ID
1088 // and the block 0 for HID format
1089 T55xxWriteBlock(data1,1,0,0);
1090 T55xxWriteBlock(data2,2,0,0);
1091 T55xxWriteBlock(data3,3,0,0);
1092
1093 if (longFMT) { // if long format there are 6 blocks
1094 T55xxWriteBlock(data4,4,0,0);
1095 T55xxWriteBlock(data5,5,0,0);
1096 T55xxWriteBlock(data6,6,0,0);
1097 }
1098
1099 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1100 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1101 T55x7_MODULATION_FSK2a |
1102 last_block << T55x7_MAXBLOCK_SHIFT,
1103 0,0,0);
1104
1105 LED_D_OFF();
1106
1107 DbpString("DONE!");
1108 }
1109
1110 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1111 {
1112 int data1=0, data2=0; //up to six blocks for long format
1113
1114 data1 = hi; // load preamble
1115 data2 = lo;
1116
1117 LED_D_ON();
1118 // Program the data blocks for supplied ID
1119 // and the block 0 for HID format
1120 T55xxWriteBlock(data1,1,0,0);
1121 T55xxWriteBlock(data2,2,0,0);
1122
1123 //Config Block
1124 T55xxWriteBlock(0x00147040,0,0,0);
1125 LED_D_OFF();
1126
1127 DbpString("DONE!");
1128 }
1129
1130 // Define 9bit header for EM410x tags
1131 #define EM410X_HEADER 0x1FF
1132 #define EM410X_ID_LENGTH 40
1133
1134 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1135 {
1136 int i, id_bit;
1137 uint64_t id = EM410X_HEADER;
1138 uint64_t rev_id = 0; // reversed ID
1139 int c_parity[4]; // column parity
1140 int r_parity = 0; // row parity
1141 uint32_t clock = 0;
1142
1143 // Reverse ID bits given as parameter (for simpler operations)
1144 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1145 if (i < 32) {
1146 rev_id = (rev_id << 1) | (id_lo & 1);
1147 id_lo >>= 1;
1148 } else {
1149 rev_id = (rev_id << 1) | (id_hi & 1);
1150 id_hi >>= 1;
1151 }
1152 }
1153
1154 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1155 id_bit = rev_id & 1;
1156
1157 if (i % 4 == 0) {
1158 // Don't write row parity bit at start of parsing
1159 if (i)
1160 id = (id << 1) | r_parity;
1161 // Start counting parity for new row
1162 r_parity = id_bit;
1163 } else {
1164 // Count row parity
1165 r_parity ^= id_bit;
1166 }
1167
1168 // First elements in column?
1169 if (i < 4)
1170 // Fill out first elements
1171 c_parity[i] = id_bit;
1172 else
1173 // Count column parity
1174 c_parity[i % 4] ^= id_bit;
1175
1176 // Insert ID bit
1177 id = (id << 1) | id_bit;
1178 rev_id >>= 1;
1179 }
1180
1181 // Insert parity bit of last row
1182 id = (id << 1) | r_parity;
1183
1184 // Fill out column parity at the end of tag
1185 for (i = 0; i < 4; ++i)
1186 id = (id << 1) | c_parity[i];
1187
1188 // Add stop bit
1189 id <<= 1;
1190
1191 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1192 LED_D_ON();
1193
1194 // Write EM410x ID
1195 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1196 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1197
1198 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1199 if (card) {
1200 // Clock rate is stored in bits 8-15 of the card value
1201 clock = (card & 0xFF00) >> 8;
1202 Dbprintf("Clock rate: %d", clock);
1203 switch (clock)
1204 {
1205 case 32:
1206 clock = T55x7_BITRATE_RF_32;
1207 break;
1208 case 16:
1209 clock = T55x7_BITRATE_RF_16;
1210 break;
1211 case 0:
1212 // A value of 0 is assumed to be 64 for backwards-compatibility
1213 // Fall through...
1214 case 64:
1215 clock = T55x7_BITRATE_RF_64;
1216 break;
1217 default:
1218 Dbprintf("Invalid clock rate: %d", clock);
1219 return;
1220 }
1221
1222 // Writing configuration for T55x7 tag
1223 T55xxWriteBlock(clock |
1224 T55x7_MODULATION_MANCHESTER |
1225 2 << T55x7_MAXBLOCK_SHIFT,
1226 0, 0, 0);
1227 }
1228 else
1229 // Writing configuration for T5555(Q5) tag
1230 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1231 T5555_MODULATION_MANCHESTER |
1232 2 << T5555_MAXBLOCK_SHIFT,
1233 0, 0, 0);
1234
1235 LED_D_OFF();
1236 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1237 (uint32_t)(id >> 32), (uint32_t)id);
1238 }
1239
1240 // Clone Indala 64-bit tag by UID to T55x7
1241 void CopyIndala64toT55x7(int hi, int lo)
1242 {
1243
1244 //Program the 2 data blocks for supplied 64bit UID
1245 // and the block 0 for Indala64 format
1246 T55xxWriteBlock(hi,1,0,0);
1247 T55xxWriteBlock(lo,2,0,0);
1248 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1249 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1250 T55x7_MODULATION_PSK1 |
1251 2 << T55x7_MAXBLOCK_SHIFT,
1252 0, 0, 0);
1253 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1254 // T5567WriteBlock(0x603E1042,0);
1255
1256 DbpString("DONE!");
1257
1258 }
1259
1260 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1261 {
1262
1263 //Program the 7 data blocks for supplied 224bit UID
1264 // and the block 0 for Indala224 format
1265 T55xxWriteBlock(uid1,1,0,0);
1266 T55xxWriteBlock(uid2,2,0,0);
1267 T55xxWriteBlock(uid3,3,0,0);
1268 T55xxWriteBlock(uid4,4,0,0);
1269 T55xxWriteBlock(uid5,5,0,0);
1270 T55xxWriteBlock(uid6,6,0,0);
1271 T55xxWriteBlock(uid7,7,0,0);
1272 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1273 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1274 T55x7_MODULATION_PSK1 |
1275 7 << T55x7_MAXBLOCK_SHIFT,
1276 0,0,0);
1277 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1278 // T5567WriteBlock(0x603E10E2,0);
1279
1280 DbpString("DONE!");
1281
1282 }
1283
1284
1285 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1286 #define max(x,y) ( x<y ? y:x)
1287
1288 int DemodPCF7931(uint8_t **outBlocks) {
1289 uint8_t BitStream[256];
1290 uint8_t Blocks[8][16];
1291 uint8_t *GraphBuffer = BigBuf_get_addr();
1292 int GraphTraceLen = BigBuf_max_traceLen();
1293 int i, j, lastval, bitidx, half_switch;
1294 int clock = 64;
1295 int tolerance = clock / 8;
1296 int pmc, block_done;
1297 int lc, warnings = 0;
1298 int num_blocks = 0;
1299 int lmin=128, lmax=128;
1300 uint8_t dir;
1301
1302 LFSetupFPGAForADC(95, true);
1303 DoAcquisition_default(0, 0);
1304
1305
1306 lmin = 64;
1307 lmax = 192;
1308
1309 i = 2;
1310
1311 /* Find first local max/min */
1312 if(GraphBuffer[1] > GraphBuffer[0]) {
1313 while(i < GraphTraceLen) {
1314 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1315 break;
1316 i++;
1317 }
1318 dir = 0;
1319 }
1320 else {
1321 while(i < GraphTraceLen) {
1322 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1323 break;
1324 i++;
1325 }
1326 dir = 1;
1327 }
1328
1329 lastval = i++;
1330 half_switch = 0;
1331 pmc = 0;
1332 block_done = 0;
1333
1334 for (bitidx = 0; i < GraphTraceLen; i++)
1335 {
1336 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1337 {
1338 lc = i - lastval;
1339 lastval = i;
1340
1341 // Switch depending on lc length:
1342 // Tolerance is 1/8 of clock rate (arbitrary)
1343 if (abs(lc-clock/4) < tolerance) {
1344 // 16T0
1345 if((i - pmc) == lc) { /* 16T0 was previous one */
1346 /* It's a PMC ! */
1347 i += (128+127+16+32+33+16)-1;
1348 lastval = i;
1349 pmc = 0;
1350 block_done = 1;
1351 }
1352 else {
1353 pmc = i;
1354 }
1355 } else if (abs(lc-clock/2) < tolerance) {
1356 // 32TO
1357 if((i - pmc) == lc) { /* 16T0 was previous one */
1358 /* It's a PMC ! */
1359 i += (128+127+16+32+33)-1;
1360 lastval = i;
1361 pmc = 0;
1362 block_done = 1;
1363 }
1364 else if(half_switch == 1) {
1365 BitStream[bitidx++] = 0;
1366 half_switch = 0;
1367 }
1368 else
1369 half_switch++;
1370 } else if (abs(lc-clock) < tolerance) {
1371 // 64TO
1372 BitStream[bitidx++] = 1;
1373 } else {
1374 // Error
1375 warnings++;
1376 if (warnings > 10)
1377 {
1378 Dbprintf("Error: too many detection errors, aborting.");
1379 return 0;
1380 }
1381 }
1382
1383 if(block_done == 1) {
1384 if(bitidx == 128) {
1385 for(j=0; j<16; j++) {
1386 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1387 64*BitStream[j*8+6]+
1388 32*BitStream[j*8+5]+
1389 16*BitStream[j*8+4]+
1390 8*BitStream[j*8+3]+
1391 4*BitStream[j*8+2]+
1392 2*BitStream[j*8+1]+
1393 BitStream[j*8];
1394 }
1395 num_blocks++;
1396 }
1397 bitidx = 0;
1398 block_done = 0;
1399 half_switch = 0;
1400 }
1401 if(i < GraphTraceLen)
1402 {
1403 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1404 else dir = 1;
1405 }
1406 }
1407 if(bitidx==255)
1408 bitidx=0;
1409 warnings = 0;
1410 if(num_blocks == 4) break;
1411 }
1412 memcpy(outBlocks, Blocks, 16*num_blocks);
1413 return num_blocks;
1414 }
1415
1416 int IsBlock0PCF7931(uint8_t *Block) {
1417 // Assume RFU means 0 :)
1418 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1419 return 1;
1420 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1421 return 1;
1422 return 0;
1423 }
1424
1425 int IsBlock1PCF7931(uint8_t *Block) {
1426 // Assume RFU means 0 :)
1427 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1428 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1429 return 1;
1430
1431 return 0;
1432 }
1433
1434 #define ALLOC 16
1435
1436 void ReadPCF7931() {
1437 uint8_t Blocks[8][17];
1438 uint8_t tmpBlocks[4][16];
1439 int i, j, ind, ind2, n;
1440 int num_blocks = 0;
1441 int max_blocks = 8;
1442 int ident = 0;
1443 int error = 0;
1444 int tries = 0;
1445
1446 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1447
1448 do {
1449 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1450 n = DemodPCF7931((uint8_t**)tmpBlocks);
1451 if(!n)
1452 error++;
1453 if(error==10 && num_blocks == 0) {
1454 Dbprintf("Error, no tag or bad tag");
1455 return;
1456 }
1457 else if (tries==20 || error==10) {
1458 Dbprintf("Error reading the tag");
1459 Dbprintf("Here is the partial content");
1460 goto end;
1461 }
1462
1463 for(i=0; i<n; i++)
1464 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1465 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1466 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1467 if(!ident) {
1468 for(i=0; i<n; i++) {
1469 if(IsBlock0PCF7931(tmpBlocks[i])) {
1470 // Found block 0 ?
1471 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1472 // Found block 1!
1473 // \o/
1474 ident = 1;
1475 memcpy(Blocks[0], tmpBlocks[i], 16);
1476 Blocks[0][ALLOC] = 1;
1477 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1478 Blocks[1][ALLOC] = 1;
1479 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1480 // Debug print
1481 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1482 num_blocks = 2;
1483 // Handle following blocks
1484 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1485 if(j==n) j=0;
1486 if(j==i) break;
1487 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1488 Blocks[ind2][ALLOC] = 1;
1489 }
1490 break;
1491 }
1492 }
1493 }
1494 }
1495 else {
1496 for(i=0; i<n; i++) { // Look for identical block in known blocks
1497 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1498 for(j=0; j<max_blocks; j++) {
1499 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1500 // Found an identical block
1501 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1502 if(ind2 < 0)
1503 ind2 = max_blocks;
1504 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1505 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1506 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1507 Blocks[ind2][ALLOC] = 1;
1508 num_blocks++;
1509 if(num_blocks == max_blocks) goto end;
1510 }
1511 }
1512 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1513 if(ind2 > max_blocks)
1514 ind2 = 0;
1515 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1516 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1517 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1518 Blocks[ind2][ALLOC] = 1;
1519 num_blocks++;
1520 if(num_blocks == max_blocks) goto end;
1521 }
1522 }
1523 }
1524 }
1525 }
1526 }
1527 }
1528 tries++;
1529 if (BUTTON_PRESS()) return;
1530 } while (num_blocks != max_blocks);
1531 end:
1532 Dbprintf("-----------------------------------------");
1533 Dbprintf("Memory content:");
1534 Dbprintf("-----------------------------------------");
1535 for(i=0; i<max_blocks; i++) {
1536 if(Blocks[i][ALLOC]==1)
1537 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1538 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1539 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1540 else
1541 Dbprintf("<missing block %d>", i);
1542 }
1543 Dbprintf("-----------------------------------------");
1544
1545 return ;
1546 }
1547
1548
1549 //-----------------------------------
1550 // EM4469 / EM4305 routines
1551 //-----------------------------------
1552 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1553 #define FWD_CMD_WRITE 0xA
1554 #define FWD_CMD_READ 0x9
1555 #define FWD_CMD_DISABLE 0x5
1556
1557
1558 uint8_t forwardLink_data[64]; //array of forwarded bits
1559 uint8_t * forward_ptr; //ptr for forward message preparation
1560 uint8_t fwd_bit_sz; //forwardlink bit counter
1561 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1562
1563 //====================================================================
1564 // prepares command bits
1565 // see EM4469 spec
1566 //====================================================================
1567 //--------------------------------------------------------------------
1568 uint8_t Prepare_Cmd( uint8_t cmd ) {
1569 //--------------------------------------------------------------------
1570
1571 *forward_ptr++ = 0; //start bit
1572 *forward_ptr++ = 0; //second pause for 4050 code
1573
1574 *forward_ptr++ = cmd;
1575 cmd >>= 1;
1576 *forward_ptr++ = cmd;
1577 cmd >>= 1;
1578 *forward_ptr++ = cmd;
1579 cmd >>= 1;
1580 *forward_ptr++ = cmd;
1581
1582 return 6; //return number of emited bits
1583 }
1584
1585 //====================================================================
1586 // prepares address bits
1587 // see EM4469 spec
1588 //====================================================================
1589
1590 //--------------------------------------------------------------------
1591 uint8_t Prepare_Addr( uint8_t addr ) {
1592 //--------------------------------------------------------------------
1593
1594 register uint8_t line_parity;
1595
1596 uint8_t i;
1597 line_parity = 0;
1598 for(i=0;i<6;i++) {
1599 *forward_ptr++ = addr;
1600 line_parity ^= addr;
1601 addr >>= 1;
1602 }
1603
1604 *forward_ptr++ = (line_parity & 1);
1605
1606 return 7; //return number of emited bits
1607 }
1608
1609 //====================================================================
1610 // prepares data bits intreleaved with parity bits
1611 // see EM4469 spec
1612 //====================================================================
1613
1614 //--------------------------------------------------------------------
1615 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1616 //--------------------------------------------------------------------
1617
1618 register uint8_t line_parity;
1619 register uint8_t column_parity;
1620 register uint8_t i, j;
1621 register uint16_t data;
1622
1623 data = data_low;
1624 column_parity = 0;
1625
1626 for(i=0; i<4; i++) {
1627 line_parity = 0;
1628 for(j=0; j<8; j++) {
1629 line_parity ^= data;
1630 column_parity ^= (data & 1) << j;
1631 *forward_ptr++ = data;
1632 data >>= 1;
1633 }
1634 *forward_ptr++ = line_parity;
1635 if(i == 1)
1636 data = data_hi;
1637 }
1638
1639 for(j=0; j<8; j++) {
1640 *forward_ptr++ = column_parity;
1641 column_parity >>= 1;
1642 }
1643 *forward_ptr = 0;
1644
1645 return 45; //return number of emited bits
1646 }
1647
1648 //====================================================================
1649 // Forward Link send function
1650 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1651 // fwd_bit_count set with number of bits to be sent
1652 //====================================================================
1653 void SendForward(uint8_t fwd_bit_count) {
1654
1655 fwd_write_ptr = forwardLink_data;
1656 fwd_bit_sz = fwd_bit_count;
1657
1658 LED_D_ON();
1659
1660 //Field on
1661 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1662 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1663 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1664
1665 // Give it a bit of time for the resonant antenna to settle.
1666 // And for the tag to fully power up
1667 SpinDelay(150);
1668
1669 // force 1st mod pulse (start gap must be longer for 4305)
1670 fwd_bit_sz--; //prepare next bit modulation
1671 fwd_write_ptr++;
1672 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1673 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1674 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1675 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1676 SpinDelayUs(16*8); //16 cycles on (8us each)
1677
1678 // now start writting
1679 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1680 if(((*fwd_write_ptr++) & 1) == 1)
1681 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1682 else {
1683 //These timings work for 4469/4269/4305 (with the 55*8 above)
1684 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1685 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1686 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1687 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1688 SpinDelayUs(9*8); //16 cycles on (8us each)
1689 }
1690 }
1691 }
1692
1693 void EM4xLogin(uint32_t Password) {
1694
1695 uint8_t fwd_bit_count;
1696
1697 forward_ptr = forwardLink_data;
1698 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1699 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1700
1701 SendForward(fwd_bit_count);
1702
1703 //Wait for command to complete
1704 SpinDelay(20);
1705
1706 }
1707
1708 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1709
1710 uint8_t *dest = BigBuf_get_addr();
1711 uint16_t bufferlength = BigBuf_max_traceLen();
1712 uint32_t i = 0;
1713
1714 // Clear destination buffer before sending the command 0x80 = average.
1715 memset(dest, 0x80, bufferlength);
1716
1717 uint8_t fwd_bit_count;
1718
1719 //If password mode do login
1720 if (PwdMode == 1) EM4xLogin(Pwd);
1721
1722 forward_ptr = forwardLink_data;
1723 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1724 fwd_bit_count += Prepare_Addr( Address );
1725
1726 // Connect the A/D to the peak-detected low-frequency path.
1727 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1728 // Now set up the SSC to get the ADC samples that are now streaming at us.
1729 FpgaSetupSsc();
1730
1731 SendForward(fwd_bit_count);
1732
1733 // Now do the acquisition
1734 i = 0;
1735 for(;;) {
1736 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1737 AT91C_BASE_SSC->SSC_THR = 0x43;
1738 }
1739 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1740 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1741 ++i;
1742 if (i >= bufferlength) break;
1743 }
1744 }
1745
1746 cmd_send(CMD_ACK,0,0,0,0,0);
1747 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1748 LED_D_OFF();
1749 }
1750
1751 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1752
1753 uint8_t fwd_bit_count;
1754
1755 //If password mode do login
1756 if (PwdMode == 1) EM4xLogin(Pwd);
1757
1758 forward_ptr = forwardLink_data;
1759 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1760 fwd_bit_count += Prepare_Addr( Address );
1761 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1762
1763 SendForward(fwd_bit_count);
1764
1765 //Wait for write to complete
1766 SpinDelay(20);
1767 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1768 LED_D_OFF();
1769 }
Proxmark3 GIT tracking
Impressum, Datenschutz