1 //-----------------------------------------------------------------------------
2 // Gerhard de Koning Gans - May 2008
3 // Hagen Fritsch - June 2010
4 // Gerhard de Koning Gans - May 2011
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
9 //-----------------------------------------------------------------------------
10 // Routines to support iClass.
11 //-----------------------------------------------------------------------------
12 // Based on ISO14443a implementation. Still in experimental phase.
13 // Contribution made during a security research at Radboud University Nijmegen
15 // Please feel free to contribute and extend iClass support!!
16 //-----------------------------------------------------------------------------
25 // We still have sometimes a demodulation error when snooping iClass communication.
26 // The resulting trace of a read-block-03 command may look something like this:
28 // + 22279: : 0c 03 e8 01
30 // ...with an incorrect answer...
32 // + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
34 // We still left the error signalling bytes in the traces like 0xbb
36 // A correct trace should look like this:
38 // + 21112: : 0c 03 e8 01
39 // + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
41 //-----------------------------------------------------------------------------
43 #include "proxmark3.h"
50 static uint8_t *trace
= (uint8_t *) BigBuf
;
51 static int traceLen
= 0;
52 static int rsamples
= 0;
55 // Sequence D: 11110000 modulation with subcarrier during first half
56 // Sequence E: 00001111 modulation with subcarrier during second half
57 // Sequence F: 00000000 no modulation with subcarrier
59 // Sequence X: 00001100 drop after half a period
60 // Sequence Y: 00000000 no drop
61 // Sequence Z: 11000000 drop at start
69 static const uint8_t OddByteParity
[256] = {
70 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
71 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
72 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
73 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
74 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
75 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
76 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
77 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
78 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
79 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
80 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
81 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
82 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
83 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
84 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
85 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
88 //static const uint8_t MajorityNibble[16] = { 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1 };
89 //static const uint8_t MajorityNibble[16] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
91 // BIG CHANGE - UNDERSTAND THIS BEFORE WE COMMIT
92 #define RECV_CMD_OFFSET 3032
93 #define RECV_RES_OFFSET 3096
94 #define DMA_BUFFER_OFFSET 3160
95 #define DMA_BUFFER_SIZE 4096
96 #define TRACE_LENGTH 3000
99 //-----------------------------------------------------------------------------
100 // The software UART that receives commands from the reader, and its state
102 //-----------------------------------------------------------------------------
106 STATE_START_OF_COMMUNICATION
,
127 static RAMFUNC
int MillerDecoding(int bit
)
132 if(!Uart
.bitBuffer
) {
133 Uart
.bitBuffer
= bit
^ 0xFF0;
137 Uart
.bitBuffer
<<= 4;
138 Uart
.bitBuffer
^= bit
;
142 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
145 if(Uart.byteCnt > 15) { return TRUE; }
151 if(Uart
.state
!= STATE_UNSYNCD
) {
154 if((Uart
.bitBuffer
& Uart
.syncBit
) ^ Uart
.syncBit
) {
160 if(((Uart
.bitBuffer
<< 1) & Uart
.syncBit
) ^ Uart
.syncBit
) {
166 if(bit
!= bitright
) { bit
= bitright
; }
169 // So, now we only have to deal with *bit*, lets see...
170 if(Uart
.posCnt
== 1) {
171 // measurement first half bitperiod
173 // Drop in first half means that we are either seeing
176 if(Uart
.nOutOfCnt
== 1) {
177 // End of Communication
178 Uart
.state
= STATE_UNSYNCD
;
180 if(Uart
.byteCnt
== 0) {
181 // Its not straightforward to show single EOFs
182 // So just leave it and do not return TRUE
183 Uart
.output
[Uart
.byteCnt
] = 0xf0;
186 // Calculate the parity bit for the client...
193 else if(Uart
.state
!= STATE_START_OF_COMMUNICATION
) {
194 // When not part of SOF or EOF, it is an error
195 Uart
.state
= STATE_UNSYNCD
;
202 // measurement second half bitperiod
203 // Count the bitslot we are in... (ISO 15693)
207 if(Uart
.dropPosition
) {
208 if(Uart
.state
== STATE_START_OF_COMMUNICATION
) {
214 // It is an error if we already have seen a drop in current frame
215 Uart
.state
= STATE_UNSYNCD
;
219 Uart
.dropPosition
= Uart
.nOutOfCnt
;
226 if(Uart
.nOutOfCnt
== Uart
.OutOfCnt
&& Uart
.OutOfCnt
== 4) {
229 if(Uart
.state
== STATE_START_OF_COMMUNICATION
) {
230 if(Uart
.dropPosition
== 4) {
231 Uart
.state
= STATE_RECEIVING
;
234 else if(Uart
.dropPosition
== 3) {
235 Uart
.state
= STATE_RECEIVING
;
237 //Uart.output[Uart.byteCnt] = 0xdd;
241 Uart
.state
= STATE_UNSYNCD
;
244 Uart
.dropPosition
= 0;
249 if(!Uart
.dropPosition
) {
250 Uart
.state
= STATE_UNSYNCD
;
259 //if(Uart.dropPosition == 1) { Uart.dropPosition = 2; }
260 //else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; }
262 Uart
.shiftReg
^= ((Uart
.dropPosition
& 0x03) << 6);
264 Uart
.dropPosition
= 0;
266 if(Uart
.bitCnt
== 8) {
267 Uart
.output
[Uart
.byteCnt
] = (Uart
.shiftReg
& 0xff);
270 // Calculate the parity bit for the client...
271 Uart
.parityBits
<<= 1;
272 Uart
.parityBits
^= OddByteParity
[(Uart
.shiftReg
& 0xff)];
280 else if(Uart
.nOutOfCnt
== Uart
.OutOfCnt
) {
283 if(!Uart
.dropPosition
) {
284 Uart
.state
= STATE_UNSYNCD
;
290 Uart
.output
[Uart
.byteCnt
] = (Uart
.dropPosition
& 0xff);
293 // Calculate the parity bit for the client...
294 Uart
.parityBits
<<= 1;
295 Uart
.parityBits
^= OddByteParity
[(Uart
.dropPosition
& 0xff)];
300 Uart
.dropPosition
= 0;
305 Uart.output[Uart.byteCnt] = 0xAA;
307 Uart.output[Uart.byteCnt] = error & 0xFF;
309 Uart.output[Uart.byteCnt] = 0xAA;
311 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
313 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
315 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
317 Uart.output[Uart.byteCnt] = 0xAA;
325 bit
= Uart
.bitBuffer
& 0xf0;
327 bit
^= 0x0F; // drops become 1s ;-)
329 // should have been high or at least (4 * 128) / fc
330 // according to ISO this should be at least (9 * 128 + 20) / fc
331 if(Uart
.highCnt
== 8) {
332 // we went low, so this could be start of communication
333 // it turns out to be safer to choose a less significant
334 // syncbit... so we check whether the neighbour also represents the drop
335 Uart
.posCnt
= 1; // apparently we are busy with our first half bit period
336 Uart
.syncBit
= bit
& 8;
338 if(!Uart
.syncBit
) { Uart
.syncBit
= bit
& 4; Uart
.samples
= 2; }
339 else if(bit
& 4) { Uart
.syncBit
= bit
& 4; Uart
.samples
= 2; bit
<<= 2; }
340 if(!Uart
.syncBit
) { Uart
.syncBit
= bit
& 2; Uart
.samples
= 1; }
341 else if(bit
& 2) { Uart
.syncBit
= bit
& 2; Uart
.samples
= 1; bit
<<= 1; }
342 if(!Uart
.syncBit
) { Uart
.syncBit
= bit
& 1; Uart
.samples
= 0;
343 if(Uart
.syncBit
&& (Uart
.bitBuffer
& 8)) {
346 // the first half bit period is expected in next sample
351 else if(bit
& 1) { Uart
.syncBit
= bit
& 1; Uart
.samples
= 0; }
354 Uart
.state
= STATE_START_OF_COMMUNICATION
;
359 Uart
.OutOfCnt
= 4; // Start at 1/4, could switch to 1/256
360 Uart
.dropPosition
= 0;
369 if(Uart
.highCnt
< 8) {
378 //=============================================================================
379 // ISO 14443 Type A - Manchester
380 //=============================================================================
385 DEMOD_START_OF_COMMUNICATION
,
386 DEMOD_START_OF_COMMUNICATION2
,
387 DEMOD_START_OF_COMMUNICATION3
,
391 DEMOD_END_OF_COMMUNICATION
,
392 DEMOD_END_OF_COMMUNICATION2
,
416 static RAMFUNC
int ManchesterDecoding(int v
)
423 Demod
.buffer
= Demod
.buffer2
;
424 Demod
.buffer2
= Demod
.buffer3
;
432 if(Demod
.state
==DEMOD_UNSYNCD
) {
433 Demod
.output
[Demod
.len
] = 0xfa;
436 Demod
.posCount
= 1; // This is the first half bit period, so after syncing handle the second part
437 /* if(bit & 0x08) { Demod.syncBit = 0x08; }
439 if(bit & 0x04) { Demod.syncBit = 0x04; }
441 else if(bit & 0x04) { Demod.syncBit = 0x04; bit <<= 4; }
443 if(bit & 0x02) { Demod.syncBit = 0x02; }
445 else if(bit & 0x02) { Demod.syncBit = 0x02; bit <<= 4; }
447 if(bit & 0x01) { Demod.syncBit = 0x01; }
449 if(Demod.syncBit && (Demod.buffer & 0x08)) {
450 Demod.syncBit = 0x08;
452 // The first half bitperiod is expected in next sample
454 Demod.output[Demod.len] = 0xfb;
457 else if(bit & 0x01) { Demod.syncBit = 0x01; }
461 Demod
.syncBit
= 0x08;
468 Demod
.syncBit
= 0x04;
475 Demod
.syncBit
= 0x02;
478 if(bit
& 0x01 && Demod
.syncBit
) {
479 Demod
.syncBit
= 0x01;
484 Demod
.state
= DEMOD_START_OF_COMMUNICATION
;
485 Demod
.sub
= SUB_FIRST_HALF
;
488 Demod
.parityBits
= 0;
491 //if(trigger) LED_A_OFF(); // Not useful in this case...
492 switch(Demod
.syncBit
) {
493 case 0x08: Demod
.samples
= 3; break;
494 case 0x04: Demod
.samples
= 2; break;
495 case 0x02: Demod
.samples
= 1; break;
496 case 0x01: Demod
.samples
= 0; break;
498 // SOF must be long burst... otherwise stay unsynced!!!
499 if(!(Demod
.buffer
& Demod
.syncBit
) || !(Demod
.buffer2
& Demod
.syncBit
)) {
500 Demod
.state
= DEMOD_UNSYNCD
;
504 // SOF must be long burst... otherwise stay unsynced!!!
505 if(!(Demod
.buffer2
& Demod
.syncBit
) || !(Demod
.buffer3
& Demod
.syncBit
)) {
506 Demod
.state
= DEMOD_UNSYNCD
;
516 modulation
= bit
& Demod
.syncBit
;
517 modulation
|= ((bit
<< 1) ^ ((Demod
.buffer
& 0x08) >> 3)) & Demod
.syncBit
;
518 //modulation = ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
522 if(Demod
.posCount
==0) {
525 Demod
.sub
= SUB_FIRST_HALF
;
528 Demod
.sub
= SUB_NONE
;
533 /*(modulation && (Demod.sub == SUB_FIRST_HALF)) {
534 if(Demod.state!=DEMOD_ERROR_WAIT) {
535 Demod.state = DEMOD_ERROR_WAIT;
536 Demod.output[Demod.len] = 0xaa;
540 //else if(modulation) {
542 if(Demod
.sub
== SUB_FIRST_HALF
) {
543 Demod
.sub
= SUB_BOTH
;
546 Demod
.sub
= SUB_SECOND_HALF
;
549 else if(Demod
.sub
== SUB_NONE
) {
550 if(Demod
.state
== DEMOD_SOF_COMPLETE
) {
551 Demod
.output
[Demod
.len
] = 0x0f;
553 Demod
.parityBits
<<= 1;
554 Demod
.parityBits
^= OddByteParity
[0x0f];
555 Demod
.state
= DEMOD_UNSYNCD
;
560 Demod
.state
= DEMOD_ERROR_WAIT
;
563 /*if(Demod.state!=DEMOD_ERROR_WAIT) {
564 Demod.state = DEMOD_ERROR_WAIT;
565 Demod.output[Demod.len] = 0xaa;
570 switch(Demod
.state
) {
571 case DEMOD_START_OF_COMMUNICATION
:
572 if(Demod
.sub
== SUB_BOTH
) {
573 //Demod.state = DEMOD_MANCHESTER_D;
574 Demod
.state
= DEMOD_START_OF_COMMUNICATION2
;
576 Demod
.sub
= SUB_NONE
;
579 Demod
.output
[Demod
.len
] = 0xab;
580 Demod
.state
= DEMOD_ERROR_WAIT
;
584 case DEMOD_START_OF_COMMUNICATION2
:
585 if(Demod
.sub
== SUB_SECOND_HALF
) {
586 Demod
.state
= DEMOD_START_OF_COMMUNICATION3
;
589 Demod
.output
[Demod
.len
] = 0xab;
590 Demod
.state
= DEMOD_ERROR_WAIT
;
594 case DEMOD_START_OF_COMMUNICATION3
:
595 if(Demod
.sub
== SUB_SECOND_HALF
) {
596 // Demod.state = DEMOD_MANCHESTER_D;
597 Demod
.state
= DEMOD_SOF_COMPLETE
;
598 //Demod.output[Demod.len] = Demod.syncBit & 0xFF;
602 Demod
.output
[Demod
.len
] = 0xab;
603 Demod
.state
= DEMOD_ERROR_WAIT
;
607 case DEMOD_SOF_COMPLETE
:
608 case DEMOD_MANCHESTER_D
:
609 case DEMOD_MANCHESTER_E
:
610 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
611 // 00001111 = 1 (0 in 14443)
612 if(Demod
.sub
== SUB_SECOND_HALF
) { // SUB_FIRST_HALF
614 Demod
.shiftReg
= (Demod
.shiftReg
>> 1) ^ 0x100;
615 Demod
.state
= DEMOD_MANCHESTER_D
;
617 else if(Demod
.sub
== SUB_FIRST_HALF
) { // SUB_SECOND_HALF
619 Demod
.shiftReg
>>= 1;
620 Demod
.state
= DEMOD_MANCHESTER_E
;
622 else if(Demod
.sub
== SUB_BOTH
) {
623 Demod
.state
= DEMOD_MANCHESTER_F
;
626 Demod
.state
= DEMOD_ERROR_WAIT
;
631 case DEMOD_MANCHESTER_F
:
632 // Tag response does not need to be a complete byte!
633 if(Demod
.len
> 0 || Demod
.bitCount
> 0) {
634 if(Demod
.bitCount
> 1) { // was > 0, do not interpret last closing bit, is part of EOF
635 Demod
.shiftReg
>>= (9 - Demod
.bitCount
);
636 Demod
.output
[Demod
.len
] = Demod
.shiftReg
& 0xff;
638 // No parity bit, so just shift a 0
639 Demod
.parityBits
<<= 1;
642 Demod
.state
= DEMOD_UNSYNCD
;
646 Demod
.output
[Demod
.len
] = 0xad;
647 Demod
.state
= DEMOD_ERROR_WAIT
;
652 case DEMOD_ERROR_WAIT
:
653 Demod
.state
= DEMOD_UNSYNCD
;
657 Demod
.output
[Demod
.len
] = 0xdd;
658 Demod
.state
= DEMOD_UNSYNCD
;
662 /*if(Demod.bitCount>=9) {
663 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
666 Demod.parityBits <<= 1;
667 Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);
672 if(Demod
.bitCount
>=8) {
673 Demod
.shiftReg
>>= 1;
674 Demod
.output
[Demod
.len
] = (Demod
.shiftReg
& 0xff);
677 // FOR ISO15639 PARITY NOT SEND OTA, JUST CALCULATE IT FOR THE CLIENT
678 Demod
.parityBits
<<= 1;
679 Demod
.parityBits
^= OddByteParity
[(Demod
.shiftReg
& 0xff)];
686 Demod
.output
[Demod
.len
] = 0xBB;
688 Demod
.output
[Demod
.len
] = error
& 0xFF;
690 Demod
.output
[Demod
.len
] = 0xBB;
692 Demod
.output
[Demod
.len
] = bit
& 0xFF;
694 Demod
.output
[Demod
.len
] = Demod
.buffer
& 0xFF;
697 Demod
.output
[Demod
.len
] = Demod
.buffer2
& 0xFF;
699 Demod
.output
[Demod
.len
] = Demod
.syncBit
& 0xFF;
701 Demod
.output
[Demod
.len
] = 0xBB;
708 } // end (state != UNSYNCED)
713 //=============================================================================
714 // Finally, a `sniffer' for ISO 14443 Type A
715 // Both sides of communication!
716 //=============================================================================
718 //-----------------------------------------------------------------------------
719 // Record the sequence of commands sent by the reader to the tag, with
720 // triggering so that we start recording at the point that the tag is moved
722 //-----------------------------------------------------------------------------
723 void RAMFUNC
SnoopIClass(void)
725 // #define RECV_CMD_OFFSET 2032 // original (working as of 21/2/09) values
726 // #define RECV_RES_OFFSET 2096 // original (working as of 21/2/09) values
727 // #define DMA_BUFFER_OFFSET 2160 // original (working as of 21/2/09) values
728 // #define DMA_BUFFER_SIZE 4096 // original (working as of 21/2/09) values
729 // #define TRACE_LENGTH 2000 // original (working as of 21/2/09) values
731 // We won't start recording the frames that we acquire until we trigger;
732 // a good trigger condition to get started is probably when we see a
733 // response from the tag.
734 int triggered
= FALSE
; // FALSE to wait first for card
736 // The command (reader -> tag) that we're receiving.
737 // The length of a received command will in most cases be no more than 18 bytes.
738 // So 32 should be enough!
739 uint8_t *receivedCmd
= (((uint8_t *)BigBuf
) + RECV_CMD_OFFSET
);
740 // The response (tag -> reader) that we're receiving.
741 uint8_t *receivedResponse
= (((uint8_t *)BigBuf
) + RECV_RES_OFFSET
);
743 // As we receive stuff, we copy it from receivedCmd or receivedResponse
744 // into trace, along with its length and other annotations.
745 //uint8_t *trace = (uint8_t *)BigBuf;
747 traceLen
= 0; // uncommented to fix ISSUE 15 - gerhard - jan2011
749 // The DMA buffer, used to stream samples from the FPGA
750 int8_t *dmaBuf
= ((int8_t *)BigBuf
) + DMA_BUFFER_OFFSET
;
756 // Count of samples received so far, so that we can include timing
757 // information in the trace buffer.
761 memset(trace
, 0x44, RECV_CMD_OFFSET
);
763 // Set up the demodulator for tag -> reader responses.
764 Demod
.output
= receivedResponse
;
766 Demod
.state
= DEMOD_UNSYNCD
;
768 // Setup for the DMA.
771 lastRxCounter
= DMA_BUFFER_SIZE
;
772 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
);
774 // And the reader -> tag commands
775 memset(&Uart
, 0, sizeof(Uart
));
776 Uart
.output
= receivedCmd
;
777 Uart
.byteCntMax
= 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
778 Uart
.state
= STATE_UNSYNCD
;
780 // And put the FPGA in the appropriate mode
781 // Signal field is off with the appropriate LED
783 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_SNIFFER
);
784 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
791 // And now we loop, receiving samples.
795 int behindBy
= (lastRxCounter
- AT91C_BASE_PDC_SSC
->PDC_RCR
) &
797 if(behindBy
> maxBehindBy
) {
798 maxBehindBy
= behindBy
;
800 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy
);
804 if(behindBy
< 1) continue;
810 if(upTo
- dmaBuf
> DMA_BUFFER_SIZE
) {
811 upTo
-= DMA_BUFFER_SIZE
;
812 lastRxCounter
+= DMA_BUFFER_SIZE
;
813 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) upTo
;
814 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
823 //decbyte ^= ((smpl & 0x01) << (3 - div));
824 //decbyte ^= (((smpl & 0x01) | ((smpl & 0x02) >> 1)) << (3 - div)); // better already...
825 //decbyte ^= (((smpl & 0x01) | ((smpl & 0x02) >> 1) | ((smpl & 0x04) >> 2)) << (3 - div)); // even better...
827 decbyte
^= (1 << (3 - div
));
829 //decbyte ^= (MajorityNibble[(smpl & 0x0F)] << (3 - div));
831 // FOR READER SIDE COMMUMICATION...
832 //decbyte ^= ((smpl & 0x10) << (3 - div));
834 decbyter
^= (smpl
& 0x30);
838 if((div
+ 1) % 2 == 0) {
840 if(MillerDecoding((smpl
& 0xF0) >> 4)) {
841 rsamples
= samples
- Uart
.samples
;
844 trace
[traceLen
++] = ((rsamples
>> 0) & 0xff);
845 trace
[traceLen
++] = ((rsamples
>> 8) & 0xff);
846 trace
[traceLen
++] = ((rsamples
>> 16) & 0xff);
847 trace
[traceLen
++] = ((rsamples
>> 24) & 0xff);
848 trace
[traceLen
++] = ((Uart
.parityBits
>> 0) & 0xff);
849 trace
[traceLen
++] = ((Uart
.parityBits
>> 8) & 0xff);
850 trace
[traceLen
++] = ((Uart
.parityBits
>> 16) & 0xff);
851 trace
[traceLen
++] = ((Uart
.parityBits
>> 24) & 0xff);
852 trace
[traceLen
++] = Uart
.byteCnt
;
853 memcpy(trace
+traceLen
, receivedCmd
, Uart
.byteCnt
);
854 traceLen
+= Uart
.byteCnt
;
855 if(traceLen
> TRACE_LENGTH
) break;
857 /* And ready to receive another command. */
858 Uart
.state
= STATE_UNSYNCD
;
859 /* And also reset the demod code, which might have been */
860 /* false-triggered by the commands from the reader. */
861 Demod
.state
= DEMOD_UNSYNCD
;
870 if(ManchesterDecoding(smpl
& 0x0F)) {
871 rsamples
= samples
- Demod
.samples
;
874 // timestamp, as a count of samples
875 trace
[traceLen
++] = ((rsamples
>> 0) & 0xff);
876 trace
[traceLen
++] = ((rsamples
>> 8) & 0xff);
877 trace
[traceLen
++] = ((rsamples
>> 16) & 0xff);
878 trace
[traceLen
++] = 0x80 | ((rsamples
>> 24) & 0xff);
879 trace
[traceLen
++] = ((Demod
.parityBits
>> 0) & 0xff);
880 trace
[traceLen
++] = ((Demod
.parityBits
>> 8) & 0xff);
881 trace
[traceLen
++] = ((Demod
.parityBits
>> 16) & 0xff);
882 trace
[traceLen
++] = ((Demod
.parityBits
>> 24) & 0xff);
884 trace
[traceLen
++] = Demod
.len
;
885 memcpy(trace
+traceLen
, receivedResponse
, Demod
.len
);
886 traceLen
+= Demod
.len
;
887 if(traceLen
> TRACE_LENGTH
) break;
891 // And ready to receive another response.
892 memset(&Demod
, 0, sizeof(Demod
));
893 Demod
.output
= receivedResponse
;
894 Demod
.state
= DEMOD_UNSYNCD
;
904 DbpString("cancelled_a");
909 DbpString("COMMAND FINISHED");
911 Dbprintf("%x %x %x", maxBehindBy
, Uart
.state
, Uart
.byteCnt
);
912 Dbprintf("%x %x %x", Uart
.byteCntMax
, traceLen
, (int)Uart
.output
[0]);
915 AT91C_BASE_PDC_SSC
->PDC_PTCR
= AT91C_PDC_RXTDIS
;
916 Dbprintf("%x %x %x", maxBehindBy
, Uart
.state
, Uart
.byteCnt
);
917 Dbprintf("%x %x %x", Uart
.byteCntMax
, traceLen
, (int)Uart
.output
[0]);