[proxmark3-svn] / include / at91sam7s128.h

#include <at91sam7s512.h>

#ifndef __AT91SAM7S128_H
#define __AT91SAM7S128_H

/***************************************************************
 * Start of translation between PM3 defines and AT91 defines
 * TODO these should be replaced throughout the code at some stage
 ***************************************************************/
#define PERIPH_PIOA                                                             AT91C_ID_PIOA
#define PERIPH_ADC                                                              AT91C_ID_ADC
#define PERIPH_SPI                                                              AT91C_ID_SPI
#define PERIPH_SSC                                                              AT91C_ID_SSC
#define PERIPH_PWMC                                                             AT91C_ID_PWMC
#define PERIPH_UDP                                                              AT91C_ID_UDP
#define PERIPH_TC1                                                              AT91C_ID_TC1

#define SSC_BASE                                                                AT91C_BASE_SSC

#define WDT_CONTROL                                                             AT91C_BASE_WDTC->WDTC_WDCR

#define PWM_ENABLE                                                              AT91C_BASE_PWMC->PWMC_ENA

// TODO WARNING these PWM defines MUST be replaced in the code ASAP before
// someone starts using a value of x other than that selected below
#define PWM_CH_PERIOD(x)                                                AT91C_BASE_PWMC_CH0->PWMC_CPRDR
#define PWM_CH_COUNTER(x)                                               AT91C_BASE_PWMC_CH0->PWMC_CCNTR
#define PWM_CH_MODE(x)                                                  AT91C_BASE_PWMC_CH0->PWMC_CMR
#define PWM_CH_DUTY_CYCLE(x)                                    AT91C_BASE_PWMC_CH0->PWMC_CDTYR

#define PDC_RX_POINTER(x)                                               AT91C_BASE_PDC_SSC->PDC_RPR
#define PDC_RX_COUNTER(x)                                               AT91C_BASE_PDC_SSC->PDC_RCR
#define PDC_RX_NEXT_POINTER(x)                                  AT91C_BASE_PDC_SSC->PDC_RNPR
#define PDC_RX_NEXT_COUNTER(x)                                  AT91C_BASE_PDC_SSC->PDC_RNCR
#define PDC_CONTROL(x)                                                  AT91C_BASE_PDC_SSC->PDC_PTCR
// End WARNING

#define DBGU_CIDR                                                               AT91C_BASE_DBGU->DBGU_CIDR

#define RSTC_CONTROL                                                    AT91C_BASE_RSTC->RSTC_RCR
#define RSTC_STATUS                                                             AT91C_BASE_RSTC->RSTC_RSR

#define MC_FLASH_COMMAND                                                AT91C_BASE_EFC0->EFC_FCR
#define MC_FLASH_MODE0                                                  AT91C_BASE_EFC0->EFC_FMR
#define MC_FLASH_MODE1                                                  AT91C_BASE_EFC1->EFC_FMR
#define MC_FLASH_STATUS                                                 AT91C_BASE_EFC0->EFC_FSR

#define ADC_CONTROL                                                             AT91C_BASE_ADC->ADC_CR
#define ADC_MODE                                                                AT91C_BASE_ADC->ADC_MR
#define ADC_CHANNEL_ENABLE                                              AT91C_BASE_ADC->ADC_CHER
#define ADC_STATUS                                                              AT91C_BASE_ADC->ADC_SR
#define ADC_CHANNEL_DATA(x)                                             AT91C_BASE_ADC->ADC_CDR[x]

#define PIO_ENABLE                                                              AT91C_BASE_PIOA->PIO_PER
#define PIO_DISABLE                                                             AT91C_BASE_PIOA->PIO_PDR
#define PIO_OUTPUT_ENABLE                                               AT91C_BASE_PIOA->PIO_OER
#define PIO_OUTPUT_DISABLE                                              AT91C_BASE_PIOA->PIO_ODR
#define PIO_OUTPUT_DATA_SET                                             AT91C_BASE_PIOA->PIO_SODR
#define PIO_OUTPUT_DATA_CLEAR                                   AT91C_BASE_PIOA->PIO_CODR
#define PIO_PIN_DATA_STATUS                                             AT91C_BASE_PIOA->PIO_PDSR
#define PIO_NO_PULL_UP_ENABLE                                   AT91C_BASE_PIOA->PIO_PPUDR
#define PIO_NO_PULL_UP_DISABLE                                  AT91C_BASE_PIOA->PIO_PPUER
#define PIO_PERIPHERAL_B_SEL                                    AT91C_BASE_PIOA->PIO_BSR
#define PIO_PERIPHERAL_A_SEL                                    AT91C_BASE_PIOA->PIO_ASR

#define PMC_SYS_CLK_ENABLE                                              AT91C_BASE_PMC->PMC_SCER
#define PMC_PERIPHERAL_CLK_ENABLE                               AT91C_BASE_PMC->PMC_PCER
#define PMC_MAIN_OSCILLATOR                                             AT91C_BASE_PMC->PMC_MOR
#define PMC_PLL                                                                 AT91C_BASE_PMC->PMC_PLLR
#define PMC_MASTER_CLK                                                  AT91C_BASE_PMC->PMC_MCKR
#define PMC_PROGRAMMABLE_CLK_0                                  AT91C_BASE_PMC->PMC_PCKR[0]
#define PMC_INTERRUPT_STATUS                                    AT91C_BASE_PMC->PMC_SR

#define SSC_CONTROL                                                             AT91C_BASE_SSC->SSC_CR
#define SSC_CLOCK_DIVISOR                                               AT91C_BASE_SSC->SSC_CMR
#define SSC_RECEIVE_CLOCK_MODE                                  AT91C_BASE_SSC->SSC_RCMR
#define SSC_RECEIVE_FRAME_MODE                                  AT91C_BASE_SSC->SSC_RFMR
#define SSC_TRANSMIT_CLOCK_MODE                                 AT91C_BASE_SSC->SSC_TCMR
#define SSC_TRANSMIT_FRAME_MODE                                 AT91C_BASE_SSC->SSC_TFMR
#define SSC_RECEIVE_HOLDING                                             AT91C_BASE_SSC->SSC_RHR
#define SSC_TRANSMIT_HOLDING                                    AT91C_BASE_SSC->SSC_THR
#define SSC_STATUS                                                              AT91C_BASE_SSC->SSC_SR

#define SPI_CONTROL                                                             AT91C_BASE_SPI->SPI_CR
#define SPI_MODE                                                                AT91C_BASE_SPI->SPI_MR
#define SPI_TX_DATA                                                             AT91C_BASE_SPI->SPI_TDR
#define SPI_STATUS                                                              AT91C_BASE_SPI->SPI_SR
#define SPI_FOR_CHIPSEL_0                                               AT91C_BASE_SPI->SPI_CSR[0]
#define SPI_FOR_CHIPSEL_1                                               AT91C_BASE_SPI->SPI_CSR[1]
#define SPI_FOR_CHIPSEL_2                                               AT91C_BASE_SPI->SPI_CSR[2]
#define SPI_FOR_CHIPSEL_3                                               AT91C_BASE_SPI->SPI_CSR[3]

#define TC1_CCR                                                                 AT91C_BASE_TC1->TC_CCR
#define TC1_CMR                                                                 AT91C_BASE_TC1->TC_CMR
#define TC1_CV                                                                  AT91C_BASE_TC1->TC_CV
#define TC1_RA                                                                  AT91C_BASE_TC1->TC_RA
#define TC1_SR                                                                  AT91C_BASE_TC1->TC_SR

#define PDC_RX_ENABLE                                                   AT91C_PDC_RXTEN
#define PDC_RX_DISABLE                                                  AT91C_PDC_RXTDIS

#define TC_CMR_ETRGEDG_RISING                                   AT91C_TC_ETRGEDG_RISING
#define TC_CMR_ABETRG                                                   AT91C_TC_ABETRG
#define TC_CMR_LDRA_RISING                                              AT91C_TC_LDRA_RISING
#define TC_CMR_LDRB_RISING                                              AT91C_TC_LDRB_RISING
#define TC_CCR_CLKEN                                                    AT91C_TC_CLKEN
#define TC_CCR_SWTRG                                                    AT91C_TC_SWTRG
#define TC_SR_LDRAS                                                             AT91C_TC_LDRAS
#define TC_CMR_ETRGEDG                                                  AT91C_TC_ETRGEDG
#define TC_CCR_CLKDIS                                                   AT91C_TC_CLKDIS

#define ADC_CONTROL_RESET                                               AT91C_ADC_SWRST
#define ADC_CONTROL_START                                               AT91C_ADC_START

#define SPI_CONTROL_ENABLE                                              AT91C_SPI_SPIEN
#define SPI_CONTROL_LAST_TRANSFER                               AT91C_SPI_LASTXFER
#define SPI_CONTROL_RESET                                               AT91C_SPI_SWRST
#define SPI_CONTROL_DISABLE                                             AT91C_SPI_SPIDIS
#define SPI_STATUS_TX_EMPTY                                             AT91C_SPI_TXEMPTY

#define SSC_CONTROL_RX_ENABLE                                   AT91C_SSC_RXEN
#define SSC_CONTROL_TX_ENABLE                                   AT91C_SSC_TXEN
#define SSC_FRAME_MODE_MSB_FIRST                                AT91C_SSC_MSBF
#define SSC_CONTROL_RESET                                               AT91C_SSC_SWRST
#define SSC_STATUS_TX_READY                                             AT91C_SSC_TXRDY
#define SSC_STATUS_RX_READY                                             AT91C_SSC_RXRDY

#define FCMD_WRITE_PAGE                                                 AT91C_MC_FCMD_START_PROG
#define FLASH_PAGE_SIZE_BYTES                                   AT91C_IFLASH_PAGE_SIZE

#define RST_CONTROL_PROCESSOR_RESET                             AT91C_RSTC_PROCRST
#define RST_STATUS_TYPE_MASK                                    AT91C_RSTC_RSTTYP
#define RST_STATUS_TYPE_WATCHDOG                                AT91C_RSTC_RSTTYP_WATCHDOG
#define RST_STATUS_TYPE_SOFTWARE                                AT91C_RSTC_RSTTYP_SOFTWARE
#define RST_STATUS_TYPE_USER                                    AT91C_RSTC_RSTTYP_USER

#define PMC_SYS_CLK_PROCESSOR_CLK                               AT91C_PMC_PCK
#define PMC_SYS_CLK_UDP_CLK                                             AT91C_PMC_UDP
#define PMC_CLK_SELECTION_PLL_CLOCK                             AT91C_PMC_CSS_PLL_CLK
#define PMC_CLK_PRESCALE_DIV_4                                  AT91C_PMC_PRES_CLK_4
#define PMC_SYS_CLK_PROGRAMMABLE_CLK_0                  AT91C_PMC_PCK0

#define UDP_INTERRUPT_STATUS                                    AT91C_BASE_UDP->UDP_ISR
#define UDP_INTERRUPT_CLEAR                                             AT91C_BASE_UDP->UDP_ICR
#define UDP_FUNCTION_ADDR                                               AT91C_BASE_UDP->UDP_FADDR
#define UDP_RESET_ENDPOINT                                              AT91C_BASE_UDP->UDP_RSTEP
#define UDP_GLOBAL_STATE                                                AT91C_BASE_UDP->UDP_GLBSTATE
#define UDP_ENDPOINT_CSR(x)                                             AT91C_BASE_UDP->UDP_CSR[x]
#define UDP_ENDPOINT_FIFO(x)                                    AT91C_BASE_UDP->UDP_FDR[x]

#define UDP_CSR_CONTROL_DATA_DIR                                AT91C_UDP_DIR
#define UDP_CSR_ENABLE_EP                                               AT91C_UDP_EPEDS
#define UDP_CSR_EPTYPE_CONTROL                                  AT91C_UDP_EPTYPE_CTRL
#define UDP_CSR_EPTYPE_INTERRUPT_IN                             AT91C_UDP_EPTYPE_INT_IN
#define UDP_CSR_EPTYPE_INTERRUPT_OUT                    AT91C_UDP_EPTYPE_INT_OUT
#define UDP_CSR_FORCE_STALL                                             AT91C_UDP_FORCESTALL
#define UDP_CSR_RX_HAVE_READ_SETUP_DATA                 AT91C_UDP_RXSETUP
#define UDP_CSR_RX_PACKET_RECEIVED_BANK_0               AT91C_UDP_RX_DATA_BK0
#define UDP_CSR_RX_PACKET_RECEIVED_BANK_1               AT91C_UDP_RX_DATA_BK1
#define UDP_CSR_STALL_SENT                                              AT91C_UDP_STALLSENT
#define UDP_CSR_TX_PACKET                                               AT91C_UDP_TXPKTRDY
#define UDP_CSR_TX_PACKET_ACKED                                 AT91C_UDP_TXCOMP

#define UDP_FUNCTION_ADDR_ENABLED                               AT91C_UDP_FEN
#define UDP_GLOBAL_STATE_ADDRESSED                              AT91C_UDP_FADDEN
#define UDP_GLOBAL_STATE_CONFIGURED                             AT91C_UDP_CONFG
#define UDP_INTERRUPT_END_OF_BUS_RESET                  AT91C_UDP_ENDBUSRES
/***************************************************************
 * end of translation between PM3 defines and AT91 defines
 ***************************************************************/

/***************************************************************
 * the defines below this line have no AT91 equivalents and can
 * be ideally moved to proxmark3.h
 ***************************************************************/
#define WDT_HIT()                                                               WDT_CONTROL = 0xa5000001

#define PWM_CH_MODE_PRESCALER(x)                                ((x)<<0)
#define PWM_CHANNEL(x)                                                  (1<<(x))

#define TC_CMR_TCCLKS_TIMER_CLOCK1                              (0<<0)

#define ADC_CHAN_LF                                                             4
#define ADC_CHAN_HF                                                             5
#define ADC_MODE_PRESCALE(x)                                    ((x)<<8)
#define ADC_MODE_STARTUP_TIME(x)                                ((x)<<16)
#define ADC_MODE_SAMPLE_HOLD_TIME(x)                    ((x)<<24)
#define ADC_CHANNEL(x)                                                  (1<<(x))
#define ADC_END_OF_CONVERSION(x)                                (1<<(x))

#define SSC_CLOCK_MODE_START(x)                                 ((x)<<8)
#define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x)    ((x)<<8)
#define SSC_CLOCK_MODE_SELECT(x)                                ((x)<<0)
#define SSC_FRAME_MODE_BITS_IN_WORD(x)                  (((x)-1)<<0)

#define MC_FLASH_COMMAND_KEY                                    ((0x5A)<<24)
#define MC_FLASH_STATUS_READY                                   (1<<0)
#define MC_FLASH_MODE_FLASH_WAIT_STATES(x)              ((x)<<8)
#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x)              ((x)<<16)
#define MC_FLASH_COMMAND_PAGEN(x)                               ((x)<<8)

#define RST_CONTROL_KEY                                                 (0xA5<<24)

#define PMC_MAIN_OSCILLATOR_ENABLE                              (1<<0)
#define PMC_MAIN_OSCILLATOR_STABILIZED                  (1<<0)
#define PMC_MAIN_OSCILLATOR_PLL_LOCK                    (1<<2)
#define PMC_MAIN_OSCILLATOR_MCK_READY                   (1<<3)

#define PMC_PLL_DIVISOR(x)                                              (x)
#define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x)    ((x)<<8)
#define PMC_CLK_PRESCALE_DIV_2                                  (1<<2)
#define PMC_PLL_MULTIPLIER(x)                                   (((x)-1)<<16)
#define PMC_PLL_COUNT_BEFORE_LOCK(x)                    ((x)<<8)
#define PMC_PLL_FREQUENCY_RANGE(x)                              ((x)<<14)
#define PMC_PLL_USB_DIVISOR(x)                                  ((x)<<28)

#define UDP_INTERRUPT_ENDPOINT(x)                               (1<<(x))
#define UDP_CSR_BYTES_RECEIVED(x)                               (((x) >> 16) & 0x7ff)

#endif