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   1 //-----------------------------------------------------------------------------
   2 // For reading TI tags, we need to place the FPGA in pass through mode
   3 // and pass everything through to the ARM
   4 //-----------------------------------------------------------------------------
   5
   6 module lo_passthru(
   7     pck0, ck_1356meg, ck_1356megb,
   8     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
   9     adc_d, adc_clk,
  10     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  11     cross_hi, cross_lo,
  12     dbg
  13 );
  14     input pck0, ck_1356meg, ck_1356megb;
  15     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  16     input [7:0] adc_d;
  17     output adc_clk;
  18     input ssp_dout;
  19     output ssp_frame, ssp_din, ssp_clk;
  20     input cross_hi, cross_lo;
  21     output dbg;
  22
  23 // No logic, straight through.
  24
  25 assign pwr_oe3 = 1'b0;
  26 assign pwr_oe1 = 1'b1;
  27 assign pwr_oe2 = 1'b1;
  28 assign pwr_oe4 = 1'b1;
  29 assign pwr_lo = 1'b0;
  30 assign pwr_hi = 1'b0;
  31 assign adc_clk = 1'b0;
  32 assign ssp_din = cross_lo;
  33 assign dbg = cross_lo;
  34
  35 endmodule