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FIXED: lf t55xx fsk now demods but only to binary.
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "../include/proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "../include/hitag2.h"
15 #include "../common/crc16.h"
16 #include "string.h"
17 #include "crapto1.h"
18 #include "mifareutil.h"
19
20 void LFSetupFPGAForADC(int divisor, bool lf_field)
21 {
22 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
23 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
24 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
25 else if (divisor == 0)
26 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
27 else
28 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
29
30 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
31
32 // Connect the A/D to the peak-detected low-frequency path.
33 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
34
35 // Give it a bit of time for the resonant antenna to settle.
36 SpinDelay(150);
37
38 // Now set up the SSC to get the ADC samples that are now streaming at us.
39 FpgaSetupSsc();
40 }
41
42 void AcquireRawAdcSamples125k(int divisor)
43 {
44 LFSetupFPGAForADC(divisor, true);
45 DoAcquisition125k();
46 }
47
48 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
49 {
50 LFSetupFPGAForADC(divisor, false);
51 DoAcquisition125k_threshold(trigger_threshold);
52 }
53
54 // split into two routines so we can avoid timing issues after sending commands //
55 void DoAcquisition125k_internal(int trigger_threshold, bool silent)
56 {
57 uint8_t *dest = mifare_get_bigbufptr();
58 int n = 8000;
59 int i;
60
61 memset(dest, 0x00, n);
62 i = 0;
63 for(;;) {
64 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
65 AT91C_BASE_SSC->SSC_THR = 0x43;
66 LED_D_ON();
67 }
68 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
69 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
70 LED_D_OFF();
71 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
72 continue;
73 else
74 trigger_threshold = -1;
75 if (++i >= n) break;
76 }
77 }
78 if (!silent){
79 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
80 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
81 }
82 }
83 void DoAcquisition125k_threshold(int trigger_threshold) {
84 DoAcquisition125k_internal(trigger_threshold, true);
85 }
86 void DoAcquisition125k() {
87 DoAcquisition125k_internal(-1, true);
88 }
89
90 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
91 {
92 int at134khz;
93
94 /* Make sure the tag is reset */
95 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
96 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
97 SpinDelay(2500);
98
99 // see if 'h' was specified
100 if (command[strlen((char *) command) - 1] == 'h')
101 at134khz = TRUE;
102 else
103 at134khz = FALSE;
104
105 if (at134khz)
106 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
107 else
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
109
110 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
111
112 // Give it a bit of time for the resonant antenna to settle.
113 SpinDelay(50);
114 // And a little more time for the tag to fully power up
115 SpinDelay(2000);
116
117 // Now set up the SSC to get the ADC samples that are now streaming at us.
118 FpgaSetupSsc();
119
120 // now modulate the reader field
121 while(*command != '\0' && *command != ' ') {
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
123 LED_D_OFF();
124 SpinDelayUs(delay_off);
125 if (at134khz)
126 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
127 else
128 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
129
130 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
131 LED_D_ON();
132 if(*(command++) == '0')
133 SpinDelayUs(period_0);
134 else
135 SpinDelayUs(period_1);
136 }
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
138 LED_D_OFF();
139 SpinDelayUs(delay_off);
140 if (at134khz)
141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
142 else
143 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
144
145 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
146
147 // now do the read
148 DoAcquisition125k();
149 }
150
151 /* blank r/w tag data stream
152 ...0000000000000000 01111111
153 1010101010101010101010101010101010101010101010101010101010101010
154 0011010010100001
155 01111111
156 101010101010101[0]000...
157
158 [5555fe852c5555555555555555fe0000]
159 */
160 void ReadTItag(void)
161 {
162 // some hardcoded initial params
163 // when we read a TI tag we sample the zerocross line at 2Mhz
164 // TI tags modulate a 1 as 16 cycles of 123.2Khz
165 // TI tags modulate a 0 as 16 cycles of 134.2Khz
166 #define FSAMPLE 2000000
167 #define FREQLO 123200
168 #define FREQHI 134200
169
170 signed char *dest = (signed char *)BigBuf;
171 int n = sizeof(BigBuf);
172 // int *dest = GraphBuffer;
173 // int n = GraphTraceLen;
174
175 // 128 bit shift register [shift3:shift2:shift1:shift0]
176 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
177
178 int i, cycles=0, samples=0;
179 // how many sample points fit in 16 cycles of each frequency
180 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
181 // when to tell if we're close enough to one freq or another
182 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
183
184 // TI tags charge at 134.2Khz
185 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
186 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
187
188 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
189 // connects to SSP_DIN and the SSP_DOUT logic level controls
190 // whether we're modulating the antenna (high)
191 // or listening to the antenna (low)
192 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
193
194 // get TI tag data into the buffer
195 AcquireTiType();
196
197 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
198
199 for (i=0; i<n-1; i++) {
200 // count cycles by looking for lo to hi zero crossings
201 if ( (dest[i]<0) && (dest[i+1]>0) ) {
202 cycles++;
203 // after 16 cycles, measure the frequency
204 if (cycles>15) {
205 cycles=0;
206 samples=i-samples; // number of samples in these 16 cycles
207
208 // TI bits are coming to us lsb first so shift them
209 // right through our 128 bit right shift register
210 shift0 = (shift0>>1) | (shift1 << 31);
211 shift1 = (shift1>>1) | (shift2 << 31);
212 shift2 = (shift2>>1) | (shift3 << 31);
213 shift3 >>= 1;
214
215 // check if the cycles fall close to the number
216 // expected for either the low or high frequency
217 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
218 // low frequency represents a 1
219 shift3 |= (1<<31);
220 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
221 // high frequency represents a 0
222 } else {
223 // probably detected a gay waveform or noise
224 // use this as gaydar or discard shift register and start again
225 shift3 = shift2 = shift1 = shift0 = 0;
226 }
227 samples = i;
228
229 // for each bit we receive, test if we've detected a valid tag
230
231 // if we see 17 zeroes followed by 6 ones, we might have a tag
232 // remember the bits are backwards
233 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
234 // if start and end bytes match, we have a tag so break out of the loop
235 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
236 cycles = 0xF0B; //use this as a flag (ugly but whatever)
237 break;
238 }
239 }
240 }
241 }
242 }
243
244 // if flag is set we have a tag
245 if (cycles!=0xF0B) {
246 DbpString("Info: No valid tag detected.");
247 } else {
248 // put 64 bit data into shift1 and shift0
249 shift0 = (shift0>>24) | (shift1 << 8);
250 shift1 = (shift1>>24) | (shift2 << 8);
251
252 // align 16 bit crc into lower half of shift2
253 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
254
255 // if r/w tag, check ident match
256 if ( shift3&(1<<15) ) {
257 DbpString("Info: TI tag is rewriteable");
258 // only 15 bits compare, last bit of ident is not valid
259 if ( ((shift3>>16)^shift0)&0x7fff ) {
260 DbpString("Error: Ident mismatch!");
261 } else {
262 DbpString("Info: TI tag ident is valid");
263 }
264 } else {
265 DbpString("Info: TI tag is readonly");
266 }
267
268 // WARNING the order of the bytes in which we calc crc below needs checking
269 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
270 // bytes in reverse or something
271 // calculate CRC
272 uint32_t crc=0;
273
274 crc = update_crc16(crc, (shift0)&0xff);
275 crc = update_crc16(crc, (shift0>>8)&0xff);
276 crc = update_crc16(crc, (shift0>>16)&0xff);
277 crc = update_crc16(crc, (shift0>>24)&0xff);
278 crc = update_crc16(crc, (shift1)&0xff);
279 crc = update_crc16(crc, (shift1>>8)&0xff);
280 crc = update_crc16(crc, (shift1>>16)&0xff);
281 crc = update_crc16(crc, (shift1>>24)&0xff);
282
283 Dbprintf("Info: Tag data: %x%08x, crc=%x",
284 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
285 if (crc != (shift2&0xffff)) {
286 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
287 } else {
288 DbpString("Info: CRC is good");
289 }
290 }
291 }
292
293 void WriteTIbyte(uint8_t b)
294 {
295 int i = 0;
296
297 // modulate 8 bits out to the antenna
298 for (i=0; i<8; i++)
299 {
300 if (b&(1<<i)) {
301 // stop modulating antenna
302 LOW(GPIO_SSC_DOUT);
303 SpinDelayUs(1000);
304 // modulate antenna
305 HIGH(GPIO_SSC_DOUT);
306 SpinDelayUs(1000);
307 } else {
308 // stop modulating antenna
309 LOW(GPIO_SSC_DOUT);
310 SpinDelayUs(300);
311 // modulate antenna
312 HIGH(GPIO_SSC_DOUT);
313 SpinDelayUs(1700);
314 }
315 }
316 }
317
318 void AcquireTiType(void)
319 {
320 int i, j, n;
321 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
322 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
323 #define TIBUFLEN 1250
324
325 // clear buffer
326 memset(BigBuf,0,sizeof(BigBuf));
327
328 // Set up the synchronous serial port
329 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
330 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
331
332 // steal this pin from the SSP and use it to control the modulation
333 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
334 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
335
336 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
337 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
338
339 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
340 // 48/2 = 24 MHz clock must be divided by 12
341 AT91C_BASE_SSC->SSC_CMR = 12;
342
343 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
344 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
345 AT91C_BASE_SSC->SSC_TCMR = 0;
346 AT91C_BASE_SSC->SSC_TFMR = 0;
347
348 LED_D_ON();
349
350 // modulate antenna
351 HIGH(GPIO_SSC_DOUT);
352
353 // Charge TI tag for 50ms.
354 SpinDelay(50);
355
356 // stop modulating antenna and listen
357 LOW(GPIO_SSC_DOUT);
358
359 LED_D_OFF();
360
361 i = 0;
362 for(;;) {
363 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
364 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
365 i++; if(i >= TIBUFLEN) break;
366 }
367 WDT_HIT();
368 }
369
370 // return stolen pin to SSP
371 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
372 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
373
374 char *dest = (char *)BigBuf;
375 n = TIBUFLEN*32;
376 // unpack buffer
377 for (i=TIBUFLEN-1; i>=0; i--) {
378 for (j=0; j<32; j++) {
379 if(BigBuf[i] & (1 << j)) {
380 dest[--n] = 1;
381 } else {
382 dest[--n] = -1;
383 }
384 }
385 }
386 }
387
388 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
389 // if crc provided, it will be written with the data verbatim (even if bogus)
390 // if not provided a valid crc will be computed from the data and written.
391 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
392 {
393 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
394 if(crc == 0) {
395 crc = update_crc16(crc, (idlo)&0xff);
396 crc = update_crc16(crc, (idlo>>8)&0xff);
397 crc = update_crc16(crc, (idlo>>16)&0xff);
398 crc = update_crc16(crc, (idlo>>24)&0xff);
399 crc = update_crc16(crc, (idhi)&0xff);
400 crc = update_crc16(crc, (idhi>>8)&0xff);
401 crc = update_crc16(crc, (idhi>>16)&0xff);
402 crc = update_crc16(crc, (idhi>>24)&0xff);
403 }
404 Dbprintf("Writing to tag: %x%08x, crc=%x",
405 (unsigned int) idhi, (unsigned int) idlo, crc);
406
407 // TI tags charge at 134.2Khz
408 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
409 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
410 // connects to SSP_DIN and the SSP_DOUT logic level controls
411 // whether we're modulating the antenna (high)
412 // or listening to the antenna (low)
413 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
414 LED_A_ON();
415
416 // steal this pin from the SSP and use it to control the modulation
417 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
418 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
419
420 // writing algorithm:
421 // a high bit consists of a field off for 1ms and field on for 1ms
422 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
423 // initiate a charge time of 50ms (field on) then immediately start writing bits
424 // start by writing 0xBB (keyword) and 0xEB (password)
425 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
426 // finally end with 0x0300 (write frame)
427 // all data is sent lsb firts
428 // finish with 15ms programming time
429
430 // modulate antenna
431 HIGH(GPIO_SSC_DOUT);
432 SpinDelay(50); // charge time
433
434 WriteTIbyte(0xbb); // keyword
435 WriteTIbyte(0xeb); // password
436 WriteTIbyte( (idlo )&0xff );
437 WriteTIbyte( (idlo>>8 )&0xff );
438 WriteTIbyte( (idlo>>16)&0xff );
439 WriteTIbyte( (idlo>>24)&0xff );
440 WriteTIbyte( (idhi )&0xff );
441 WriteTIbyte( (idhi>>8 )&0xff );
442 WriteTIbyte( (idhi>>16)&0xff );
443 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
444 WriteTIbyte( (crc )&0xff ); // crc lo
445 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
446 WriteTIbyte(0x00); // write frame lo
447 WriteTIbyte(0x03); // write frame hi
448 HIGH(GPIO_SSC_DOUT);
449 SpinDelay(50); // programming time
450
451 LED_A_OFF();
452
453 // get TI tag data into the buffer
454 AcquireTiType();
455
456 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
457 DbpString("Now use tiread to check");
458 }
459
460 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
461 {
462 int i;
463 uint8_t *tab = (uint8_t *)BigBuf;
464
465 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
466 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
467
468 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
469
470 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
471 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
472
473 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
474 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
475
476 i = 0;
477 for(;;) {
478 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
479 if(BUTTON_PRESS()) {
480 DbpString("Stopped");
481 return;
482 }
483 WDT_HIT();
484 }
485
486 if (ledcontrol)
487 LED_D_ON();
488
489 if(tab[i])
490 OPEN_COIL();
491 else
492 SHORT_COIL();
493
494 if (ledcontrol)
495 LED_D_OFF();
496
497 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
498 if(BUTTON_PRESS()) {
499 DbpString("Stopped");
500 return;
501 }
502 WDT_HIT();
503 }
504
505 i++;
506 if(i == period) {
507 i = 0;
508 if (gap) {
509 SHORT_COIL();
510 SpinDelayUs(gap);
511 }
512 }
513 }
514 }
515
516 #define DEBUG_FRAME_CONTENTS 1
517 void SimulateTagLowFrequencyBidir(int divisor, int t0)
518 {
519 }
520
521 // compose fc/8 fc/10 waveform
522 static void fc(int c, int *n) {
523 uint8_t *dest = (uint8_t *)BigBuf;
524 int idx;
525
526 // for when we want an fc8 pattern every 4 logical bits
527 if(c==0) {
528 dest[((*n)++)]=1;
529 dest[((*n)++)]=1;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 dest[((*n)++)]=0;
533 dest[((*n)++)]=0;
534 dest[((*n)++)]=0;
535 dest[((*n)++)]=0;
536 }
537 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
538 if(c==8) {
539 for (idx=0; idx<6; idx++) {
540 dest[((*n)++)]=1;
541 dest[((*n)++)]=1;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 dest[((*n)++)]=0;
546 dest[((*n)++)]=0;
547 dest[((*n)++)]=0;
548 }
549 }
550
551 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
552 if(c==10) {
553 for (idx=0; idx<5; idx++) {
554 dest[((*n)++)]=1;
555 dest[((*n)++)]=1;
556 dest[((*n)++)]=1;
557 dest[((*n)++)]=0;
558 dest[((*n)++)]=0;
559 dest[((*n)++)]=0;
560 dest[((*n)++)]=0;
561 dest[((*n)++)]=0;
562 dest[((*n)++)]=0;
563 dest[((*n)++)]=0;
564 }
565 }
566 }
567
568 // prepare a waveform pattern in the buffer based on the ID given then
569 // simulate a HID tag until the button is pressed
570 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
571 {
572 int n=0, i=0;
573 /*
574 HID tag bitstream format
575 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
576 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
577 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
578 A fc8 is inserted before every 4 bits
579 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
580 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
581 */
582
583 if (hi>0xFFF) {
584 DbpString("Tags can only have 44 bits.");
585 return;
586 }
587 fc(0,&n);
588 // special start of frame marker containing invalid bit sequences
589 fc(8, &n); fc(8, &n); // invalid
590 fc(8, &n); fc(10, &n); // logical 0
591 fc(10, &n); fc(10, &n); // invalid
592 fc(8, &n); fc(10, &n); // logical 0
593
594 WDT_HIT();
595 // manchester encode bits 43 to 32
596 for (i=11; i>=0; i--) {
597 if ((i%4)==3) fc(0,&n);
598 if ((hi>>i)&1) {
599 fc(10, &n); fc(8, &n); // low-high transition
600 } else {
601 fc(8, &n); fc(10, &n); // high-low transition
602 }
603 }
604
605 WDT_HIT();
606 // manchester encode bits 31 to 0
607 for (i=31; i>=0; i--) {
608 if ((i%4)==3) fc(0,&n);
609 if ((lo>>i)&1) {
610 fc(10, &n); fc(8, &n); // low-high transition
611 } else {
612 fc(8, &n); fc(10, &n); // high-low transition
613 }
614 }
615
616 if (ledcontrol)
617 LED_A_ON();
618 SimulateTagLowFrequency(n, 0, ledcontrol);
619
620 if (ledcontrol)
621 LED_A_OFF();
622 }
623
624 size_t fsk_demod(uint8_t * dest, size_t size)
625 {
626 uint32_t last_transition = 0;
627 uint32_t idx = 1;
628
629 // we don't care about actual value, only if it's more or less than a
630 // threshold essentially we capture zero crossings for later analysis
631 uint8_t threshold_value = 127;
632
633 // sync to first lo-hi transition, and threshold
634
635 //Need to threshold first sample
636 dest[0] = (dest[0] < threshold_value) ? 0 : 1;
637
638 size_t numBits = 0;
639 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
640 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
641 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
642 for(idx = 1; idx < size; idx++) {
643 // threshold current value
644 dest[idx] = (dest[idx] < threshold_value) ? 0 : 1;
645
646 // Check for 0->1 transition
647 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
648
649 dest[numBits] = (idx-last_transition < 9) ? 1 : 0;
650 last_transition = idx;
651 numBits++;
652 }
653 }
654 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
655 }
656
657
658 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
659 {
660 uint8_t lastval=dest[0];
661 uint32_t idx=0;
662 size_t numBits=0;
663 uint32_t n=1;
664
665 for( idx=1; idx < size; idx++) {
666
667 if (dest[idx]==lastval) {
668 n++;
669 continue;
670 }
671 //if lastval was 1, we have a 1->0 crossing
672 if ( dest[idx-1] ) {
673 n=(n+1) / h2l_crossing_value;
674 } else {// 0->1 crossing
675 n=(n+1) / l2h_crossing_value;
676 }
677 if (n == 0) n = 1;
678
679 if(n < maxConsequtiveBits)
680 {
681 memset(dest+numBits, dest[idx-1] , n);
682 numBits += n;
683 }
684 n=0;
685 lastval=dest[idx];
686 }//end for
687
688 return numBits;
689
690 }
691 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
692 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
693 {
694 uint8_t *dest = (uint8_t *)BigBuf;
695
696 size_t size=0,idx=0; //, found=0;
697 uint32_t hi2=0, hi=0, lo=0;
698
699
700 while(!BUTTON_PRESS()) {
701
702 // Configure to go in 125Khz listen mode
703 LFSetupFPGAForADC(0,true);
704
705 WDT_HIT();
706 if (ledcontrol) LED_A_ON();
707
708 DoAcquisition125k();
709 size = sizeof(BigBuf);
710
711 // FSK demodulator
712 size = fsk_demod(dest, size);
713 WDT_HIT();
714
715 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
716 // 1->0 : fc/8 in sets of 6
717 // 0->1 : fc/10 in sets of 5
718 size = aggregate_bits(dest,size, 6,5,5);
719
720 WDT_HIT();
721
722 // final loop, go over previously decoded manchester data and decode into usable tag ID
723 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
724 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
725 int numshifts = 0;
726 idx = 0;
727 while( idx + sizeof(frame_marker_mask) < size) {
728 // search for a start of frame marker
729 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
730 { // frame marker found
731 idx+=sizeof(frame_marker_mask);
732
733 while(dest[idx] != dest[idx+1] && idx < size-2)
734 { // Keep going until next frame marker (or error)
735 // Shift in a bit. Start by shifting high registers
736 hi2=(hi2<<1)|(hi>>31);
737 hi=(hi<<1)|(lo>>31);
738 //Then, shift in a 0 or one into low
739 if (dest[idx] && !dest[idx+1]) // 1 0
740 lo=(lo<<1)|0;
741 else // 0 1
742 lo=(lo<<1)|
743 1;
744 numshifts ++;
745 idx += 2;
746 }
747 //Dbprintf("Num shifts: %d ", numshifts);
748 // Hopefully, we read a tag and hit upon the next frame marker
749 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
750 {
751 if (hi2 != 0){
752 Dbprintf("TAG ID: %x%08x%08x (%d)",
753 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
754 }
755 else {
756 Dbprintf("TAG ID: %x%08x (%d)",
757 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
758 }
759 }
760
761 // reset
762 hi2 = hi = lo = 0;
763 numshifts = 0;
764 }else
765 {
766 idx++;
767 }
768 }
769 WDT_HIT();
770
771 }
772 DbpString("Stopped");
773 if (ledcontrol) LED_A_OFF();
774 }
775
776 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
777 {
778 uint32_t num = 0;
779 for(int i = 0 ; i < numbits ; i++)
780 {
781 num = (num << 1) | (*src);
782 src++;
783 }
784 return num;
785 }
786
787
788 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
789 {
790 uint8_t *dest = (uint8_t *)BigBuf;
791
792 size_t size=0, idx=0;
793 uint32_t code=0, code2=0;
794
795
796 while(!BUTTON_PRESS()) {
797
798 // Configure to go in 125Khz listen mode
799 LFSetupFPGAForADC(0,true);
800
801 WDT_HIT();
802 if (ledcontrol) LED_A_ON();
803
804 DoAcquisition125k(true);
805 size = sizeof(BigBuf);
806
807 // FSK demodulator
808 size = fsk_demod(dest, size);
809 WDT_HIT();
810
811 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
812 // 1->0 : fc/8 in sets of 7
813 // 0->1 : fc/10 in sets of 6
814 size = aggregate_bits(dest, size, 7,6,13);
815
816 WDT_HIT();
817
818 //Handle the data
819 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
820 for( idx=0; idx < size - 64; idx++) {
821
822 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
823
824 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
825 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
826 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
827 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
828 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
829 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
830 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
831 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
832
833 code = bytebits_to_byte(dest+idx,32);
834 code2 = bytebits_to_byte(dest+idx+32,32);
835
836 short version = bytebits_to_byte(dest+idx+14,4);
837 char unknown = bytebits_to_byte(dest+idx+19,8) ;
838 uint16_t number = bytebits_to_byte(dest+idx+36,9);
839
840 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
841 if (ledcontrol) LED_D_OFF();
842
843 // if we're only looking for one tag
844 if (findone){
845 LED_A_OFF();
846 return;
847 }
848 }
849 WDT_HIT();
850 }
851 DbpString("Stopped");
852 if (ledcontrol) LED_A_OFF();
853 }
854
855 /*------------------------------
856 * T5555/T5557/T5567 routines
857 *------------------------------
858 */
859
860 /* T55x7 configuration register definitions */
861 #define T55x7_POR_DELAY 0x00000001
862 #define T55x7_ST_TERMINATOR 0x00000008
863 #define T55x7_PWD 0x00000010
864 #define T55x7_MAXBLOCK_SHIFT 5
865 #define T55x7_AOR 0x00000200
866 #define T55x7_PSKCF_RF_2 0
867 #define T55x7_PSKCF_RF_4 0x00000400
868 #define T55x7_PSKCF_RF_8 0x00000800
869 #define T55x7_MODULATION_DIRECT 0
870 #define T55x7_MODULATION_PSK1 0x00001000
871 #define T55x7_MODULATION_PSK2 0x00002000
872 #define T55x7_MODULATION_PSK3 0x00003000
873 #define T55x7_MODULATION_FSK1 0x00004000
874 #define T55x7_MODULATION_FSK2 0x00005000
875 #define T55x7_MODULATION_FSK1a 0x00006000
876 #define T55x7_MODULATION_FSK2a 0x00007000
877 #define T55x7_MODULATION_MANCHESTER 0x00008000
878 #define T55x7_MODULATION_BIPHASE 0x00010000
879 #define T55x7_BITRATE_RF_8 0
880 #define T55x7_BITRATE_RF_16 0x00040000
881 #define T55x7_BITRATE_RF_32 0x00080000
882 #define T55x7_BITRATE_RF_40 0x000C0000
883 #define T55x7_BITRATE_RF_50 0x00100000
884 #define T55x7_BITRATE_RF_64 0x00140000
885 #define T55x7_BITRATE_RF_100 0x00180000
886 #define T55x7_BITRATE_RF_128 0x001C0000
887
888 /* T5555 (Q5) configuration register definitions */
889 #define T5555_ST_TERMINATOR 0x00000001
890 #define T5555_MAXBLOCK_SHIFT 0x00000001
891 #define T5555_MODULATION_MANCHESTER 0
892 #define T5555_MODULATION_PSK1 0x00000010
893 #define T5555_MODULATION_PSK2 0x00000020
894 #define T5555_MODULATION_PSK3 0x00000030
895 #define T5555_MODULATION_FSK1 0x00000040
896 #define T5555_MODULATION_FSK2 0x00000050
897 #define T5555_MODULATION_BIPHASE 0x00000060
898 #define T5555_MODULATION_DIRECT 0x00000070
899 #define T5555_INVERT_OUTPUT 0x00000080
900 #define T5555_PSK_RF_2 0
901 #define T5555_PSK_RF_4 0x00000100
902 #define T5555_PSK_RF_8 0x00000200
903 #define T5555_USE_PWD 0x00000400
904 #define T5555_USE_AOR 0x00000800
905 #define T5555_BITRATE_SHIFT 12
906 #define T5555_FAST_WRITE 0x00004000
907 #define T5555_PAGE_SELECT 0x00008000
908
909 /*
910 * Relevant times in microsecond
911 * To compensate antenna falling times shorten the write times
912 * and enlarge the gap ones.
913 */
914 #define START_GAP 30*8 // 10 - 50fc 250
915 #define WRITE_GAP 20*8 // 8 - 30fc
916 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
917 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
918
919 // VALUES TAKEN FROM EM4x function: SendForward
920 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
921 // WRITE_GAP = 128; (16*8)
922 // WRITE_1 = 256 32*8; (32*8)
923
924 // These timings work for 4469/4269/4305 (with the 55*8 above)
925 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
926
927 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
928
929 // Write one bit to card
930 void T55xxWriteBit(int bit)
931 {
932 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
933 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
934 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
935 if (!bit)
936 SpinDelayUs(WRITE_0);
937 else
938 SpinDelayUs(WRITE_1);
939 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
940 SpinDelayUs(WRITE_GAP);
941 }
942
943 // Write one card block in page 0, no lock
944 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
945 {
946 uint32_t i = 0;
947
948 // Set up FPGA, 125kHz
949 // Wait for config.. (192+8190xPOW)x8 == 67ms
950 LFSetupFPGAForADC(0, true);
951
952 // Now start writting
953 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
954 SpinDelayUs(START_GAP);
955
956 // Opcode
957 T55xxWriteBit(1);
958 T55xxWriteBit(0); //Page 0
959 if (PwdMode == 1){
960 // Pwd
961 for (i = 0x80000000; i != 0; i >>= 1)
962 T55xxWriteBit(Pwd & i);
963 }
964 // Lock bit
965 T55xxWriteBit(0);
966
967 // Data
968 for (i = 0x80000000; i != 0; i >>= 1)
969 T55xxWriteBit(Data & i);
970
971 // Block
972 for (i = 0x04; i != 0; i >>= 1)
973 T55xxWriteBit(Block & i);
974
975 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
976 // so wait a little more)
977 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
978 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
979 SpinDelay(20);
980 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
981 }
982
983 // Read one card block in page 0
984 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
985 {
986 uint8_t *dest = mifare_get_bigbufptr();
987 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
988 uint32_t i = 0;
989
990 // Clear destination buffer before sending the command 0x80 = average.
991 memset(dest, 0x80, bufferlength);
992
993 // Set up FPGA, 125kHz
994 // Wait for config.. (192+8190xPOW)x8 == 67ms
995 LFSetupFPGAForADC(0, true);
996
997 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
998 SpinDelayUs(START_GAP);
999
1000 // Opcode
1001 T55xxWriteBit(1);
1002 T55xxWriteBit(0); //Page 0
1003 if (PwdMode == 1){
1004 // Pwd
1005 for (i = 0x80000000; i != 0; i >>= 1)
1006 T55xxWriteBit(Pwd & i);
1007 }
1008 // Lock bit
1009 T55xxWriteBit(0);
1010 // Block
1011 for (i = 0x04; i != 0; i >>= 1)
1012 T55xxWriteBit(Block & i);
1013
1014 // Turn field on to read the response
1015 TurnReadLFOn();
1016
1017 // Now do the acquisition
1018 i = 0;
1019 for(;;) {
1020 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1021 AT91C_BASE_SSC->SSC_THR = 0x43;
1022 LED_D_ON();
1023 }
1024 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1025 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1026 ++i;
1027 LED_D_OFF();
1028 if (i > bufferlength) break;
1029 }
1030 }
1031
1032 cmd_send(CMD_ACK,0,0,0,0,0);
1033 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1034 LED_D_OFF();
1035 }
1036
1037 // Read card traceability data (page 1)
1038 void T55xxReadTrace(void){
1039 uint8_t *dest = mifare_get_bigbufptr();
1040 uint16_t bufferlength = T55xx_SAMPLES_SIZE;
1041 int i=0;
1042
1043 // Clear destination buffer before sending the command 0x80 = average
1044 memset(dest, 0x80, bufferlength);
1045
1046 LFSetupFPGAForADC(0, true);
1047
1048 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1049 SpinDelayUs(START_GAP);
1050
1051 // Opcode
1052 T55xxWriteBit(1);
1053 T55xxWriteBit(1); //Page 1
1054
1055 // Turn field on to read the response
1056 TurnReadLFOn();
1057
1058 // Now do the acquisition
1059 for(;;) {
1060 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1061 AT91C_BASE_SSC->SSC_THR = 0x43;
1062 LED_D_ON();
1063 }
1064 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1065 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1066 ++i;
1067 LED_D_OFF();
1068
1069 if (i >= bufferlength) break;
1070 }
1071 }
1072
1073 cmd_send(CMD_ACK,0,0,0,0,0);
1074 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1075 LED_D_OFF();
1076 }
1077
1078 void TurnReadLFOn(){
1079 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1080 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1081 // Give it a bit of time for the resonant antenna to settle.
1082 //SpinDelay(30);
1083 SpinDelayUs(8*150);
1084 }
1085
1086 /*-------------- Cloning routines -----------*/
1087 // Copy HID id to card and setup block 0 config
1088 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1089 {
1090 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1091 int last_block = 0;
1092
1093 if (longFMT){
1094 // Ensure no more than 84 bits supplied
1095 if (hi2>0xFFFFF) {
1096 DbpString("Tags can only have 84 bits.");
1097 return;
1098 }
1099 // Build the 6 data blocks for supplied 84bit ID
1100 last_block = 6;
1101 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1102 for (int i=0;i<4;i++) {
1103 if (hi2 & (1<<(19-i)))
1104 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1105 else
1106 data1 |= (1<<((3-i)*2)); // 0 -> 01
1107 }
1108
1109 data2 = 0;
1110 for (int i=0;i<16;i++) {
1111 if (hi2 & (1<<(15-i)))
1112 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1113 else
1114 data2 |= (1<<((15-i)*2)); // 0 -> 01
1115 }
1116
1117 data3 = 0;
1118 for (int i=0;i<16;i++) {
1119 if (hi & (1<<(31-i)))
1120 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1121 else
1122 data3 |= (1<<((15-i)*2)); // 0 -> 01
1123 }
1124
1125 data4 = 0;
1126 for (int i=0;i<16;i++) {
1127 if (hi & (1<<(15-i)))
1128 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1129 else
1130 data4 |= (1<<((15-i)*2)); // 0 -> 01
1131 }
1132
1133 data5 = 0;
1134 for (int i=0;i<16;i++) {
1135 if (lo & (1<<(31-i)))
1136 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1137 else
1138 data5 |= (1<<((15-i)*2)); // 0 -> 01
1139 }
1140
1141 data6 = 0;
1142 for (int i=0;i<16;i++) {
1143 if (lo & (1<<(15-i)))
1144 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1145 else
1146 data6 |= (1<<((15-i)*2)); // 0 -> 01
1147 }
1148 }
1149 else {
1150 // Ensure no more than 44 bits supplied
1151 if (hi>0xFFF) {
1152 DbpString("Tags can only have 44 bits.");
1153 return;
1154 }
1155
1156 // Build the 3 data blocks for supplied 44bit ID
1157 last_block = 3;
1158
1159 data1 = 0x1D000000; // load preamble
1160
1161 for (int i=0;i<12;i++) {
1162 if (hi & (1<<(11-i)))
1163 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1164 else
1165 data1 |= (1<<((11-i)*2)); // 0 -> 01
1166 }
1167
1168 data2 = 0;
1169 for (int i=0;i<16;i++) {
1170 if (lo & (1<<(31-i)))
1171 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1172 else
1173 data2 |= (1<<((15-i)*2)); // 0 -> 01
1174 }
1175
1176 data3 = 0;
1177 for (int i=0;i<16;i++) {
1178 if (lo & (1<<(15-i)))
1179 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1180 else
1181 data3 |= (1<<((15-i)*2)); // 0 -> 01
1182 }
1183 }
1184
1185 LED_D_ON();
1186 // Program the data blocks for supplied ID
1187 // and the block 0 for HID format
1188 T55xxWriteBlock(data1,1,0,0);
1189 T55xxWriteBlock(data2,2,0,0);
1190 T55xxWriteBlock(data3,3,0,0);
1191
1192 if (longFMT) { // if long format there are 6 blocks
1193 T55xxWriteBlock(data4,4,0,0);
1194 T55xxWriteBlock(data5,5,0,0);
1195 T55xxWriteBlock(data6,6,0,0);
1196 }
1197
1198 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1199 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1200 T55x7_MODULATION_FSK2a |
1201 last_block << T55x7_MAXBLOCK_SHIFT,
1202 0,0,0);
1203
1204 LED_D_OFF();
1205
1206 DbpString("DONE!");
1207 }
1208
1209 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1210 {
1211 int data1=0, data2=0; //up to six blocks for long format
1212
1213 data1 = hi; // load preamble
1214 data2 = lo;
1215
1216 LED_D_ON();
1217 // Program the data blocks for supplied ID
1218 // and the block 0 for HID format
1219 T55xxWriteBlock(data1,1,0,0);
1220 T55xxWriteBlock(data2,2,0,0);
1221
1222 //Config Block
1223 T55xxWriteBlock(0x00147040,0,0,0);
1224 LED_D_OFF();
1225
1226 DbpString("DONE!");
1227 }
1228
1229 // Define 9bit header for EM410x tags
1230 #define EM410X_HEADER 0x1FF
1231 #define EM410X_ID_LENGTH 40
1232
1233 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1234 {
1235 int i, id_bit;
1236 uint64_t id = EM410X_HEADER;
1237 uint64_t rev_id = 0; // reversed ID
1238 int c_parity[4]; // column parity
1239 int r_parity = 0; // row parity
1240 uint32_t clock = 0;
1241
1242 // Reverse ID bits given as parameter (for simpler operations)
1243 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1244 if (i < 32) {
1245 rev_id = (rev_id << 1) | (id_lo & 1);
1246 id_lo >>= 1;
1247 } else {
1248 rev_id = (rev_id << 1) | (id_hi & 1);
1249 id_hi >>= 1;
1250 }
1251 }
1252
1253 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1254 id_bit = rev_id & 1;
1255
1256 if (i % 4 == 0) {
1257 // Don't write row parity bit at start of parsing
1258 if (i)
1259 id = (id << 1) | r_parity;
1260 // Start counting parity for new row
1261 r_parity = id_bit;
1262 } else {
1263 // Count row parity
1264 r_parity ^= id_bit;
1265 }
1266
1267 // First elements in column?
1268 if (i < 4)
1269 // Fill out first elements
1270 c_parity[i] = id_bit;
1271 else
1272 // Count column parity
1273 c_parity[i % 4] ^= id_bit;
1274
1275 // Insert ID bit
1276 id = (id << 1) | id_bit;
1277 rev_id >>= 1;
1278 }
1279
1280 // Insert parity bit of last row
1281 id = (id << 1) | r_parity;
1282
1283 // Fill out column parity at the end of tag
1284 for (i = 0; i < 4; ++i)
1285 id = (id << 1) | c_parity[i];
1286
1287 // Add stop bit
1288 id <<= 1;
1289
1290 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1291 LED_D_ON();
1292
1293 // Write EM410x ID
1294 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1295 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1296
1297 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1298 if (card) {
1299 // Clock rate is stored in bits 8-15 of the card value
1300 clock = (card & 0xFF00) >> 8;
1301 Dbprintf("Clock rate: %d", clock);
1302 switch (clock)
1303 {
1304 case 32:
1305 clock = T55x7_BITRATE_RF_32;
1306 break;
1307 case 16:
1308 clock = T55x7_BITRATE_RF_16;
1309 break;
1310 case 0:
1311 // A value of 0 is assumed to be 64 for backwards-compatibility
1312 // Fall through...
1313 case 64:
1314 clock = T55x7_BITRATE_RF_64;
1315 break;
1316 default:
1317 Dbprintf("Invalid clock rate: %d", clock);
1318 return;
1319 }
1320
1321 // Writing configuration for T55x7 tag
1322 T55xxWriteBlock(clock |
1323 T55x7_MODULATION_MANCHESTER |
1324 2 << T55x7_MAXBLOCK_SHIFT,
1325 0, 0, 0);
1326 }
1327 else
1328 // Writing configuration for T5555(Q5) tag
1329 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1330 T5555_MODULATION_MANCHESTER |
1331 2 << T5555_MAXBLOCK_SHIFT,
1332 0, 0, 0);
1333
1334 LED_D_OFF();
1335 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1336 (uint32_t)(id >> 32), (uint32_t)id);
1337 }
1338
1339 // Clone Indala 64-bit tag by UID to T55x7
1340 void CopyIndala64toT55x7(int hi, int lo)
1341 {
1342 //Program the 2 data blocks for supplied 64bit UID
1343 // and the block 0 for Indala64 format
1344 T55xxWriteBlock(hi,1,0,0);
1345 T55xxWriteBlock(lo,2,0,0);
1346 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1347 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1348 T55x7_MODULATION_PSK1 |
1349 2 << T55x7_MAXBLOCK_SHIFT,
1350 0, 0, 0);
1351 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1352 // T5567WriteBlock(0x603E1042,0);
1353
1354 DbpString("DONE!");
1355 }
1356
1357 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1358 {
1359 //Program the 7 data blocks for supplied 224bit UID
1360 // and the block 0 for Indala224 format
1361 T55xxWriteBlock(uid1,1,0,0);
1362 T55xxWriteBlock(uid2,2,0,0);
1363 T55xxWriteBlock(uid3,3,0,0);
1364 T55xxWriteBlock(uid4,4,0,0);
1365 T55xxWriteBlock(uid5,5,0,0);
1366 T55xxWriteBlock(uid6,6,0,0);
1367 T55xxWriteBlock(uid7,7,0,0);
1368 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1369 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1370 T55x7_MODULATION_PSK1 |
1371 7 << T55x7_MAXBLOCK_SHIFT,
1372 0,0,0);
1373 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1374 // T5567WriteBlock(0x603E10E2,0);
1375
1376 DbpString("DONE!");
1377 }
1378
1379
1380 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1381 #define max(x,y) ( x<y ? y:x)
1382
1383 int DemodPCF7931(uint8_t **outBlocks) {
1384 uint8_t BitStream[256];
1385 uint8_t Blocks[8][16];
1386 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1387 int GraphTraceLen = sizeof(BigBuf);
1388 int i, j, lastval, bitidx, half_switch;
1389 int clock = 64;
1390 int tolerance = clock / 8;
1391 int pmc, block_done;
1392 int lc, warnings = 0;
1393 int num_blocks = 0;
1394 int lmin=128, lmax=128;
1395 uint8_t dir;
1396
1397 AcquireRawAdcSamples125k(0);
1398
1399 lmin = 64;
1400 lmax = 192;
1401
1402 i = 2;
1403
1404 /* Find first local max/min */
1405 if(GraphBuffer[1] > GraphBuffer[0]) {
1406 while(i < GraphTraceLen) {
1407 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1408 break;
1409 i++;
1410 }
1411 dir = 0;
1412 }
1413 else {
1414 while(i < GraphTraceLen) {
1415 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1416 break;
1417 i++;
1418 }
1419 dir = 1;
1420 }
1421
1422 lastval = i++;
1423 half_switch = 0;
1424 pmc = 0;
1425 block_done = 0;
1426
1427 for (bitidx = 0; i < GraphTraceLen; i++)
1428 {
1429 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1430 {
1431 lc = i - lastval;
1432 lastval = i;
1433
1434 // Switch depending on lc length:
1435 // Tolerance is 1/8 of clock rate (arbitrary)
1436 if (abs(lc-clock/4) < tolerance) {
1437 // 16T0
1438 if((i - pmc) == lc) { /* 16T0 was previous one */
1439 /* It's a PMC ! */
1440 i += (128+127+16+32+33+16)-1;
1441 lastval = i;
1442 pmc = 0;
1443 block_done = 1;
1444 }
1445 else {
1446 pmc = i;
1447 }
1448 } else if (abs(lc-clock/2) < tolerance) {
1449 // 32TO
1450 if((i - pmc) == lc) { /* 16T0 was previous one */
1451 /* It's a PMC ! */
1452 i += (128+127+16+32+33)-1;
1453 lastval = i;
1454 pmc = 0;
1455 block_done = 1;
1456 }
1457 else if(half_switch == 1) {
1458 BitStream[bitidx++] = 0;
1459 half_switch = 0;
1460 }
1461 else
1462 half_switch++;
1463 } else if (abs(lc-clock) < tolerance) {
1464 // 64TO
1465 BitStream[bitidx++] = 1;
1466 } else {
1467 // Error
1468 warnings++;
1469 if (warnings > 10)
1470 {
1471 Dbprintf("Error: too many detection errors, aborting.");
1472 return 0;
1473 }
1474 }
1475
1476 if(block_done == 1) {
1477 if(bitidx == 128) {
1478 for(j=0; j<16; j++) {
1479 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1480 64*BitStream[j*8+6]+
1481 32*BitStream[j*8+5]+
1482 16*BitStream[j*8+4]+
1483 8*BitStream[j*8+3]+
1484 4*BitStream[j*8+2]+
1485 2*BitStream[j*8+1]+
1486 BitStream[j*8];
1487 }
1488 num_blocks++;
1489 }
1490 bitidx = 0;
1491 block_done = 0;
1492 half_switch = 0;
1493 }
1494 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1495 else dir = 1;
1496 }
1497 if(bitidx==255)
1498 bitidx=0;
1499 warnings = 0;
1500 if(num_blocks == 4) break;
1501 }
1502 memcpy(outBlocks, Blocks, 16*num_blocks);
1503 return num_blocks;
1504 }
1505
1506 int IsBlock0PCF7931(uint8_t *Block) {
1507 // Assume RFU means 0 :)
1508 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1509 return 1;
1510 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1511 return 1;
1512 return 0;
1513 }
1514
1515 int IsBlock1PCF7931(uint8_t *Block) {
1516 // Assume RFU means 0 :)
1517 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1518 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1519 return 1;
1520
1521 return 0;
1522 }
1523 #define ALLOC 16
1524
1525 void ReadPCF7931() {
1526 uint8_t Blocks[8][17];
1527 uint8_t tmpBlocks[4][16];
1528 int i, j, ind, ind2, n;
1529 int num_blocks = 0;
1530 int max_blocks = 8;
1531 int ident = 0;
1532 int error = 0;
1533 int tries = 0;
1534
1535 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1536
1537 do {
1538 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1539 n = DemodPCF7931((uint8_t**)tmpBlocks);
1540 if(!n)
1541 error++;
1542 if(error==10 && num_blocks == 0) {
1543 Dbprintf("Error, no tag or bad tag");
1544 return;
1545 }
1546 else if (tries==20 || error==10) {
1547 Dbprintf("Error reading the tag");
1548 Dbprintf("Here is the partial content");
1549 goto end;
1550 }
1551
1552 for(i=0; i<n; i++)
1553 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1554 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1555 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1556 if(!ident) {
1557 for(i=0; i<n; i++) {
1558 if(IsBlock0PCF7931(tmpBlocks[i])) {
1559 // Found block 0 ?
1560 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1561 // Found block 1!
1562 // \o/
1563 ident = 1;
1564 memcpy(Blocks[0], tmpBlocks[i], 16);
1565 Blocks[0][ALLOC] = 1;
1566 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1567 Blocks[1][ALLOC] = 1;
1568 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1569 // Debug print
1570 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1571 num_blocks = 2;
1572 // Handle following blocks
1573 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1574 if(j==n) j=0;
1575 if(j==i) break;
1576 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1577 Blocks[ind2][ALLOC] = 1;
1578 }
1579 break;
1580 }
1581 }
1582 }
1583 }
1584 else {
1585 for(i=0; i<n; i++) { // Look for identical block in known blocks
1586 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1587 for(j=0; j<max_blocks; j++) {
1588 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1589 // Found an identical block
1590 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1591 if(ind2 < 0)
1592 ind2 = max_blocks;
1593 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1594 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1595 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1596 Blocks[ind2][ALLOC] = 1;
1597 num_blocks++;
1598 if(num_blocks == max_blocks) goto end;
1599 }
1600 }
1601 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1602 if(ind2 > max_blocks)
1603 ind2 = 0;
1604 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1605 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1606 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1607 Blocks[ind2][ALLOC] = 1;
1608 num_blocks++;
1609 if(num_blocks == max_blocks) goto end;
1610 }
1611 }
1612 }
1613 }
1614 }
1615 }
1616 }
1617 tries++;
1618 if (BUTTON_PRESS()) return;
1619 } while (num_blocks != max_blocks);
1620 end:
1621 Dbprintf("-----------------------------------------");
1622 Dbprintf("Memory content:");
1623 Dbprintf("-----------------------------------------");
1624 for(i=0; i<max_blocks; i++) {
1625 if(Blocks[i][ALLOC]==1)
1626 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1627 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1628 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1629 else
1630 Dbprintf("<missing block %d>", i);
1631 }
1632 Dbprintf("-----------------------------------------");
1633
1634 return ;
1635 }
1636
1637
1638 //-----------------------------------
1639 // EM4469 / EM4305 routines
1640 //-----------------------------------
1641 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1642 #define FWD_CMD_WRITE 0xA
1643 #define FWD_CMD_READ 0x9
1644 #define FWD_CMD_DISABLE 0x5
1645
1646
1647 uint8_t forwardLink_data[64]; //array of forwarded bits
1648 uint8_t * forward_ptr; //ptr for forward message preparation
1649 uint8_t fwd_bit_sz; //forwardlink bit counter
1650 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1651
1652 //====================================================================
1653 // prepares command bits
1654 // see EM4469 spec
1655 //====================================================================
1656 //--------------------------------------------------------------------
1657 uint8_t Prepare_Cmd( uint8_t cmd ) {
1658 //--------------------------------------------------------------------
1659
1660 *forward_ptr++ = 0; //start bit
1661 *forward_ptr++ = 0; //second pause for 4050 code
1662
1663 *forward_ptr++ = cmd;
1664 cmd >>= 1;
1665 *forward_ptr++ = cmd;
1666 cmd >>= 1;
1667 *forward_ptr++ = cmd;
1668 cmd >>= 1;
1669 *forward_ptr++ = cmd;
1670
1671 return 6; //return number of emited bits
1672 }
1673
1674 //====================================================================
1675 // prepares address bits
1676 // see EM4469 spec
1677 //====================================================================
1678
1679 //--------------------------------------------------------------------
1680 uint8_t Prepare_Addr( uint8_t addr ) {
1681 //--------------------------------------------------------------------
1682
1683 register uint8_t line_parity;
1684
1685 uint8_t i;
1686 line_parity = 0;
1687 for(i=0;i<6;i++) {
1688 *forward_ptr++ = addr;
1689 line_parity ^= addr;
1690 addr >>= 1;
1691 }
1692
1693 *forward_ptr++ = (line_parity & 1);
1694
1695 return 7; //return number of emited bits
1696 }
1697
1698 //====================================================================
1699 // prepares data bits intreleaved with parity bits
1700 // see EM4469 spec
1701 //====================================================================
1702
1703 //--------------------------------------------------------------------
1704 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1705 //--------------------------------------------------------------------
1706
1707 register uint8_t line_parity;
1708 register uint8_t column_parity;
1709 register uint8_t i, j;
1710 register uint16_t data;
1711
1712 data = data_low;
1713 column_parity = 0;
1714
1715 for(i=0; i<4; i++) {
1716 line_parity = 0;
1717 for(j=0; j<8; j++) {
1718 line_parity ^= data;
1719 column_parity ^= (data & 1) << j;
1720 *forward_ptr++ = data;
1721 data >>= 1;
1722 }
1723 *forward_ptr++ = line_parity;
1724 if(i == 1)
1725 data = data_hi;
1726 }
1727
1728 for(j=0; j<8; j++) {
1729 *forward_ptr++ = column_parity;
1730 column_parity >>= 1;
1731 }
1732 *forward_ptr = 0;
1733
1734 return 45; //return number of emited bits
1735 }
1736
1737 //====================================================================
1738 // Forward Link send function
1739 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1740 // fwd_bit_count set with number of bits to be sent
1741 //====================================================================
1742 void SendForward(uint8_t fwd_bit_count) {
1743
1744 fwd_write_ptr = forwardLink_data;
1745 fwd_bit_sz = fwd_bit_count;
1746
1747 LED_D_ON();
1748
1749 //Field on
1750 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1751 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1752 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1753
1754 // Give it a bit of time for the resonant antenna to settle.
1755 // And for the tag to fully power up
1756 SpinDelay(150);
1757
1758 // force 1st mod pulse (start gap must be longer for 4305)
1759 fwd_bit_sz--; //prepare next bit modulation
1760 fwd_write_ptr++;
1761 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1762 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1763 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1764 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1765 SpinDelayUs(16*8); //16 cycles on (8us each)
1766
1767 // now start writting
1768 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1769 if(((*fwd_write_ptr++) & 1) == 1)
1770 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1771 else {
1772 //These timings work for 4469/4269/4305 (with the 55*8 above)
1773 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1774 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1775 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1776 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1777 SpinDelayUs(9*8); //16 cycles on (8us each)
1778 }
1779 }
1780 }
1781
1782
1783 void EM4xLogin(uint32_t Password) {
1784
1785 uint8_t fwd_bit_count;
1786
1787 forward_ptr = forwardLink_data;
1788 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1789 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1790
1791 SendForward(fwd_bit_count);
1792
1793 //Wait for command to complete
1794 SpinDelay(20);
1795
1796 }
1797
1798 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1799
1800 uint8_t *dest = mifare_get_bigbufptr();
1801 uint16_t bufferlength = 12000;
1802 uint32_t i = 0;
1803
1804 // Clear destination buffer before sending the command 0x80 = average.
1805 memset(dest, 0x80, bufferlength);
1806
1807 uint8_t fwd_bit_count;
1808
1809 //If password mode do login
1810 if (PwdMode == 1) EM4xLogin(Pwd);
1811
1812 forward_ptr = forwardLink_data;
1813 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1814 fwd_bit_count += Prepare_Addr( Address );
1815
1816 // Connect the A/D to the peak-detected low-frequency path.
1817 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1818 // Now set up the SSC to get the ADC samples that are now streaming at us.
1819 FpgaSetupSsc();
1820
1821 SendForward(fwd_bit_count);
1822
1823 // // Turn field on to read the response
1824 // TurnReadLFOn();
1825
1826 // Now do the acquisition
1827 i = 0;
1828 for(;;) {
1829 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1830 AT91C_BASE_SSC->SSC_THR = 0x43;
1831 }
1832 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1833 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1834 ++i;
1835 if (i >= bufferlength) break;
1836 }
1837 }
1838
1839 cmd_send(CMD_ACK,0,0,0,0,0);
1840 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1841 LED_D_OFF();
1842 }
1843
1844 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1845
1846 uint8_t fwd_bit_count;
1847
1848 //If password mode do login
1849 if (PwdMode == 1) EM4xLogin(Pwd);
1850
1851 forward_ptr = forwardLink_data;
1852 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1853 fwd_bit_count += Prepare_Addr( Address );
1854 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1855
1856 SendForward(fwd_bit_count);
1857
1858 //Wait for write to complete
1859 SpinDelay(20);
1860 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1861 LED_D_OFF();
1862 }
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