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optimization UDOL creation. does not affect on functionality.
[proxmark3-svn] / fpga / lo_edge_detect.v
1 //-----------------------------------------------------------------------------
2 // Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 //
9 // There are two modes:
10 // - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
11 // (resp. high) edge/peak is detected, with hysteresis
12 // - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
13 // is detected.
14 // That way you can detect two consecutive edges/peaks at the same level (L/H)
15 //
16 // Output:
17 // - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
18 // - ssp_clk: cross_lo
19 `include "lp20khz_1MSa_iir_filter.v"
20 `include "lf_edge_detect.v"
21
22 module lo_edge_detect(
23 input pck0, input pck_divclk,
24 output pwr_lo, output pwr_hi,
25 output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
26 input [7:0] adc_d, output adc_clk,
27 output ssp_frame, input ssp_dout, output ssp_clk,
28 input cross_lo,
29 output dbg,
30 input lf_field,
31 input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
32 );
33
34 wire tag_modulation = ssp_dout & !lf_field;
35 wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
36
37 // No logic, straight through.
38 assign pwr_oe1 = 1'b0; // not used in LF mode
39 assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
40 // when modulating, add another 33 Ohms and 10k Ohms in parallel:
41 assign pwr_oe2 = tag_modulation;
42 assign pwr_oe4 = tag_modulation;
43
44 assign ssp_clk = cross_lo;
45 assign pwr_lo = reader_modulation;
46 assign pwr_hi = 1'b0;
47
48 // filter the ADC values
49 wire data_rdy;
50 wire [7:0] adc_filtered;
51 assign adc_clk = pck0;
52 lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
53
54 // detect edges
55 wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
56 wire [7:0] max, min;
57 wire edge_state, edge_toggle;
58 lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
59 max, min,
60 high_threshold, highz_threshold, lowz_threshold, low_threshold,
61 edge_state, edge_toggle);
62
63 assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
64
65 assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
66
67 endmodule
68
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