1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
5 //-----------------------------------------------------------------------------
6 // HitagS emulation (preliminary test version)
8 // (c) 2016 Oguzhan Cicek, Hendrik Schwartke, Ralf Spenneberg
10 //-----------------------------------------------------------------------------
11 // Some code was copied from Hitag2.c
12 //-----------------------------------------------------------------------------
17 #include "proxmark3.h"
25 #define CRC_PRESET 0xFF
26 #define CRC_POLYNOM 0x1D
31 #define rev8(x) ((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7))
32 #define rev16(x) (rev8 (x)+(rev8 (x>> 8)<< 8))
33 #define rev32(x) (rev16(x)+(rev16(x>>16)<<16))
34 #define rev64(x) (rev32(x)+(rev32(x>>32)<<32))
35 #define bit(x,n) (((x)>>(n))&1)
36 #define bit32(x,n) ((((x)[(n)>>5])>>((n)))&1)
37 #define inv32(x,i,n) ((x)[(i)>>5]^=((u32)(n))<<((i)&31))
38 #define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))
41 static bool bSuccessful
;
42 static struct hitagS_tag tag
;
43 static byte_t page_to_be_written
= 0;
44 static int block_data_left
= 0;
45 typedef enum modulation
{
46 AC2K
= 0, AC4K
, MC4K
, MC8K
48 static MOD m
= AC2K
; //used modulation
49 static uint32_t temp_uid
;
51 static int sof_bits
; //number of start-of-frame bits
52 static byte_t pwdh0
, pwdl0
, pwdl1
; //password bytes
53 static uint32_t rnd
= 0x74124485; //randomnumber
58 // Single bit Hitag2 functions:
59 #define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))
60 static const u32 ht2_f4a
= 0x2C79; // 0010 1100 0111 1001
61 static const u32 ht2_f4b
= 0x6671; // 0110 0110 0111 0001
62 static const u32 ht2_f5c
= 0x7907287B; // 0111 1001 0000 0111 0010 1000 0111 1011
63 #define ht2bs_4a(a,b,c,d) (~(((a|b)&c)^(a|d)^b))
64 #define ht2bs_4b(a,b,c,d) (~(((d|c)&(a^b))^(d|a|b)))
65 #define ht2bs_5c(a,b,c,d,e) (~((((((c^e)|d)&a)^b)&(c^b))^(((d^e)|a)&((d^b)|c))))
68 static u32
f20(const u64 x
) {
71 i5
= ((ht2_f4a
>> i4(x
, 1, 2, 4, 5)) & 1) * 1
72 + ((ht2_f4b
>> i4(x
, 7, 11, 13, 14)) & 1) * 2
73 + ((ht2_f4b
>> i4(x
, 16, 20, 22, 25)) & 1) * 4
74 + ((ht2_f4b
>> i4(x
, 27, 28, 30, 32)) & 1) * 8
75 + ((ht2_f4a
>> i4(x
, 33, 42, 43, 45)) & 1) * 16;
77 return (ht2_f5c
>> i5
) & 1;
79 static u64
hitag2_round(u64
*state
) {
83 + ((((x
>> 0) ^ (x
>> 2) ^ (x
>> 3) ^ (x
>> 6) ^ (x
>> 7) ^ (x
>> 8)
84 ^ (x
>> 16) ^ (x
>> 22) ^ (x
>> 23) ^ (x
>> 26) ^ (x
>> 30)
85 ^ (x
>> 41) ^ (x
>> 42) ^ (x
>> 43) ^ (x
>> 46) ^ (x
>> 47))
91 static u64
hitag2_init(const u64 key
, const u32 serial
, const u32 IV
) {
93 u64 x
= ((key
& 0xFFFF) << 32) + serial
;
94 for (i
= 0; i
< 32; i
++) {
96 x
+= (u64
) (f20(x
) ^ (((IV
>> i
) ^ (key
>> (i
+ 16))) & 1)) << 47;
100 static u32
hitag2_byte(u64
*x
) {
103 for (i
= 0, c
= 0; i
< 8; i
++)
104 c
+= (u32
) hitag2_round(x
) << (i
^ 7);
108 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
109 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
110 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
111 // T0 = TIMER_CLOCK1 / 125000 = 192
114 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
115 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
117 #define HITAG_FRAME_LEN 20
118 #define HITAG_T_STOP 36 /* T_EOF should be > 36 */
119 #define HITAG_T_LOW 8 /* T_LOW should be 4..10 */
120 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
121 #define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */
122 //#define HITAG_T_EOF 40 /* T_EOF should be > 36 */
123 #define HITAG_T_EOF 80 /* T_EOF should be > 36 */
124 #define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */
125 #define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */
126 #define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */
128 #define HITAG_T_TAG_ONE_HALF_PERIOD 10
129 #define HITAG_T_TAG_TWO_HALF_PERIOD 25
130 #define HITAG_T_TAG_THREE_HALF_PERIOD 41
131 #define HITAG_T_TAG_FOUR_HALF_PERIOD 57
133 #define HITAG_T_TAG_HALF_PERIOD 16
134 #define HITAG_T_TAG_FULL_PERIOD 32
136 #define HITAG_T_TAG_CAPTURE_ONE_HALF 13
137 #define HITAG_T_TAG_CAPTURE_TWO_HALF 25
138 #define HITAG_T_TAG_CAPTURE_THREE_HALF 41
139 #define HITAG_T_TAG_CAPTURE_FOUR_HALF 57
144 * Implementation of the crc8 calculation from Hitag S
145 * from http://www.proxmark.org/files/Documents/125%20kHz%20-%20Hitag/HitagS.V11.pdf
147 void calc_crc(unsigned char * crc
, unsigned char data
, unsigned char Bitcount
) {
148 *crc
^= data
; // crc = crc (exor) data
150 if (*crc
& 0x80) // if (MSB-CRC == 1)
152 *crc
<<= 1; // CRC = CRC Bit-shift left
153 *crc
^= CRC_POLYNOM
; // CRC = CRC (exor) CRC_POLYNOM
155 *crc
<<= 1; // CRC = CRC Bit-shift left
157 } while (--Bitcount
);
160 static void hitag_send_bit(int bit
) {
162 // Reset clock for the next bit
163 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
170 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
173 while (AT91C_BASE_TC0
->TC_CV
< T0
* 64)
178 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
181 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
184 while (AT91C_BASE_TC0
->TC_CV
< T0
* 48)
187 while (AT91C_BASE_TC0
->TC_CV
< T0
* 64)
196 while (AT91C_BASE_TC0
->TC_CV
< T0
* HITAG_T_TAG_HALF_PERIOD
)
199 while (AT91C_BASE_TC0
->TC_CV
< T0
* HITAG_T_TAG_FULL_PERIOD
)
204 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
207 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
210 while (AT91C_BASE_TC0
->TC_CV
< T0
* 24)
213 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
220 // Manchester: Unloaded, then loaded |__--|
222 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
225 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
228 // Manchester: Loaded, then unloaded |--__|
230 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
233 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
240 // Manchester: Unloaded, then loaded |__--|
242 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
245 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
248 // Manchester: Loaded, then unloaded |--__|
250 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
253 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
263 static void hitag_send_frame(const byte_t
* frame
, size_t frame_len
) {
264 // Send start of frame
266 for (size_t i
= 0; i
< sof_bits
; i
++) {
270 // Send the content of the frame
271 for (size_t i
= 0; i
< frame_len
; i
++) {
272 hitag_send_bit((frame
[i
/ 8] >> (7 - (i
% 8))) & 1);
274 // Drop the modulation
278 static void hitag_reader_send_bit(int bit
) {
279 //Dbprintf("BIT: %d",bit);
281 // Reset clock for the next bit
282 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
284 // Binary puls length modulation (BPLM) is used to encode the data stream
285 // This means that a transmission of a one takes longer than that of a zero
287 // Enable modulation, which means, drop the the field
290 // Wait for 4-10 times the carrier period
291 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
295 // Disable modulation, just activates the field again
300 while (AT91C_BASE_TC0
->TC_CV
< T0
* 11)
302 // SpinDelayUs(16*8);
305 while (AT91C_BASE_TC0
->TC_CV
< T0
* 14)
307 // SpinDelayUs(22*8);
310 // Wait for 4-10 times the carrier period
311 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
315 // Disable modulation, just activates the field again
320 while (AT91C_BASE_TC0
->TC_CV
< T0
* 22)
322 // SpinDelayUs(16*8);
325 while (AT91C_BASE_TC0
->TC_CV
< T0
* 28)
327 // SpinDelayUs(22*8);
334 static void hitag_reader_send_frame(const byte_t
* frame
, size_t frame_len
) {
335 // Send the content of the frame
336 for (size_t i
= 0; i
< frame_len
; i
++) {
337 if (frame
[0] == 0xf8) {
338 //Dbprintf("BIT: %d",(frame[i / 8] >> (7 - (i % 8))) & 1);
340 hitag_reader_send_bit((frame
[i
/ 8] >> (7 - (i
% 8))) & 1);
343 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
344 // Enable modulation, which means, drop the the field
346 // Wait for 4-10 times the carrier period
347 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
349 // Disable modulation, just activates the field again
354 * to check if the right uid was selected
356 static int check_select(byte_t
* rx
, uint32_t uid
) {
357 unsigned char resp
[48];
360 for (i
= 0; i
< 48; i
++)
361 resp
[i
] = (rx
[i
/ 8] >> (7 - (i
% 8))) & 0x1;
362 for (i
= 0; i
< 32; i
++)
363 ans
+= resp
[5 + i
] << (31 - i
);
364 /*if (rx[0] == 0x01 && rx[1] == 0x15 && rx[2] == 0xc1 && rx[3] == 0x14
365 && rx[4] == 0x65 && rx[5] == 0x38)
366 Dbprintf("got uid %X", ans);*/
374 * handles all commands from a reader
376 static void hitagS_handle_reader_command(byte_t
* rx
, const size_t rxlen
,
377 byte_t
* tx
, size_t* txlen
) {
378 byte_t rx_air
[HITAG_FRAME_LEN
];
384 // Copy the (original) received frame how it is send over the air
385 memcpy(rx_air
, rx
, nbytes(rxlen
));
386 // Reset the transmission frame length
388 // Try to find out which command was send by selecting on length (in bits)
391 //UID request with a selected response protocol mode
394 if ((rx
[0] & 0xf0) == 0x30) {
399 if ((rx
[0] & 0xf0) == 0xc0) {
405 if ((rx
[0] & 0xf0) == 0xd0) {
406 tag
.mode
= FAST_ADVANCED
;
410 //send uid as a response
412 for (i
= 0; i
< 4; i
++)
413 tx
[i
] = (tag
.uid
>> (24 - (i
* 8))) & 0xff;
417 //select command from reader received
418 if (check_select(rx
, tag
.uid
) == 1) {
419 //if the right tag was selected
439 for (i
= 0; i
< 4; i
++)
440 tx
[i
] = (tag
.pages
[0][1] >> (i
* 8)) & 0xff;
442 if (tag
.mode
!= STANDARD
) {
445 for (i
= 0; i
< 4; i
++)
446 calc_crc(&crc
, tx
[i
], 8);
453 //challenge message received
454 Dbprintf("Challenge for UID: %X", temp_uid
);
457 state
= hitag2_init(rev64(tag
.key
), rev32(tag
.pages
[0][0]),
458 rev32(((rx
[3] << 24) + (rx
[2] << 16) + (rx
[1] << 8) + rx
[0])));
460 ",{0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X}",
461 rx
[0], rx
[1], rx
[2], rx
[3], rx
[4], rx
[5], rx
[6], rx
[7]);
479 for (i
= 0; i
< 4; i
++)
481 //send con2,pwdh0,pwdl0,pwdl1 encrypted as a response
482 tx
[0] = hitag2_byte(&state
) ^ ((tag
.pages
[0][1] >> 16) & 0xff);
483 tx
[1] = hitag2_byte(&state
) ^ tag
.pwdh0
;
484 tx
[2] = hitag2_byte(&state
) ^ tag
.pwdl0
;
485 tx
[3] = hitag2_byte(&state
) ^ tag
.pwdl1
;
486 if (tag
.mode
!= STANDARD
) {
490 calc_crc(&crc
, ((tag
.pages
[0][1] >> 16) & 0xff), 8);
491 calc_crc(&crc
, tag
.pwdh0
, 8);
492 calc_crc(&crc
, tag
.pwdl0
, 8);
493 calc_crc(&crc
, tag
.pwdl1
, 8);
494 tx
[4] = (crc
^ hitag2_byte(&state
));
497 * some readers do not allow to authenticate multiple times in a row with the same tag.
498 * use this to change the uid between authentications.
502 if (temp2 % 2 == 0) {
503 tag.uid = 0x11223344;
504 tag.pages[0][0] = 0x44332211;
506 tag.uid = 0x55667788;
507 tag.pages[0][0] = 0x88776655;
512 //data received to be written
513 if (tag
.tstate
== WRITING_PAGE_DATA
) {
515 tag
.pages
[page_to_be_written
/ 4][page_to_be_written
% 4] = (rx
[0]
516 << 0) + (rx
[1] << 8) + (rx
[2] << 16) + (rx
[3] << 24);
520 page_to_be_written
= 0;
537 } else if (tag
.tstate
== WRITING_BLOCK_DATA
) {
538 tag
.pages
[page_to_be_written
/ 4][page_to_be_written
% 4] = (rx
[0]
539 << 24) + (rx
[1] << 16) + (rx
[2] << 8) + rx
[3];
559 page_to_be_written
++;
561 if (block_data_left
== 0) {
563 page_to_be_written
= 0;
568 //write page, write block, read page or read block command received
569 if ((rx
[0] & 0xf0) == 0xc0) //read page
572 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
574 tx
[0] = (tag
.pages
[page
/ 4][page
% 4]) & 0xff;
575 tx
[1] = (tag
.pages
[page
/ 4][page
% 4] >> 8) & 0xff;
576 tx
[2] = (tag
.pages
[page
/ 4][page
% 4] >> 16) & 0xff;
577 tx
[3] = (tag
.pages
[page
/ 4][page
% 4] >> 24) & 0xff;
578 if (tag
.LKP
&& page
== 1)
598 if (tag
.mode
!= STANDARD
) {
602 for (i
= 0; i
< 4; i
++)
603 calc_crc(&crc
, tx
[i
], 8);
607 if (tag
.LKP
&& (page
== 2 || page
== 3)) {
608 //if reader asks for key or password and the LKP-mark is set do not respond
612 } else if ((rx
[0] & 0xf0) == 0xd0) //read block
614 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
616 //send page,...,page+3 data
617 for (i
= 0; i
< 4; i
++) {
618 tx
[0 + i
* 4] = (tag
.pages
[page
/ 4][page
% 4]) & 0xff;
619 tx
[1 + i
* 4] = (tag
.pages
[page
/ 4][page
% 4] >> 8) & 0xff;
620 tx
[2 + i
* 4] = (tag
.pages
[page
/ 4][page
% 4] >> 16) & 0xff;
621 tx
[3 + i
* 4] = (tag
.pages
[page
/ 4][page
% 4] >> 24) & 0xff;
642 if (tag
.mode
!= STANDARD
) {
646 for (i
= 0; i
< 16; i
++)
647 calc_crc(&crc
, tx
[i
], 8);
651 if ((page
- 4) % 4 != 0 || (tag
.LKP
&& (page
- 4) == 0)) {
655 } else if ((rx
[0] & 0xf0) == 0x80) //write page
657 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
675 if ((tag
.LCON
&& page
== 1)
676 || (tag
.LKP
&& (page
== 2 || page
== 3))) {
683 page_to_be_written
= page
;
684 tag
.tstate
= WRITING_PAGE_DATA
;
687 } else if ((rx
[0] & 0xf0) == 0x90) //write block
689 page
= ((rx
[0] & 0x0f) * 6) + ((rx
[1] & 0xf0) / 16);
706 if (page
% 4 != 0 || page
== 0) {
713 page_to_be_written
= page
;
715 tag
.tstate
= WRITING_BLOCK_DATA
;
727 * to autenticate to a tag with the given key or challenge
729 static int hitagS_handle_tag_auth(hitag_function htf
,uint64_t key
, uint64_t NrAr
, byte_t
* rx
, const size_t rxlen
, byte_t
* tx
,
731 byte_t rx_air
[HITAG_FRAME_LEN
];
732 int response_bit
[200];
734 unsigned char mask
= 1;
735 unsigned char uid
[32];
736 byte_t uid1
= 0x00, uid2
= 0x00, uid3
= 0x00, uid4
= 0x00;
740 byte_t conf_pages
[3];
741 memcpy(rx_air
, rx
, nbytes(rxlen
));
744 if (tag
.pstate
== READY
&& rxlen
>= 67) {
747 Dbprintf("authentication failed!");
751 for (i
= 0; i
< 10; i
++) {
752 for (j
= 0; j
< 8; j
++) {
754 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
760 for (i
= 5; i
< z
; i
+= 2) {
761 uid
[k
] = response_bit
[i
];
766 uid1
= (uid
[0] << 7) | (uid
[1] << 6) | (uid
[2] << 5) | (uid
[3] << 4)
767 | (uid
[4] << 3) | (uid
[5] << 2) | (uid
[6] << 1) | uid
[7];
768 uid2
= (uid
[8] << 7) | (uid
[9] << 6) | (uid
[10] << 5) | (uid
[11] << 4)
769 | (uid
[12] << 3) | (uid
[13] << 2) | (uid
[14] << 1) | uid
[15];
770 uid3
= (uid
[16] << 7) | (uid
[17] << 6) | (uid
[18] << 5) | (uid
[19] << 4)
771 | (uid
[20] << 3) | (uid
[21] << 2) | (uid
[22] << 1) | uid
[23];
772 uid4
= (uid
[24] << 7) | (uid
[25] << 6) | (uid
[26] << 5) | (uid
[27] << 4)
773 | (uid
[28] << 3) | (uid
[29] << 2) | (uid
[30] << 1) | uid
[31];
775 Dbprintf("UID: %02X %02X %02X %02X", uid1
, uid2
, uid3
, uid4
);
776 tag
.uid
= (uid4
<< 24 | uid3
<< 16 | uid2
<< 8 | uid1
);
781 calc_crc(&crc
, 0x00, 5);
782 calc_crc(&crc
, uid1
, 8);
783 calc_crc(&crc
, uid2
, 8);
784 calc_crc(&crc
, uid3
, 8);
785 calc_crc(&crc
, uid4
, 8);
786 for (i
= 0; i
< 100; i
++) {
789 for (i
= 0; i
< 5; i
++) {
792 for (i
= 5; i
< 37; i
++) {
793 response_bit
[i
] = uid
[i
- 5];
795 for (j
= 0; j
< 8; j
++) {
797 if ((crc
& ((mask
<< 7) >> j
)) != 0)
802 for (i
= 0; i
< 6; i
++) {
803 tx
[i
] = (response_bit
[k
] << 7) | (response_bit
[k
+ 1] << 6)
804 | (response_bit
[k
+ 2] << 5) | (response_bit
[k
+ 3] << 4)
805 | (response_bit
[k
+ 4] << 3) | (response_bit
[k
+ 5] << 2)
806 | (response_bit
[k
+ 6] << 1) | response_bit
[k
+ 7];
810 } else if (tag
.pstate
== INIT
&& rxlen
== 44) {
811 // received configuration after select command
813 for (i
= 0; i
< 6; i
++) {
814 for (j
= 0; j
< 8; j
++) {
816 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
821 conf_pages
[0] = ((response_bit
[4] << 7) | (response_bit
[5] << 6)
822 | (response_bit
[6] << 5) | (response_bit
[7] << 4)
823 | (response_bit
[8] << 3) | (response_bit
[9] << 2)
824 | (response_bit
[10] << 1) | response_bit
[11]);
825 //check wich memorysize this tag has
826 if (response_bit
[10] == 0 && response_bit
[11] == 0)
827 tag
.max_page
= 32 / 32;
828 if (response_bit
[10] == 0 && response_bit
[11] == 1)
829 tag
.max_page
= 256 / 32;
830 if (response_bit
[10] == 1 && response_bit
[11] == 0)
831 tag
.max_page
= 2048 / 32;
832 conf_pages
[1] = ((response_bit
[12] << 7) | (response_bit
[13] << 6)
833 | (response_bit
[14] << 5) | (response_bit
[15] << 4)
834 | (response_bit
[16] << 3) | (response_bit
[17] << 2)
835 | (response_bit
[18] << 1) | response_bit
[19]);
836 tag
.auth
= response_bit
[12];
837 tag
.TTFC
= response_bit
[13];
838 //tag.TTFDR in response_bit[14] and response_bit[15]
839 //tag.TTFM in response_bit[16] and response_bit[17]
840 tag
.LCON
= response_bit
[18];
841 tag
.LKP
= response_bit
[19];
842 conf_pages
[2] = ((response_bit
[20] << 7) | (response_bit
[21] << 6)
843 | (response_bit
[22] << 5) | (response_bit
[23] << 4)
844 | (response_bit
[24] << 3) | (response_bit
[25] << 2)
845 | (response_bit
[26] << 1) | response_bit
[27]);
846 tag
.LCK7
= response_bit
[20];
847 tag
.LCK6
= response_bit
[21];
848 tag
.LCK5
= response_bit
[22];
849 tag
.LCK4
= response_bit
[23];
850 tag
.LCK3
= response_bit
[24];
851 tag
.LCK2
= response_bit
[25];
852 tag
.LCK1
= response_bit
[26];
853 tag
.LCK0
= response_bit
[27];
856 Dbprintf("conf0: %02X conf1: %02X conf2: %02X", conf_pages
[0],
857 conf_pages
[1], conf_pages
[2]);
859 //if the tag is in authentication mode try the key or challenge
862 if(htf
==02||htf
==04){ //RHTS_KEY //WHTS_KEY
863 state
= hitag2_init(rev64(key
), rev32(tag
.uid
),
866 for (i
= 0; i
< 4; i
++) {
867 auth_ks
[i
] = hitag2_byte(&state
) ^ 0xff;
871 tx
[1] = (rnd
>> 8) & 0xff;
872 tx
[2] = (rnd
>> 16) & 0xff;
873 tx
[3] = (rnd
>> 24) & 0xff;
880 Dbprintf("%02X %02X %02X %02X %02X %02X %02X %02X", tx
[0],
881 tx
[1], tx
[2], tx
[3], tx
[4], tx
[5], tx
[6], tx
[7]);
882 } else if(htf
==01 || htf
==03) { //RHTS_CHALLENGE //WHTS_CHALLENGE
883 for (i
= 0; i
< 8; i
++)
884 tx
[i
]=((NrAr
>>(56-(i
*8)))&0xff);
887 tag
.pstate
= AUTHENTICATE
;
889 Dbprintf("authentication failed!");
892 } else if (tag
.auth
== 0) {
893 tag
.pstate
= SELECTED
;
896 } else if (tag
.pstate
== AUTHENTICATE
&& rxlen
== 44) {
897 //encrypted con2,password received.
899 calc_crc(&crc
, 0x80, 1);
900 calc_crc(&crc
, ((rx
[0] & 0x0f) * 16 + ((rx
[1] & 0xf0) / 16)), 8);
901 calc_crc(&crc
, ((rx
[1] & 0x0f) * 16 + ((rx
[2] & 0xf0) / 16)), 8);
902 calc_crc(&crc
, ((rx
[2] & 0x0f) * 16 + ((rx
[3] & 0xf0) / 16)), 8);
903 calc_crc(&crc
, ((rx
[3] & 0x0f) * 16 + ((rx
[4] & 0xf0) / 16)), 8);
905 Dbprintf("UID:::%X", tag
.uid
);
906 Dbprintf("RND:::%X", rnd
);
913 if(htf
==02 || htf
==04){ //RHTS_KEY //WHTS_KEY
915 state
= hitag2_init(rev64(key
), rev32(tag
.uid
), rev32(rnd
));
916 for (i
= 0; i
< 5; i
++)
918 pwdh0
= ((rx
[1] & 0x0f) * 16 + ((rx
[2] & 0xf0) / 16))
919 ^ hitag2_byte(&state
);
920 pwdl0
= ((rx
[2] & 0x0f) * 16 + ((rx
[3] & 0xf0) / 16))
921 ^ hitag2_byte(&state
);
922 pwdl1
= ((rx
[3] & 0x0f) * 16 + ((rx
[4] & 0xf0) / 16))
923 ^ hitag2_byte(&state
);
927 Dbprintf("pwdh0 %02X pwdl0 %02X pwdl1 %02X", pwdh0
, pwdl0
, pwdl1
);
930 //Dbprintf("%X %02X", rnd, ((rx[4] & 0x0f) * 16) + ((rx[5] & 0xf0) / 16));
933 tag
.pstate
= SELECTED
; //tag is now ready for read/write commands
940 * Emulates a Hitag S Tag with the given data from the .hts file
942 void SimulateHitagSTag(bool tag_mem_supplied
, byte_t
* data
) {
947 byte_t rx
[HITAG_FRAME_LEN
];
949 //bool bQuitTraceFull = false;
951 byte_t txbuf
[HITAG_FRAME_LEN
];
956 // Clean up trace and prepare it for storing frames
960 DbpString("Starting HitagS simulation");
965 for (i
= 0; i
< 16; i
++)
966 for (j
= 0; j
< 4; j
++)
967 tag
.pages
[i
][j
] = 0x0;
968 //read tag data into memory
969 if (tag_mem_supplied
) {
970 DbpString("Loading hitagS memory...");
971 memcpy((byte_t
*)tag
.pages
,data
,4*64);
973 tag
.uid
=(uint32_t)tag
.pages
[0];
974 Dbprintf("Hitag S simulation started");
975 tag
.key
=(intptr_t)tag
.pages
[3];
977 tag
.key
+=((tag
.pages
[2][0])<<8)+tag
.pages
[2][1];
978 tag
.pwdl0
=tag
.pages
[2][3];
979 tag
.pwdl1
=tag
.pages
[2][2];
980 tag
.pwdh0
=tag
.pages
[1][0];
983 if((tag
.pages
[1][3]&0x2)==0 && (tag
.pages
[1][3]&0x1)==1)
985 if((tag
.pages
[1][3]&0x2)==0 && (tag
.pages
[1][3]&0x1)==0)
989 if((tag
.pages
[1][2]&0x80)==1)
992 if((tag
.pages
[1][2]&0x2)==1)
995 if((tag
.pages
[1][2]&0x1)==1)
998 //0=read write 1=read only
1000 if((tag
.pages
[1][1]&0x80)==1)
1003 if((tag
.pages
[1][1]&0x40)==1)
1006 if((tag
.pages
[1][1]&0x20)==1)
1009 if((tag
.pages
[1][1]&0x10)==1)
1012 if((tag
.pages
[1][1]&0x8)==1)
1015 if((tag
.pages
[1][1]&0x4)==1)
1018 if((tag
.pages
[1][1]&0x2)==1)
1021 if((tag
.pages
[1][1]&0x1)==1)
1024 // Set up simulator mode, frequency divisor which will drive the FPGA
1025 // and analog mux selection.
1026 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1028 FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
1029 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1030 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1033 // Configure output pin that is connected to the FPGA (for modulating)
1034 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1035 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1037 // Disable modulation at default, which means release resistance
1040 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1041 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1043 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
1044 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1045 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1047 // Disable timer during configuration
1048 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1050 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1051 // external trigger rising edge, load RA on rising edge of TIOA.
1052 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1053 | AT91C_TC_ETRGEDG_RISING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_RISING
;
1055 // Reset the received frame, frame count and timing info
1056 memset(rx
, 0x00, sizeof(rx
));
1061 // Enable and reset counter
1062 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1064 while (!BUTTON_PRESS()) {
1068 // Receive frame, watch for at most T0*EOF periods
1069 while (AT91C_BASE_TC1
->TC_CV
< T0
* HITAG_T_EOF
) {
1070 // Check if rising edge in modulation is detected
1071 if (AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
1072 // Retrieve the new timing values
1073 int ra
= (AT91C_BASE_TC1
->TC_RA
/ T0
) + overflow
;
1076 // Reset timer every frame, we have to capture the last edge for timing
1077 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1081 // Capture reader frame
1082 if (ra
>= HITAG_T_STOP
) {
1084 //DbpString("wierd0?");
1086 // Capture the T0 periods that have passed since last communication or field drop (reset)
1087 response
= (ra
- HITAG_T_LOW
);
1088 } else if (ra
>= HITAG_T_1_MIN
) {
1090 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
1092 } else if (ra
>= HITAG_T_0_MIN
) {
1094 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
1097 // Ignore wierd value, is to small to mean anything
1102 // Check if frame was captured
1106 if (!LogTraceHitag(rx
, rxlen
, response
, 0, true)) {
1107 DbpString("Trace full");
1112 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1113 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1115 // Process the incoming frame (rx) and prepare the outgoing frame (tx)
1116 hitagS_handle_reader_command(rx
, rxlen
, tx
, &txlen
);
1118 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
1119 // not that since the clock counts since the rising edge, but T_Wait1 is
1120 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
1121 // periods. The gap time T_Low varies (4..10). All timer values are in
1122 // terms of T0 units
1123 while (AT91C_BASE_TC0
->TC_CV
< T0
* (HITAG_T_WAIT_1
- HITAG_T_LOW
))
1126 // Send and store the tag answer (if there is any)
1128 // Transmit the tag frame
1129 hitag_send_frame(tx
, txlen
);
1130 // Store the frame in the trace
1132 if (!LogTraceHitag(tx
, txlen
, 0, 0, false)) {
1133 DbpString("Trace full");
1139 // Reset the received frame and response timing info
1140 memset(rx
, 0x00, sizeof(rx
));
1143 // Enable and reset external trigger in timer for capturing future frames
1144 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1147 // Reset the frame length
1149 // Save the timer overflow, will be 0 when frame was received
1150 overflow
+= (AT91C_BASE_TC1
->TC_CV
/ T0
);
1151 // Reset the timer to restart while-loop that receives frames
1152 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_SWTRG
;
1156 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1157 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
1158 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1162 * Authenticates to the Tag with the given key or challenge.
1163 * If the key was given the password will be decrypted.
1164 * Reads every page of a hitag S transpoder.
1166 void ReadHitagS(hitag_function htf
, hitag_data
* htd
) {
1169 int response_bit
[200];
1171 byte_t rx
[HITAG_FRAME_LEN
];
1173 byte_t txbuf
[HITAG_FRAME_LEN
];
1180 int t_wait
= HITAG_T_WAIT_MAX
;
1182 bool bQuitTraceFull
= false;
1184 unsigned char mask
= 1;
1186 unsigned char pageData
[32];
1187 page_to_be_written
= 0;
1189 //read given key/challenge
1195 case 01: { //RHTS_CHALLENGE
1196 DbpString("Authenticating using nr,ar pair:");
1197 memcpy(NrAr_
,htd
->auth
.NrAr
,8);
1198 Dbhexdump(8,NrAr_
,false);
1199 NrAr
=NrAr_
[7] | ((uint64_t)NrAr_
[6]) << 8 | ((uint64_t)NrAr_
[5]) << 16 | ((uint64_t)NrAr_
[4]) << 24 | ((uint64_t)NrAr_
[3]) << 32 |
1200 ((uint64_t)NrAr_
[2]) << 40| ((uint64_t)NrAr_
[1]) << 48 | ((uint64_t)NrAr_
[0]) << 56;
1202 case 02: { //RHTS_KEY
1203 DbpString("Authenticating using key:");
1204 memcpy(key_
,htd
->crypto
.key
,6);
1205 Dbhexdump(6,key_
,false);
1206 key
=key_
[5] | ((uint64_t)key_
[4]) << 8 | ((uint64_t)key_
[3]) << 16 | ((uint64_t)key_
[2]) << 24 | ((uint64_t)key_
[1]) << 32 | ((uint64_t)key_
[0]) << 40;
1209 Dbprintf("Error , unknown function: %d",htf
);
1216 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1217 // Reset the return status
1218 bSuccessful
= false;
1220 // Clean up trace and prepare it for storing frames
1225 bQuitTraceFull
= true;
1229 // Configure output and enable pin that is connected to the FPGA (for modulating)
1230 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1231 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1233 // Set fpga in edge detect with reader field, we can modulate as reader now
1235 FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
1237 // Set Frequency divisor which will drive the FPGA and analog mux selection
1238 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1239 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1242 // Disable modulation at default, which means enable the field
1245 // Give it a bit of time for the resonant antenna to settle.
1248 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1249 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1251 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1252 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1253 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1255 // Disable timer during configuration
1256 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1258 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1259 // external trigger rising edge, load RA on falling edge of TIOA.
1260 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1262 | AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_FALLING
;
1264 // Enable and reset counters
1265 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1266 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1268 // Reset the received frame, frame count and timing info
1277 while (!bStop
&& !BUTTON_PRESS()) {
1281 // Check if frame was captured and store it
1285 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
1286 DbpString("Trace full");
1287 if (bQuitTraceFull
) {
1296 // By default reset the transmission buffer
1301 //start authentication
1303 memcpy(tx
, "\xc0", nbytes(txlen
));
1306 } else if (tag
.pstate
!= SELECTED
) {
1307 if (hitagS_handle_tag_auth(htf
, key
,NrAr
,rx
, rxlen
, tx
, &txlen
) == -1)
1310 if (tag
.pstate
== SELECTED
&& tag
.tstate
== NO_OP
&& rxlen
> 0) {
1312 tag
.tstate
= READING_PAGE
;
1315 tx
[0] = 0xc0 + (sendNum
/ 16);
1316 calc_crc(&crc
, tx
[0], 8);
1317 calc_crc(&crc
, 0x00 + ((sendNum
% 16) * 16), 4);
1318 tx
[1] = 0x00 + ((sendNum
% 16) * 16) + (crc
/ 16);
1319 tx
[2] = 0x00 + (crc
% 16) * 16;
1320 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== READING_PAGE
1322 //save received data
1324 for (i
= 0; i
< 5; i
++) {
1325 for (j
= 0; j
< 8; j
++) {
1326 response_bit
[z
] = 0;
1327 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
1328 response_bit
[z
] = 1;
1333 for (i
= 4; i
< 36; i
++) {
1334 pageData
[k
] = response_bit
[i
];
1337 for (i
= 0; i
< 4; i
++)
1338 tag
.pages
[sendNum
/ 4][sendNum
% 4] = 0x0;
1339 for (i
= 0; i
< 4; i
++) {
1340 tag
.pages
[sendNum
/ 4][sendNum
% 4] += ((pageData
[i
* 8] << 7)
1341 | (pageData
[1 + (i
* 8)] << 6)
1342 | (pageData
[2 + (i
* 8)] << 5)
1343 | (pageData
[3 + (i
* 8)] << 4)
1344 | (pageData
[4 + (i
* 8)] << 3)
1345 | (pageData
[5 + (i
* 8)] << 2)
1346 | (pageData
[6 + (i
* 8)] << 1) | pageData
[7 + (i
* 8)])
1349 if (tag
.auth
&& tag
.LKP
&& sendNum
== 1) {
1350 Dbprintf("Page[%2d]: %02X %02X %02X %02X", sendNum
, pwdh0
,
1351 (tag
.pages
[sendNum
/ 4][sendNum
% 4] >> 16) & 0xff,
1352 (tag
.pages
[sendNum
/ 4][sendNum
% 4] >> 8) & 0xff,
1353 tag
.pages
[sendNum
/ 4][sendNum
% 4] & 0xff);
1355 Dbprintf("Page[%2d]: %02X %02X %02X %02X", sendNum
,
1356 (tag
.pages
[sendNum
/ 4][sendNum
% 4] >> 24) & 0xff,
1357 (tag
.pages
[sendNum
/ 4][sendNum
% 4] >> 16) & 0xff,
1358 (tag
.pages
[sendNum
/ 4][sendNum
% 4] >> 8) & 0xff,
1359 tag
.pages
[sendNum
/ 4][sendNum
% 4] & 0xff);
1363 //display key and password if possible
1364 if (sendNum
== 2 && tag
.auth
== 1 && tag
.LKP
) {
1365 if (htf
== 02) { //RHTS_KEY
1366 Dbprintf("Page[ 2]: %02X %02X %02X %02X",
1367 (byte_t
)(key
>> 8) & 0xff,
1368 (byte_t
) key
& 0xff, pwdl1
, pwdl0
);
1369 Dbprintf("Page[ 3]: %02X %02X %02X %02X",
1370 (byte_t
)(key
>> 40) & 0xff,
1371 (byte_t
)(key
>> 32) & 0xff,
1372 (byte_t
)(key
>> 24) & 0xff,
1373 (byte_t
)(key
>> 16) & 0xff);
1375 //if the authentication is done with a challenge the key and password are unknown
1376 Dbprintf("Page[ 2]: __ __ __ __");
1377 Dbprintf("Page[ 3]: __ __ __ __");
1383 tx
[0] = 0xc0 + (sendNum
/ 16);
1384 calc_crc(&crc
, tx
[0], 8);
1385 calc_crc(&crc
, 0x00 + ((sendNum
% 16) * 16), 4);
1386 tx
[1] = 0x00 + ((sendNum
% 16) * 16) + (crc
/ 16);
1387 tx
[2] = 0x00 + (crc
% 16) * 16;
1388 if (sendNum
>= tag
.max_page
) {
1393 // Send and store the reader command
1394 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1395 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1397 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1398 // Since the clock counts since the last falling edge, a 'one' means that the
1399 // falling edge occured halfway the period. with respect to this falling edge,
1400 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1401 // All timer values are in terms of T0 units
1403 while (AT91C_BASE_TC0
->TC_CV
1404 < T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
)))
1407 // Transmit the reader frame
1408 hitag_reader_send_frame(tx
, txlen
);
1410 // Enable and reset external trigger in timer for capturing future frames
1411 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1413 // Add transmitted frame to total count
1417 // Store the frame in the trace
1418 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
1419 if (bQuitTraceFull
) {
1420 DbpString("Trace full");
1429 // Reset values for receiving frames
1430 memset(rx
, 0x00, sizeof(rx
));
1434 tag_sof
= reset_sof
;
1437 // Receive frame, watch for at most T0*EOF periods
1438 while (AT91C_BASE_TC1
->TC_CV
< T0
* HITAG_T_WAIT_MAX
) {
1439 // Check if falling edge in tag modulation is detected
1440 if (AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
1441 // Retrieve the new timing values
1442 int ra
= (AT91C_BASE_TC1
->TC_RA
/ T0
);
1444 // Reset timer every frame, we have to capture the last edge for timing
1445 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
1449 // Capture tag frame (manchester decoding using only falling edges)
1450 if (ra
>= HITAG_T_EOF
) {
1452 //DbpString("wierd1?");
1454 // Capture the T0 periods that have passed since last communication or field drop (reset)
1455 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
1456 response
= ra
- HITAG_T_TAG_HALF_PERIOD
;
1457 } else if (ra
>= HITAG_T_TAG_CAPTURE_FOUR_HALF
) {
1458 // Manchester coding example |-_|_-|-_| (101)
1459 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
1461 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
1463 } else if (ra
>= HITAG_T_TAG_CAPTURE_THREE_HALF
) {
1464 // Manchester coding example |_-|...|_-|-_| (0...01)
1465 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
1467 // We have to skip this half period at start and add the 'one' the second time
1469 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
1474 } else if (ra
>= HITAG_T_TAG_CAPTURE_TWO_HALF
) {
1475 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
1477 // Ignore bits that are transmitted during SOF
1480 // bit is same as last bit
1481 rx
[rxlen
/ 8] |= lastbit
<< (7 - (rxlen
% 8));
1485 // Ignore wierd value, is to small to mean anything
1489 // We can break this loop if we received the last bit from a frame
1490 if (AT91C_BASE_TC1
->TC_CV
> T0
* HITAG_T_EOF
) {
1499 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1500 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
1501 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1502 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);
1506 * Authenticates to the Tag with the given Key or Challenge.
1507 * Writes the given 32Bit data into page_
1509 void WritePageHitagS(hitag_function htf
, hitag_data
* htd
,int page_
) {
1512 byte_t rx
[HITAG_FRAME_LEN
];
1514 byte_t txbuf
[HITAG_FRAME_LEN
];
1521 int t_wait
= HITAG_T_WAIT_MAX
;
1523 bool bQuitTraceFull
= false;
1526 byte_t data
[4]= {0,0,0,0};
1528 //read given key/challenge, the page and the data
1534 case 03: { //WHTS_CHALLENGE
1535 memcpy(data
,htd
->auth
.data
,4);
1536 DbpString("Authenticating using nr,ar pair:");
1537 memcpy(NrAr_
,htd
->auth
.NrAr
,8);
1538 Dbhexdump(8,NrAr_
,false);
1539 NrAr
=NrAr_
[7] | ((uint64_t)NrAr_
[6]) << 8 | ((uint64_t)NrAr_
[5]) << 16 | ((uint64_t)NrAr_
[4]) << 24 | ((uint64_t)NrAr_
[3]) << 32 |
1540 ((uint64_t)NrAr_
[2]) << 40| ((uint64_t)NrAr_
[1]) << 48 | ((uint64_t)NrAr_
[0]) << 56;
1542 case 04: { //WHTS_KEY
1543 memcpy(data
,htd
->crypto
.data
,4);
1544 DbpString("Authenticating using key:");
1545 memcpy(key_
,htd
->crypto
.key
,6);
1546 Dbhexdump(6,key_
,false);
1547 key
=key_
[5] | ((uint64_t)key_
[4]) << 8 | ((uint64_t)key_
[3]) << 16 | ((uint64_t)key_
[2]) << 24 | ((uint64_t)key_
[1]) << 32 | ((uint64_t)key_
[0]) << 40;
1550 Dbprintf("Error , unknown function: %d",htf
);
1555 Dbprintf("Page: %d",page_
);
1556 Dbprintf("DATA: %02X %02X %02X %02X", data
[0], data
[1], data
[2], data
[3]);
1557 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1558 // Reset the return status
1559 bSuccessful
= false;
1564 // Clean up trace and prepare it for storing frames
1569 bQuitTraceFull
= true;
1573 // Configure output and enable pin that is connected to the FPGA (for modulating)
1574 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1575 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1577 // Set fpga in edge detect with reader field, we can modulate as reader now
1579 FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
1581 // Set Frequency divisor which will drive the FPGA and analog mux selection
1582 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1583 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1586 // Disable modulation at default, which means enable the field
1589 // Give it a bit of time for the resonant antenna to settle.
1592 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1593 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1595 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1596 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1597 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1599 // Disable timer during configuration
1600 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1602 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1603 // external trigger rising edge, load RA on falling edge of TIOA.
1604 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1605 | AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
1606 | AT91C_TC_LDRA_FALLING
;
1608 // Enable and reset counters
1609 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1610 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1612 // Reset the received frame, frame count and timing info
1621 while (!bStop
&& !BUTTON_PRESS()) {
1625 // Check if frame was captured and store it
1629 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
1630 DbpString("Trace full");
1631 if (bQuitTraceFull
) {
1640 //check for valid input
1643 "usage: lf hitag writer [03 | 04] [CHALLENGE | KEY] [page] [byte0] [byte1] [byte2] [byte3]");
1647 // By default reset the transmission buffer
1651 if (rxlen
== 0 && tag
.tstate
== WRITING_PAGE_ACK
) {
1652 //no write access on this page
1653 Dbprintf("no write access on page %d", page_
);
1655 } else if (rxlen
== 0 && tag
.tstate
!= WRITING_PAGE_DATA
) {
1656 //start the authetication
1658 memcpy(tx
, "\xc0", nbytes(txlen
));
1661 } else if (tag
.pstate
!= SELECTED
) {
1662 //try to authenticate with the given key or challenge
1663 if (hitagS_handle_tag_auth(htf
,key
,NrAr
,rx
, rxlen
, tx
, &txlen
) == -1)
1666 if (tag
.pstate
== SELECTED
&& tag
.tstate
== NO_OP
&& rxlen
> 0) {
1667 //check if the given page exists
1668 if (page
> tag
.max_page
) {
1669 Dbprintf("page number too big");
1672 //ask Tag for write permission
1673 tag
.tstate
= WRITING_PAGE_ACK
;
1676 tx
[0] = 0x90 + (page
/ 16);
1677 calc_crc(&crc
, tx
[0], 8);
1678 calc_crc(&crc
, 0x00 + ((page
% 16) * 16), 4);
1679 tx
[1] = 0x00 + ((page
% 16) * 16) + (crc
/ 16);
1680 tx
[2] = 0x00 + (crc
% 16) * 16;
1681 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== WRITING_PAGE_ACK
1682 && rxlen
== 6 && rx
[0] == 0xf4) {
1683 //ACK recieved to write the page. send data
1684 tag
.tstate
= WRITING_PAGE_DATA
;
1687 calc_crc(&crc
, data
[3], 8);
1688 calc_crc(&crc
, data
[2], 8);
1689 calc_crc(&crc
, data
[1], 8);
1690 calc_crc(&crc
, data
[0], 8);
1696 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== WRITING_PAGE_DATA
1697 && rxlen
== 6 && rx
[0] == 0xf4) {
1699 Dbprintf("Successful!");
1703 // Send and store the reader command
1704 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1705 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1707 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1708 // Since the clock counts since the last falling edge, a 'one' means that the
1709 // falling edge occured halfway the period. with respect to this falling edge,
1710 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1711 // All timer values are in terms of T0 units
1713 while (AT91C_BASE_TC0
->TC_CV
1714 < T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
)))
1717 // Transmit the reader frame
1718 hitag_reader_send_frame(tx
, txlen
);
1720 // Enable and reset external trigger in timer for capturing future frames
1721 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1723 // Add transmitted frame to total count
1727 // Store the frame in the trace
1728 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
1729 if (bQuitTraceFull
) {
1730 DbpString("Trace full");
1739 // Reset values for receiving frames
1740 memset(rx
, 0x00, sizeof(rx
));
1744 tag_sof
= reset_sof
;
1747 // Receive frame, watch for at most T0*EOF periods
1748 while (AT91C_BASE_TC1
->TC_CV
< T0
* HITAG_T_WAIT_MAX
) {
1749 // Check if falling edge in tag modulation is detected
1750 if (AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
1751 // Retrieve the new timing values
1752 int ra
= (AT91C_BASE_TC1
->TC_RA
/ T0
);
1754 // Reset timer every frame, we have to capture the last edge for timing
1755 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
1759 // Capture tag frame (manchester decoding using only falling edges)
1760 if (ra
>= HITAG_T_EOF
) {
1762 //DbpString("wierd1?");
1764 // Capture the T0 periods that have passed since last communication or field drop (reset)
1765 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
1766 response
= ra
- HITAG_T_TAG_HALF_PERIOD
;
1767 } else if (ra
>= HITAG_T_TAG_CAPTURE_FOUR_HALF
) {
1768 // Manchester coding example |-_|_-|-_| (101)
1769 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
1771 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
1773 } else if (ra
>= HITAG_T_TAG_CAPTURE_THREE_HALF
) {
1774 // Manchester coding example |_-|...|_-|-_| (0...01)
1775 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
1777 // We have to skip this half period at start and add the 'one' the second time
1779 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
1784 } else if (ra
>= HITAG_T_TAG_CAPTURE_TWO_HALF
) {
1785 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
1787 // Ignore bits that are transmitted during SOF
1790 // bit is same as last bit
1791 rx
[rxlen
/ 8] |= lastbit
<< (7 - (rxlen
% 8));
1795 // Ignore wierd value, is to small to mean anything
1799 // We can break this loop if we received the last bit from a frame
1800 if (AT91C_BASE_TC1
->TC_CV
> T0
* HITAG_T_EOF
) {
1809 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1810 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
1811 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1812 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);
1816 * Tries to authenticate to a Hitag S Transponder with the given challenges from a .cc file.
1817 * Displays all Challenges that failed.
1818 * When collecting Challenges to break the key it is possible that some data
1819 * is not received correctly due to Antenna problems. This function
1820 * detects these challenges.
1822 void check_challenges(bool file_given
, byte_t
* data
) {
1827 byte_t rx
[HITAG_FRAME_LEN
];
1828 byte_t unlocker
[60][8];
1831 byte_t txbuf
[HITAG_FRAME_LEN
];
1838 int t_wait
= HITAG_T_WAIT_MAX
;
1841 bool bQuitTraceFull
= false;
1842 int response_bit
[200];
1843 unsigned char mask
= 1;
1844 unsigned char uid
[32];
1847 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1848 // Reset the return status
1849 bSuccessful
= false;
1851 // Clean up trace and prepare it for storing frames
1856 bQuitTraceFull
= true;
1860 // Configure output and enable pin that is connected to the FPGA (for modulating)
1861 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1862 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1864 // Set fpga in edge detect with reader field, we can modulate as reader now
1866 FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
1868 // Set Frequency divisor which will drive the FPGA and analog mux selection
1869 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1870 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1873 // Disable modulation at default, which means enable the field
1876 // Give it a bit of time for the resonant antenna to settle.
1879 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1880 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1882 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1883 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1884 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1886 // Disable timer during configuration
1887 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1889 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1890 // external trigger rising edge, load RA on falling edge of TIOA.
1891 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1893 | AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_FALLING
;
1895 // Enable and reset counters
1896 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1897 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1899 // Reset the received frame, frame count and timing info
1909 DbpString("Loading challenges...");
1910 memcpy((byte_t
*)unlocker
,data
,60*8);
1913 while (file_given
&& !bStop
&& !BUTTON_PRESS()) {
1917 // Check if frame was captured and store it
1921 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
1922 DbpString("Trace full");
1923 if (bQuitTraceFull
) {
1937 Dbprintf("Challenge failed: %02X %02X %02X %02X %02X %02X %02X %02X",
1938 unlocker
[u1
- 1][0], unlocker
[u1
- 1][1],
1939 unlocker
[u1
- 1][2], unlocker
[u1
- 1][3],
1940 unlocker
[u1
- 1][4], unlocker
[u1
- 1][5],
1941 unlocker
[u1
- 1][6], unlocker
[u1
- 1][7]);
1944 //start new authentication
1945 memcpy(tx
, "\xc0", nbytes(txlen
));
1946 } else if (rxlen
>= 67 && STATE
== 0) {
1949 for (i
= 0; i
< 10; i
++) {
1950 for (j
= 0; j
< 8; j
++) {
1951 response_bit
[z
] = 0;
1952 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
1953 response_bit
[z
] = 1;
1958 for (i
= 5; i
< z
; i
+= 2) {
1959 uid
[k
] = response_bit
[i
];
1964 uid_byte
[0] = (uid
[0] << 7) | (uid
[1] << 6) | (uid
[2] << 5)
1965 | (uid
[3] << 4) | (uid
[4] << 3) | (uid
[5] << 2)
1966 | (uid
[6] << 1) | uid
[7];
1967 uid_byte
[1] = (uid
[8] << 7) | (uid
[9] << 6) | (uid
[10] << 5)
1968 | (uid
[11] << 4) | (uid
[12] << 3) | (uid
[13] << 2)
1969 | (uid
[14] << 1) | uid
[15];
1970 uid_byte
[2] = (uid
[16] << 7) | (uid
[17] << 6) | (uid
[18] << 5)
1971 | (uid
[19] << 4) | (uid
[20] << 3) | (uid
[21] << 2)
1972 | (uid
[22] << 1) | uid
[23];
1973 uid_byte
[3] = (uid
[24] << 7) | (uid
[25] << 6) | (uid
[26] << 5)
1974 | (uid
[27] << 4) | (uid
[28] << 3) | (uid
[29] << 2)
1975 | (uid
[30] << 1) | uid
[31];
1976 //Dbhexdump(10, rx, rxlen);
1980 calc_crc(&crc
, 0x00, 5);
1981 calc_crc(&crc
, uid_byte
[0], 8);
1982 calc_crc(&crc
, uid_byte
[1], 8);
1983 calc_crc(&crc
, uid_byte
[2], 8);
1984 calc_crc(&crc
, uid_byte
[3], 8);
1985 for (i
= 0; i
< 100; i
++) {
1986 response_bit
[i
] = 0;
1988 for (i
= 0; i
< 5; i
++) {
1989 response_bit
[i
] = 0;
1991 for (i
= 5; i
< 37; i
++) {
1992 response_bit
[i
] = uid
[i
- 5];
1994 for (j
= 0; j
< 8; j
++) {
1995 response_bit
[i
] = 0;
1996 if ((crc
& ((mask
<< 7) >> j
)) != 0)
1997 response_bit
[i
] = 1;
2001 for (i
= 0; i
< 6; i
++) {
2002 tx
[i
] = (response_bit
[k
] << 7) | (response_bit
[k
+ 1] << 6)
2003 | (response_bit
[k
+ 2] << 5)
2004 | (response_bit
[k
+ 3] << 4)
2005 | (response_bit
[k
+ 4] << 3)
2006 | (response_bit
[k
+ 5] << 2)
2007 | (response_bit
[k
+ 6] << 1) | response_bit
[k
+ 7];
2011 } else if (STATE
== 1 && rxlen
== 44) {
2012 //received configuration
2015 for (i
= 0; i
< 6; i
++) {
2016 for (j
= 0; j
< 8; j
++) {
2017 response_bit
[z
] = 0;
2018 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
2019 response_bit
[z
] = 1;
2025 if (u1
>= (sizeof(unlocker
) / sizeof(unlocker
[0])))
2027 for (i
= 0; i
< 8; i
++)
2028 tx
[i
] = unlocker
[u1
][i
];
2031 } else if (STATE
== 2 && rxlen
>= 44) {
2035 // Send and store the reader command
2036 // Disable timer 1 with external trigger to avoid triggers during our own modulation
2037 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2039 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
2040 // Since the clock counts since the last falling edge, a 'one' means that the
2041 // falling edge occured halfway the period. with respect to this falling edge,
2042 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
2043 // All timer values are in terms of T0 units
2045 while (AT91C_BASE_TC0
->TC_CV
2046 < T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
)))
2049 // Transmit the reader frame
2050 hitag_reader_send_frame(tx
, txlen
);
2052 // Enable and reset external trigger in timer for capturing future frames
2053 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2055 // Add transmitted frame to total count
2059 // Store the frame in the trace
2060 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
2061 if (bQuitTraceFull
) {
2062 DbpString("Trace full");
2071 // Reset values for receiving frames
2072 memset(rx
, 0x00, sizeof(rx
));
2076 tag_sof
= reset_sof
;
2079 // Receive frame, watch for at most T0*EOF periods
2080 while (AT91C_BASE_TC1
->TC_CV
< T0
* HITAG_T_WAIT_MAX
) {
2081 // Check if falling edge in tag modulation is detected
2082 if (AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
2083 // Retrieve the new timing values
2084 int ra
= (AT91C_BASE_TC1
->TC_RA
/ T0
);
2086 // Reset timer every frame, we have to capture the last edge for timing
2087 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
2091 // Capture tag frame (manchester decoding using only falling edges)
2092 if (ra
>= HITAG_T_EOF
) {
2094 //DbpString("wierd1?");
2096 // Capture the T0 periods that have passed since last communication or field drop (reset)
2097 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
2098 response
= ra
- HITAG_T_TAG_HALF_PERIOD
;
2099 } else if (ra
>= HITAG_T_TAG_CAPTURE_FOUR_HALF
) {
2100 // Manchester coding example |-_|_-|-_| (101)
2101 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
2103 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
2105 } else if (ra
>= HITAG_T_TAG_CAPTURE_THREE_HALF
) {
2106 // Manchester coding example |_-|...|_-|-_| (0...01)
2107 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
2109 // We have to skip this half period at start and add the 'one' the second time
2111 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
2116 } else if (ra
>= HITAG_T_TAG_CAPTURE_TWO_HALF
) {
2117 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
2119 // Ignore bits that are transmitted during SOF
2122 // bit is same as last bit
2123 rx
[rxlen
/ 8] |= lastbit
<< (7 - (rxlen
% 8));
2127 // Ignore wierd value, is to small to mean anything
2131 // We can break this loop if we received the last bit from a frame
2132 if (AT91C_BASE_TC1
->TC_CV
> T0
* HITAG_T_EOF
) {
2140 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2141 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
2142 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2143 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);