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Minor changes in iso1443-standalone mode
[proxmark3-svn] / armsrc / iso14443b.c
1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to support ISO 14443B. This includes both the reader software and
9 // the `fake tag' modes.
10 //-----------------------------------------------------------------------------
11
12 #include "proxmark3.h"
13 #include "apps.h"
14 #include "util.h"
15 #include "string.h"
16
17 #include "iso14443crc.h"
18
19 #define RECEIVE_SAMPLES_TIMEOUT 2000
20 #define ISO14443B_DMA_BUFFER_SIZE 256
21
22 // PCB Block number for APDUs
23 static uint8_t pcb_blocknum = 0;
24
25 //=============================================================================
26 // An ISO 14443 Type B tag. We listen for commands from the reader, using
27 // a UART kind of thing that's implemented in software. When we get a
28 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
29 // If it's good, then we can do something appropriate with it, and send
30 // a response.
31 //=============================================================================
32
33 //-----------------------------------------------------------------------------
34 // Code up a string of octets at layer 2 (including CRC, we don't generate
35 // that here) so that they can be transmitted to the reader. Doesn't transmit
36 // them yet, just leaves them ready to send in ToSend[].
37 //-----------------------------------------------------------------------------
38 static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
39 {
40 int i;
41
42 ToSendReset();
43
44 // Transmit a burst of ones, as the initial thing that lets the
45 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
46 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
47 // so I will too.
48 for(i = 0; i < 20; i++) {
49 ToSendStuffBit(1);
50 ToSendStuffBit(1);
51 ToSendStuffBit(1);
52 ToSendStuffBit(1);
53 }
54
55 // Send SOF.
56 for(i = 0; i < 10; i++) {
57 ToSendStuffBit(0);
58 ToSendStuffBit(0);
59 ToSendStuffBit(0);
60 ToSendStuffBit(0);
61 }
62 for(i = 0; i < 2; i++) {
63 ToSendStuffBit(1);
64 ToSendStuffBit(1);
65 ToSendStuffBit(1);
66 ToSendStuffBit(1);
67 }
68
69 for(i = 0; i < len; i++) {
70 int j;
71 uint8_t b = cmd[i];
72
73 // Start bit
74 ToSendStuffBit(0);
75 ToSendStuffBit(0);
76 ToSendStuffBit(0);
77 ToSendStuffBit(0);
78
79 // Data bits
80 for(j = 0; j < 8; j++) {
81 if(b & 1) {
82 ToSendStuffBit(1);
83 ToSendStuffBit(1);
84 ToSendStuffBit(1);
85 ToSendStuffBit(1);
86 } else {
87 ToSendStuffBit(0);
88 ToSendStuffBit(0);
89 ToSendStuffBit(0);
90 ToSendStuffBit(0);
91 }
92 b >>= 1;
93 }
94
95 // Stop bit
96 ToSendStuffBit(1);
97 ToSendStuffBit(1);
98 ToSendStuffBit(1);
99 ToSendStuffBit(1);
100 }
101
102 // Send EOF.
103 for(i = 0; i < 10; i++) {
104 ToSendStuffBit(0);
105 ToSendStuffBit(0);
106 ToSendStuffBit(0);
107 ToSendStuffBit(0);
108 }
109 for(i = 0; i < 2; i++) {
110 ToSendStuffBit(1);
111 ToSendStuffBit(1);
112 ToSendStuffBit(1);
113 ToSendStuffBit(1);
114 }
115
116 // Convert from last byte pos to length
117 ToSendMax++;
118 }
119
120 //-----------------------------------------------------------------------------
121 // The software UART that receives commands from the reader, and its state
122 // variables.
123 //-----------------------------------------------------------------------------
124 static struct {
125 enum {
126 STATE_UNSYNCD,
127 STATE_GOT_FALLING_EDGE_OF_SOF,
128 STATE_AWAITING_START_BIT,
129 STATE_RECEIVING_DATA
130 } state;
131 uint16_t shiftReg;
132 int bitCnt;
133 int byteCnt;
134 int byteCntMax;
135 int posCnt;
136 uint8_t *output;
137 } Uart;
138
139 /* Receive & handle a bit coming from the reader.
140 *
141 * This function is called 4 times per bit (every 2 subcarrier cycles).
142 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
143 *
144 * LED handling:
145 * LED A -> ON once we have received the SOF and are expecting the rest.
146 * LED A -> OFF once we have received EOF or are in error state or unsynced
147 *
148 * Returns: true if we received a EOF
149 * false if we are still waiting for some more
150 */
151 static RAMFUNC int Handle14443bUartBit(uint8_t bit)
152 {
153 switch(Uart.state) {
154 case STATE_UNSYNCD:
155 if(!bit) {
156 // we went low, so this could be the beginning
157 // of an SOF
158 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
159 Uart.posCnt = 0;
160 Uart.bitCnt = 0;
161 }
162 break;
163
164 case STATE_GOT_FALLING_EDGE_OF_SOF:
165 Uart.posCnt++;
166 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
167 if(bit) {
168 if(Uart.bitCnt > 9) {
169 // we've seen enough consecutive
170 // zeros that it's a valid SOF
171 Uart.posCnt = 0;
172 Uart.byteCnt = 0;
173 Uart.state = STATE_AWAITING_START_BIT;
174 LED_A_ON(); // Indicate we got a valid SOF
175 } else {
176 // didn't stay down long enough
177 // before going high, error
178 Uart.state = STATE_UNSYNCD;
179 }
180 } else {
181 // do nothing, keep waiting
182 }
183 Uart.bitCnt++;
184 }
185 if(Uart.posCnt >= 4) Uart.posCnt = 0;
186 if(Uart.bitCnt > 12) {
187 // Give up if we see too many zeros without
188 // a one, too.
189 LED_A_OFF();
190 Uart.state = STATE_UNSYNCD;
191 }
192 break;
193
194 case STATE_AWAITING_START_BIT:
195 Uart.posCnt++;
196 if(bit) {
197 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
198 // stayed high for too long between
199 // characters, error
200 Uart.state = STATE_UNSYNCD;
201 }
202 } else {
203 // falling edge, this starts the data byte
204 Uart.posCnt = 0;
205 Uart.bitCnt = 0;
206 Uart.shiftReg = 0;
207 Uart.state = STATE_RECEIVING_DATA;
208 }
209 break;
210
211 case STATE_RECEIVING_DATA:
212 Uart.posCnt++;
213 if(Uart.posCnt == 2) {
214 // time to sample a bit
215 Uart.shiftReg >>= 1;
216 if(bit) {
217 Uart.shiftReg |= 0x200;
218 }
219 Uart.bitCnt++;
220 }
221 if(Uart.posCnt >= 4) {
222 Uart.posCnt = 0;
223 }
224 if(Uart.bitCnt == 10) {
225 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
226 {
227 // this is a data byte, with correct
228 // start and stop bits
229 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
230 Uart.byteCnt++;
231
232 if(Uart.byteCnt >= Uart.byteCntMax) {
233 // Buffer overflowed, give up
234 LED_A_OFF();
235 Uart.state = STATE_UNSYNCD;
236 } else {
237 // so get the next byte now
238 Uart.posCnt = 0;
239 Uart.state = STATE_AWAITING_START_BIT;
240 }
241 } else if (Uart.shiftReg == 0x000) {
242 // this is an EOF byte
243 LED_A_OFF(); // Finished receiving
244 Uart.state = STATE_UNSYNCD;
245 if (Uart.byteCnt != 0) {
246 return TRUE;
247 }
248 } else {
249 // this is an error
250 LED_A_OFF();
251 Uart.state = STATE_UNSYNCD;
252 }
253 }
254 break;
255
256 default:
257 LED_A_OFF();
258 Uart.state = STATE_UNSYNCD;
259 break;
260 }
261
262 return FALSE;
263 }
264
265
266 static void UartReset()
267 {
268 Uart.byteCntMax = MAX_FRAME_SIZE;
269 Uart.state = STATE_UNSYNCD;
270 Uart.byteCnt = 0;
271 Uart.bitCnt = 0;
272 }
273
274
275 static void UartInit(uint8_t *data)
276 {
277 Uart.output = data;
278 UartReset();
279 }
280
281
282 //-----------------------------------------------------------------------------
283 // Receive a command (from the reader to us, where we are the simulated tag),
284 // and store it in the given buffer, up to the given maximum length. Keeps
285 // spinning, waiting for a well-framed command, until either we get one
286 // (returns TRUE) or someone presses the pushbutton on the board (FALSE).
287 //
288 // Assume that we're called with the SSC (to the FPGA) and ADC path set
289 // correctly.
290 //-----------------------------------------------------------------------------
291 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
292 {
293 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
294 // only, since we are receiving, not transmitting).
295 // Signal field is off with the appropriate LED
296 LED_D_OFF();
297 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
298
299 // Now run a `software UART' on the stream of incoming samples.
300 UartInit(received);
301
302 for(;;) {
303 WDT_HIT();
304
305 if(BUTTON_PRESS()) return FALSE;
306
307 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
308 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
309 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
310 if(Handle14443bUartBit(b & mask)) {
311 *len = Uart.byteCnt;
312 return TRUE;
313 }
314 }
315 }
316 }
317
318 return FALSE;
319 }
320
321 //-----------------------------------------------------------------------------
322 // Main loop of simulated tag: receive commands from reader, decide what
323 // response to send, and send it.
324 //-----------------------------------------------------------------------------
325 void SimulateIso14443bTag(void)
326 {
327 // the only commands we understand is REQB, AFI=0, Select All, N=0:
328 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
329 // ... and REQB, AFI=0, Normal Request, N=0:
330 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF };
331
332 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
333 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
334 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
335 static const uint8_t response1[] = {
336 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
337 0x00, 0x21, 0x85, 0x5e, 0xd7
338 };
339
340 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
341
342 clear_trace();
343 set_tracing(TRUE);
344
345 const uint8_t *resp;
346 uint8_t *respCode;
347 uint16_t respLen, respCodeLen;
348
349 // allocate command receive buffer
350 BigBuf_free();
351 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
352
353 uint16_t len;
354 uint16_t cmdsRecvd = 0;
355
356 // prepare the (only one) tag answer:
357 CodeIso14443bAsTag(response1, sizeof(response1));
358 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
359 memcpy(resp1Code, ToSend, ToSendMax);
360 uint16_t resp1CodeLen = ToSendMax;
361
362 // We need to listen to the high-frequency, peak-detected path.
363 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
364 FpgaSetupSsc();
365
366 cmdsRecvd = 0;
367
368 for(;;) {
369
370 if(!GetIso14443bCommandFromReader(receivedCmd, &len)) {
371 Dbprintf("button pressed, received %d commands", cmdsRecvd);
372 break;
373 }
374
375 if (tracing) {
376 uint8_t parity[MAX_PARITY_SIZE];
377 LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
378 }
379
380 // Good, look at the command now.
381 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
382 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
383 resp = response1;
384 respLen = sizeof(response1);
385 respCode = resp1Code;
386 respCodeLen = resp1CodeLen;
387 } else {
388 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
389 // And print whether the CRC fails, just for good measure
390 uint8_t b1, b2;
391 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
392 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
393 // Not so good, try again.
394 DbpString("+++CRC fail");
395 } else {
396 DbpString("CRC passes");
397 }
398 break;
399 }
400
401 cmdsRecvd++;
402
403 if(cmdsRecvd > 0x30) {
404 DbpString("many commands later...");
405 break;
406 }
407
408 if(respCodeLen <= 0) continue;
409
410 // Modulate BPSK
411 // Signal field is off with the appropriate LED
412 LED_D_OFF();
413 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
414 AT91C_BASE_SSC->SSC_THR = 0xff;
415 FpgaSetupSsc();
416
417 // Transmit the response.
418 uint16_t i = 0;
419 for(;;) {
420 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
421 uint8_t b = respCode[i];
422
423 AT91C_BASE_SSC->SSC_THR = b;
424
425 i++;
426 if(i > respCodeLen) {
427 break;
428 }
429 }
430 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
431 volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
432 (void)b;
433 }
434 }
435
436 // trace the response:
437 if (tracing) {
438 uint8_t parity[MAX_PARITY_SIZE];
439 LogTrace(resp, respLen, 0, 0, parity, FALSE);
440 }
441
442 }
443 }
444
445 //=============================================================================
446 // An ISO 14443 Type B reader. We take layer two commands, code them
447 // appropriately, and then send them to the tag. We then listen for the
448 // tag's response, which we leave in the buffer to be demodulated on the
449 // PC side.
450 //=============================================================================
451
452 static struct {
453 enum {
454 DEMOD_UNSYNCD,
455 DEMOD_PHASE_REF_TRAINING,
456 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
457 DEMOD_GOT_FALLING_EDGE_OF_SOF,
458 DEMOD_AWAITING_START_BIT,
459 DEMOD_RECEIVING_DATA
460 } state;
461 int bitCount;
462 int posCount;
463 int thisBit;
464 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
465 int metric;
466 int metricN;
467 */
468 uint16_t shiftReg;
469 uint8_t *output;
470 int len;
471 int sumI;
472 int sumQ;
473 } Demod;
474
475 /*
476 * Handles reception of a bit from the tag
477 *
478 * This function is called 2 times per bit (every 4 subcarrier cycles).
479 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
480 *
481 * LED handling:
482 * LED C -> ON once we have received the SOF and are expecting the rest.
483 * LED C -> OFF once we have received EOF or are unsynced
484 *
485 * Returns: true if we received a EOF
486 * false if we are still waiting for some more
487 *
488 */
489 static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
490 {
491 int v;
492
493 // The soft decision on the bit uses an estimate of just the
494 // quadrant of the reference angle, not the exact angle.
495 #define MAKE_SOFT_DECISION() { \
496 if(Demod.sumI > 0) { \
497 v = ci; \
498 } else { \
499 v = -ci; \
500 } \
501 if(Demod.sumQ > 0) { \
502 v += cq; \
503 } else { \
504 v -= cq; \
505 } \
506 }
507
508 #define SUBCARRIER_DETECT_THRESHOLD 8
509
510 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
511 /* #define CHECK_FOR_SUBCARRIER() { \
512 v = ci; \
513 if(v < 0) v = -v; \
514 if(cq > 0) { \
515 v += cq; \
516 } else { \
517 v -= cq; \
518 } \
519 }
520 */
521 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
522 #define CHECK_FOR_SUBCARRIER() { \
523 if(ci < 0) { \
524 if(cq < 0) { /* ci < 0, cq < 0 */ \
525 if (cq < ci) { \
526 v = -cq - (ci >> 1); \
527 } else { \
528 v = -ci - (cq >> 1); \
529 } \
530 } else { /* ci < 0, cq >= 0 */ \
531 if (cq < -ci) { \
532 v = -ci + (cq >> 1); \
533 } else { \
534 v = cq - (ci >> 1); \
535 } \
536 } \
537 } else { \
538 if(cq < 0) { /* ci >= 0, cq < 0 */ \
539 if (-cq < ci) { \
540 v = ci - (cq >> 1); \
541 } else { \
542 v = -cq + (ci >> 1); \
543 } \
544 } else { /* ci >= 0, cq >= 0 */ \
545 if (cq < ci) { \
546 v = ci + (cq >> 1); \
547 } else { \
548 v = cq + (ci >> 1); \
549 } \
550 } \
551 } \
552 }
553
554 switch(Demod.state) {
555 case DEMOD_UNSYNCD:
556 CHECK_FOR_SUBCARRIER();
557 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
558 Demod.state = DEMOD_PHASE_REF_TRAINING;
559 Demod.sumI = ci;
560 Demod.sumQ = cq;
561 Demod.posCount = 1;
562 }
563 break;
564
565 case DEMOD_PHASE_REF_TRAINING:
566 if(Demod.posCount < 8) {
567 CHECK_FOR_SUBCARRIER();
568 if (v > SUBCARRIER_DETECT_THRESHOLD) {
569 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
570 // note: synchronization time > 80 1/fs
571 Demod.sumI += ci;
572 Demod.sumQ += cq;
573 Demod.posCount++;
574 } else { // subcarrier lost
575 Demod.state = DEMOD_UNSYNCD;
576 }
577 } else {
578 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
579 }
580 break;
581
582 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
583 MAKE_SOFT_DECISION();
584 if(v < 0) { // logic '0' detected
585 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
586 Demod.posCount = 0; // start of SOF sequence
587 } else {
588 if(Demod.posCount > 200/4) { // maximum length of TR1 = 200 1/fs
589 Demod.state = DEMOD_UNSYNCD;
590 }
591 }
592 Demod.posCount++;
593 break;
594
595 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
596 Demod.posCount++;
597 MAKE_SOFT_DECISION();
598 if(v > 0) {
599 if(Demod.posCount < 9*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
600 Demod.state = DEMOD_UNSYNCD;
601 } else {
602 LED_C_ON(); // Got SOF
603 Demod.state = DEMOD_AWAITING_START_BIT;
604 Demod.posCount = 0;
605 Demod.len = 0;
606 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
607 Demod.metricN = 0;
608 Demod.metric = 0;
609 */
610 }
611 } else {
612 if(Demod.posCount > 12*2) { // low phase of SOF too long (> 12 etu)
613 Demod.state = DEMOD_UNSYNCD;
614 LED_C_OFF();
615 }
616 }
617 break;
618
619 case DEMOD_AWAITING_START_BIT:
620 Demod.posCount++;
621 MAKE_SOFT_DECISION();
622 if(v > 0) {
623 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
624 Demod.state = DEMOD_UNSYNCD;
625 LED_C_OFF();
626 }
627 } else { // start bit detected
628 Demod.bitCount = 0;
629 Demod.posCount = 1; // this was the first half
630 Demod.thisBit = v;
631 Demod.shiftReg = 0;
632 Demod.state = DEMOD_RECEIVING_DATA;
633 }
634 break;
635
636 case DEMOD_RECEIVING_DATA:
637 MAKE_SOFT_DECISION();
638 if(Demod.posCount == 0) { // first half of bit
639 Demod.thisBit = v;
640 Demod.posCount = 1;
641 } else { // second half of bit
642 Demod.thisBit += v;
643
644 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
645 if(Demod.thisBit > 0) {
646 Demod.metric += Demod.thisBit;
647 } else {
648 Demod.metric -= Demod.thisBit;
649 }
650 (Demod.metricN)++;
651 */
652
653 Demod.shiftReg >>= 1;
654 if(Demod.thisBit > 0) { // logic '1'
655 Demod.shiftReg |= 0x200;
656 }
657
658 Demod.bitCount++;
659 if(Demod.bitCount == 10) {
660 uint16_t s = Demod.shiftReg;
661 if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
662 uint8_t b = (s >> 1);
663 Demod.output[Demod.len] = b;
664 Demod.len++;
665 Demod.state = DEMOD_AWAITING_START_BIT;
666 } else {
667 Demod.state = DEMOD_UNSYNCD;
668 LED_C_OFF();
669 if(s == 0x000) {
670 // This is EOF (start, stop and all data bits == '0'
671 return TRUE;
672 }
673 }
674 }
675 Demod.posCount = 0;
676 }
677 break;
678
679 default:
680 Demod.state = DEMOD_UNSYNCD;
681 LED_C_OFF();
682 break;
683 }
684
685 return FALSE;
686 }
687
688
689 static void DemodReset()
690 {
691 // Clear out the state of the "UART" that receives from the tag.
692 Demod.len = 0;
693 Demod.state = DEMOD_UNSYNCD;
694 Demod.posCount = 0;
695 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
696 }
697
698
699 static void DemodInit(uint8_t *data)
700 {
701 Demod.output = data;
702 DemodReset();
703 }
704
705
706 /*
707 * Demodulate the samples we received from the tag, also log to tracebuffer
708 * quiet: set to 'TRUE' to disable debug output
709 */
710 static void GetSamplesFor14443bDemod(int n, bool quiet)
711 {
712 int max = 0;
713 bool gotFrame = FALSE;
714 int lastRxCounter, ci, cq, samples = 0;
715
716 // Allocate memory from BigBuf for some buffers
717 // free all previous allocations first
718 BigBuf_free();
719
720 // The response (tag -> reader) that we're receiving.
721 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
722
723 // The DMA buffer, used to stream samples from the FPGA
724 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
725
726 // Set up the demodulator for tag -> reader responses.
727 DemodInit(receivedResponse);
728
729 // Setup and start DMA.
730 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
731
732 int8_t *upTo = dmaBuf;
733 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
734
735 // Signal field is ON with the appropriate LED:
736 LED_D_ON();
737 // And put the FPGA in the appropriate mode
738 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
739
740 for(;;) {
741 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
742 if(behindBy > max) max = behindBy;
743
744 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1)) > 2) {
745 ci = upTo[0];
746 cq = upTo[1];
747 upTo += 2;
748 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
749 upTo = dmaBuf;
750 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
751 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
752 }
753 lastRxCounter -= 2;
754 if(lastRxCounter <= 0) {
755 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
756 }
757
758 samples += 2;
759
760 if(Handle14443bSamplesDemod(ci, cq)) {
761 gotFrame = TRUE;
762 break;
763 }
764 }
765
766 if(samples > n || gotFrame) {
767 break;
768 }
769 }
770
771 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
772
773 if (!quiet) Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", max, samples, gotFrame, Demod.len, Demod.sumI, Demod.sumQ);
774 //Tracing
775 if (tracing && Demod.len > 0) {
776 uint8_t parity[MAX_PARITY_SIZE];
777 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
778 }
779 }
780
781
782 //-----------------------------------------------------------------------------
783 // Transmit the command (to the tag) that was placed in ToSend[].
784 //-----------------------------------------------------------------------------
785 static void TransmitFor14443b(void)
786 {
787 int c;
788
789 FpgaSetupSsc();
790
791 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
792 AT91C_BASE_SSC->SSC_THR = 0xff;
793 }
794
795 // Signal field is ON with the appropriate Red LED
796 LED_D_ON();
797 // Signal we are transmitting with the Green LED
798 LED_B_ON();
799 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
800
801 for(c = 0; c < 10;) {
802 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
803 AT91C_BASE_SSC->SSC_THR = 0xff;
804 c++;
805 }
806 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
807 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
808 (void)r;
809 }
810 WDT_HIT();
811 }
812
813 c = 0;
814 for(;;) {
815 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
816 AT91C_BASE_SSC->SSC_THR = ToSend[c];
817 c++;
818 if(c >= ToSendMax) {
819 break;
820 }
821 }
822 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
823 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
824 (void)r;
825 }
826 WDT_HIT();
827 }
828 LED_B_OFF(); // Finished sending
829 }
830
831
832 //-----------------------------------------------------------------------------
833 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
834 // so that it is ready to transmit to the tag using TransmitFor14443b().
835 //-----------------------------------------------------------------------------
836 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
837 {
838 int i, j;
839 uint8_t b;
840
841 ToSendReset();
842
843 // Establish initial reference level
844 for(i = 0; i < 40; i++) {
845 ToSendStuffBit(1);
846 }
847 // Send SOF
848 for(i = 0; i < 10; i++) {
849 ToSendStuffBit(0);
850 }
851
852 for(i = 0; i < len; i++) {
853 // Stop bits/EGT
854 ToSendStuffBit(1);
855 ToSendStuffBit(1);
856 // Start bit
857 ToSendStuffBit(0);
858 // Data bits
859 b = cmd[i];
860 for(j = 0; j < 8; j++) {
861 if(b & 1) {
862 ToSendStuffBit(1);
863 } else {
864 ToSendStuffBit(0);
865 }
866 b >>= 1;
867 }
868 }
869 // Send EOF
870 ToSendStuffBit(1);
871 for(i = 0; i < 10; i++) {
872 ToSendStuffBit(0);
873 }
874 for(i = 0; i < 8; i++) {
875 ToSendStuffBit(1);
876 }
877
878 // And then a little more, to make sure that the last character makes
879 // it out before we switch to rx mode.
880 for(i = 0; i < 24; i++) {
881 ToSendStuffBit(1);
882 }
883
884 // Convert from last character reference to length
885 ToSendMax++;
886 }
887
888
889 /**
890 Convenience function to encode, transmit and trace iso 14443b comms
891 **/
892 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
893 {
894 CodeIso14443bAsReader(cmd, len);
895 TransmitFor14443b();
896 if (tracing) {
897 uint8_t parity[MAX_PARITY_SIZE];
898 LogTrace(cmd,len, 0, 0, parity, TRUE);
899 }
900 }
901
902 /* Sends an APDU to the tag
903 * TODO: check CRC and preamble
904 */
905 int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
906 {
907 uint8_t message_frame[message_length + 4];
908 // PCB
909 message_frame[0] = 0x0A | pcb_blocknum;
910 pcb_blocknum ^= 1;
911 // CID
912 message_frame[1] = 0;
913 // INF
914 memcpy(message_frame + 2, message, message_length);
915 // EDC (CRC)
916 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
917 // send
918 CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
919 // get response
920 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT*100, TRUE);
921 if(Demod.len < 3)
922 {
923 return 0;
924 }
925 // TODO: Check CRC
926 // copy response contents
927 if(response != NULL)
928 {
929 memcpy(response, Demod.output, Demod.len);
930 }
931 return Demod.len;
932 }
933
934 /* Perform the ISO 14443 B Card Selection procedure
935 * Currently does NOT do any collision handling.
936 * It expects 0-1 cards in the device's range.
937 * TODO: Support multiple cards (perform anticollision)
938 * TODO: Verify CRC checksums
939 */
940 int iso14443b_select_card()
941 {
942 // WUPB command (including CRC)
943 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
944 static const uint8_t wupb[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
945 // ATTRIB command (with space for CRC)
946 uint8_t attrib[] = { 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
947
948 // first, wake up the tag
949 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
950 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
951 // ATQB too short?
952 if (Demod.len < 14)
953 {
954 return 2;
955 }
956
957 // select the tag
958 // copy the PUPI to ATTRIB
959 memcpy(attrib + 1, Demod.output + 1, 4);
960 /* copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into
961 ATTRIB (Param 3) */
962 attrib[7] = Demod.output[10] & 0x0F;
963 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
964 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
965 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
966 // Answer to ATTRIB too short?
967 if(Demod.len < 3)
968 {
969 return 2;
970 }
971 // reset PCB block number
972 pcb_blocknum = 0;
973 return 1;
974 }
975
976 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
977 void iso14443b_setup() {
978 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
979 // Set up the synchronous serial port
980 FpgaSetupSsc();
981 // connect Demodulated Signal to ADC:
982 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
983
984 // Signal field is on with the appropriate LED
985 LED_D_ON();
986 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
987
988 // Start the timer
989 StartCountSspClk();
990
991 DemodReset();
992 UartReset();
993 }
994
995 //-----------------------------------------------------------------------------
996 // Read a SRI512 ISO 14443B tag.
997 //
998 // SRI512 tags are just simple memory tags, here we're looking at making a dump
999 // of the contents of the memory. No anticollision algorithm is done, we assume
1000 // we have a single tag in the field.
1001 //
1002 // I tried to be systematic and check every answer of the tag, every CRC, etc...
1003 //-----------------------------------------------------------------------------
1004 void ReadSTMemoryIso14443b(uint32_t dwLast)
1005 {
1006 uint8_t i = 0x00;
1007
1008 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1009 // Make sure that we start from off, since the tags are stateful;
1010 // confusing things will happen if we don't reset them between reads.
1011 LED_D_OFF();
1012 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1013 SpinDelay(200);
1014
1015 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1016 FpgaSetupSsc();
1017
1018 // Now give it time to spin up.
1019 // Signal field is on with the appropriate LED
1020 LED_D_ON();
1021 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
1022 SpinDelay(200);
1023
1024 clear_trace();
1025 set_tracing(TRUE);
1026
1027 // First command: wake up the tag using the INITIATE command
1028 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
1029 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1030 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1031
1032 if (Demod.len == 0) {
1033 DbpString("No response from tag");
1034 return;
1035 } else {
1036 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
1037 Demod.output[0], Demod.output[1], Demod.output[2]);
1038 }
1039
1040 // There is a response, SELECT the uid
1041 DbpString("Now SELECT tag:");
1042 cmd1[0] = 0x0E; // 0x0E is SELECT
1043 cmd1[1] = Demod.output[0];
1044 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1045 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1046 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1047 if (Demod.len != 3) {
1048 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1049 return;
1050 }
1051 // Check the CRC of the answer:
1052 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1053 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1054 DbpString("CRC Error reading select response.");
1055 return;
1056 }
1057 // Check response from the tag: should be the same UID as the command we just sent:
1058 if (cmd1[1] != Demod.output[0]) {
1059 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1060 return;
1061 }
1062
1063 // Tag is now selected,
1064 // First get the tag's UID:
1065 cmd1[0] = 0x0B;
1066 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1067 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
1068 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1069 if (Demod.len != 10) {
1070 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1071 return;
1072 }
1073 // The check the CRC of the answer (use cmd1 as temporary variable):
1074 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1075 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1076 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1077 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1078 // Do not return;, let's go on... (we should retry, maybe ?)
1079 }
1080 Dbprintf("Tag UID (64 bits): %08x %08x",
1081 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1082 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1083
1084 // Now loop to read all 16 blocks, address from 0 to last block
1085 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
1086 cmd1[0] = 0x08;
1087 i = 0x00;
1088 dwLast++;
1089 for (;;) {
1090 if (i == dwLast) {
1091 DbpString("System area block (0xff):");
1092 i = 0xff;
1093 }
1094 cmd1[1] = i;
1095 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1096 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1097 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1098 if (Demod.len != 6) { // Check if we got an answer from the tag
1099 DbpString("Expected 6 bytes from tag, got less...");
1100 return;
1101 }
1102 // The check the CRC of the answer (use cmd1 as temporary variable):
1103 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1104 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1105 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1106 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1107 // Do not return;, let's go on... (we should retry, maybe ?)
1108 }
1109 // Now print out the memory location:
1110 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1111 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1112 (Demod.output[4]<<8)+Demod.output[5]);
1113 if (i == 0xff) {
1114 break;
1115 }
1116 i++;
1117 }
1118 }
1119
1120
1121 //=============================================================================
1122 // Finally, the `sniffer' combines elements from both the reader and
1123 // simulated tag, to show both sides of the conversation.
1124 //=============================================================================
1125
1126 //-----------------------------------------------------------------------------
1127 // Record the sequence of commands sent by the reader to the tag, with
1128 // triggering so that we start recording at the point that the tag is moved
1129 // near the reader.
1130 //-----------------------------------------------------------------------------
1131 /*
1132 * Memory usage for this function, (within BigBuf)
1133 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1134 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1135 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1136 * Demodulated samples received - all the rest
1137 */
1138 void RAMFUNC SnoopIso14443b(void)
1139 {
1140 // We won't start recording the frames that we acquire until we trigger;
1141 // a good trigger condition to get started is probably when we see a
1142 // response from the tag.
1143 int triggered = TRUE; // TODO: set and evaluate trigger condition
1144
1145 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1146 BigBuf_free();
1147
1148 clear_trace();
1149 set_tracing(TRUE);
1150
1151 // The DMA buffer, used to stream samples from the FPGA
1152 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
1153 int lastRxCounter;
1154 int8_t *upTo;
1155 int ci, cq;
1156 int maxBehindBy = 0;
1157
1158 // Count of samples received so far, so that we can include timing
1159 // information in the trace buffer.
1160 int samples = 0;
1161
1162 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1163 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1164
1165 // Print some debug information about the buffer sizes
1166 Dbprintf("Snooping buffers initialized:");
1167 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1168 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1169 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1170 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1171
1172 // Signal field is off, no reader signal, no tag signal
1173 LEDsoff();
1174
1175 // And put the FPGA in the appropriate mode
1176 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1177 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1178
1179 // Setup for the DMA.
1180 FpgaSetupSsc();
1181 upTo = dmaBuf;
1182 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1183 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
1184 uint8_t parity[MAX_PARITY_SIZE];
1185
1186 bool TagIsActive = FALSE;
1187 bool ReaderIsActive = FALSE;
1188
1189 // And now we loop, receiving samples.
1190 for(;;) {
1191 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
1192 (ISO14443B_DMA_BUFFER_SIZE-1);
1193 if(behindBy > maxBehindBy) {
1194 maxBehindBy = behindBy;
1195 }
1196
1197 if(behindBy < 2) continue;
1198
1199 ci = upTo[0];
1200 cq = upTo[1];
1201 upTo += 2;
1202 lastRxCounter -= 2;
1203 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
1204 upTo = dmaBuf;
1205 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
1206 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
1207 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
1208 WDT_HIT();
1209 if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) { // TODO: understand whether we can increase/decrease as we want or not?
1210 Dbprintf("blew circular buffer! behindBy=%d", behindBy);
1211 break;
1212 }
1213 if(!tracing) {
1214 DbpString("Reached trace limit");
1215 break;
1216 }
1217 if(BUTTON_PRESS()) {
1218 DbpString("cancelled");
1219 break;
1220 }
1221 }
1222
1223 samples += 2;
1224
1225 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
1226 if(Handle14443bUartBit(ci & 0x01)) {
1227 if(triggered && tracing) {
1228 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1229 }
1230 /* And ready to receive another command. */
1231 UartReset();
1232 /* And also reset the demod code, which might have been */
1233 /* false-triggered by the commands from the reader. */
1234 DemodReset();
1235 }
1236 if(Handle14443bUartBit(cq & 0x01)) {
1237 if(triggered && tracing) {
1238 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1239 }
1240 /* And ready to receive another command. */
1241 UartReset();
1242 /* And also reset the demod code, which might have been */
1243 /* false-triggered by the commands from the reader. */
1244 DemodReset();
1245 }
1246 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1247 }
1248
1249 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
1250 if(Handle14443bSamplesDemod(ci | 0x01, cq | 0x01)) {
1251
1252 //Use samples as a time measurement
1253 if(tracing)
1254 {
1255 uint8_t parity[MAX_PARITY_SIZE];
1256 LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
1257 }
1258 triggered = TRUE;
1259
1260 // And ready to receive another response.
1261 DemodReset();
1262 }
1263 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1264 }
1265
1266 }
1267
1268 FpgaDisableSscDma();
1269 LEDsoff();
1270 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
1271 DbpString("Snoop statistics:");
1272 Dbprintf(" Max behind by: %i", maxBehindBy);
1273 Dbprintf(" Uart State: %x", Uart.state);
1274 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1275 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
1276 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1277 }
1278
1279
1280 /*
1281 * Send raw command to tag ISO14443B
1282 * @Input
1283 * datalen len of buffer data
1284 * recv bool when true wait for data from tag and send to client
1285 * powerfield bool leave the field on when true
1286 * data buffer with byte to send
1287 *
1288 * @Output
1289 * none
1290 *
1291 */
1292 void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
1293 {
1294 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1295 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1296 FpgaSetupSsc();
1297
1298 set_tracing(TRUE);
1299
1300 CodeAndTransmit14443bAsReader(data, datalen);
1301
1302 if(recv) {
1303 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1304 uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1305 cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
1306 }
1307
1308 if(!powerfield) {
1309 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1310 LED_D_OFF();
1311 }
1312 }
1313
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