]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
Updated the windows Makefile to be compatible with both nmake and make
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // Miscellaneous routines for low frequency tag operations.
3 // Tags supported here so far are Texas Instruments (TI), HID
4 // Also routines for raw mode reading/simulating of LF waveform
5 //
6 //-----------------------------------------------------------------------------
7 #include <proxmark3.h>
8 #include "apps.h"
9 #include "hitag2.h"
10 #include "../common/crc16.c"
11
12 void AcquireRawAdcSamples125k(BOOL at134khz)
13 {
14 if(at134khz) {
15 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
16 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
17 } else {
18 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
19 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
20 }
21
22 // Connect the A/D to the peak-detected low-frequency path.
23 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
24
25 // Give it a bit of time for the resonant antenna to settle.
26 SpinDelay(50);
27
28 // Now set up the SSC to get the ADC samples that are now streaming at us.
29 FpgaSetupSsc();
30
31 // Now call the acquisition routine
32 DoAcquisition125k(at134khz);
33 }
34
35 // split into two routines so we can avoid timing issues after sending commands //
36 void DoAcquisition125k(BOOL at134khz)
37 {
38 BYTE *dest = (BYTE *)BigBuf;
39 int n = sizeof(BigBuf);
40 int i;
41
42 memset(dest,0,n);
43 i = 0;
44 for(;;) {
45 if(SSC_STATUS & (SSC_STATUS_TX_READY)) {
46 SSC_TRANSMIT_HOLDING = 0x43;
47 LED_D_ON();
48 }
49 if(SSC_STATUS & (SSC_STATUS_RX_READY)) {
50 dest[i] = (BYTE)SSC_RECEIVE_HOLDING;
51 i++;
52 LED_D_OFF();
53 if(i >= n) {
54 break;
55 }
56 }
57 }
58 DbpIntegers(dest[0], dest[1], at134khz);
59 }
60
61 void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYTE *command)
62 {
63 BOOL at134khz;
64
65 /* Make sure the tag is reset */
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
67 SpinDelay(2500);
68
69 // see if 'h' was specified
70 if(command[strlen((char *) command) - 1] == 'h')
71 at134khz= TRUE;
72 else
73 at134khz= FALSE;
74
75 if(at134khz) {
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
78 } else {
79 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
80 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
81 }
82
83 // Give it a bit of time for the resonant antenna to settle.
84 SpinDelay(50);
85 // And a little more time for the tag to fully power up
86 SpinDelay(2000);
87
88 // Now set up the SSC to get the ADC samples that are now streaming at us.
89 FpgaSetupSsc();
90
91 // now modulate the reader field
92 while(*command != '\0' && *command != ' ')
93 {
94 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
95 LED_D_OFF();
96 SpinDelayUs(delay_off);
97 if(at134khz) {
98 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
99 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
100 } else {
101 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
102 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
103 }
104 LED_D_ON();
105 if(*(command++) == '0') {
106 SpinDelayUs(period_0);
107 } else {
108 SpinDelayUs(period_1);
109 }
110 }
111 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
112 LED_D_OFF();
113 SpinDelayUs(delay_off);
114 if(at134khz) {
115 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
117 } else {
118 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
120 }
121
122 // now do the read
123 DoAcquisition125k(at134khz);
124 }
125
126 /* blank r/w tag data stream
127 ...0000000000000000 01111111
128 1010101010101010101010101010101010101010101010101010101010101010
129 0011010010100001
130 01111111
131 101010101010101[0]000...
132
133 [5555fe852c5555555555555555fe0000]
134 */
135 void ReadTItag()
136 {
137 // some hardcoded initial params
138 // when we read a TI tag we sample the zerocross line at 2Mhz
139 // TI tags modulate a 1 as 16 cycles of 123.2Khz
140 // TI tags modulate a 0 as 16 cycles of 134.2Khz
141 #define FSAMPLE 2000000
142 #define FREQLO 123200
143 #define FREQHI 134200
144
145 signed char *dest = (signed char *)BigBuf;
146 int n = sizeof(BigBuf);
147 // int *dest = GraphBuffer;
148 // int n = GraphTraceLen;
149
150 // 128 bit shift register [shift3:shift2:shift1:shift0]
151 DWORD shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
152
153 int i, cycles=0, samples=0;
154 // how many sample points fit in 16 cycles of each frequency
155 DWORD sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
156 // when to tell if we're close enough to one freq or another
157 DWORD threshold = (sampleslo - sampleshi + 1)>>1;
158
159 // TI tags charge at 134.2Khz
160 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
161
162 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
163 // connects to SSP_DIN and the SSP_DOUT logic level controls
164 // whether we're modulating the antenna (high)
165 // or listening to the antenna (low)
166 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
167
168 // get TI tag data into the buffer
169 AcquireTiType();
170
171 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
172
173 for (i=0; i<n-1; i++) {
174 // count cycles by looking for lo to hi zero crossings
175 if ( (dest[i]<0) && (dest[i+1]>0) ) {
176 cycles++;
177 // after 16 cycles, measure the frequency
178 if (cycles>15) {
179 cycles=0;
180 samples=i-samples; // number of samples in these 16 cycles
181
182 // TI bits are coming to us lsb first so shift them
183 // right through our 128 bit right shift register
184 shift0 = (shift0>>1) | (shift1 << 31);
185 shift1 = (shift1>>1) | (shift2 << 31);
186 shift2 = (shift2>>1) | (shift3 << 31);
187 shift3 >>= 1;
188
189 // check if the cycles fall close to the number
190 // expected for either the low or high frequency
191 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
192 // low frequency represents a 1
193 shift3 |= (1<<31);
194 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
195 // high frequency represents a 0
196 } else {
197 // probably detected a gay waveform or noise
198 // use this as gaydar or discard shift register and start again
199 shift3 = shift2 = shift1 = shift0 = 0;
200 }
201 samples = i;
202
203 // for each bit we receive, test if we've detected a valid tag
204
205 // if we see 17 zeroes followed by 6 ones, we might have a tag
206 // remember the bits are backwards
207 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
208 // if start and end bytes match, we have a tag so break out of the loop
209 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
210 cycles = 0xF0B; //use this as a flag (ugly but whatever)
211 break;
212 }
213 }
214 }
215 }
216 }
217
218 // if flag is set we have a tag
219 if (cycles!=0xF0B) {
220 DbpString("Info: No valid tag detected.");
221 } else {
222 // put 64 bit data into shift1 and shift0
223 shift0 = (shift0>>24) | (shift1 << 8);
224 shift1 = (shift1>>24) | (shift2 << 8);
225
226 // align 16 bit crc into lower half of shift2
227 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
228
229 // if r/w tag, check ident match
230 if ( shift3&(1<<15) ) {
231 DbpString("Info: TI tag is rewriteable");
232 // only 15 bits compare, last bit of ident is not valid
233 if ( ((shift3>>16)^shift0)&0x7fff ) {
234 DbpString("Error: Ident mismatch!");
235 } else {
236 DbpString("Info: TI tag ident is valid");
237 }
238 } else {
239 DbpString("Info: TI tag is readonly");
240 }
241
242 // WARNING the order of the bytes in which we calc crc below needs checking
243 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
244 // bytes in reverse or something
245 // calculate CRC
246 DWORD crc=0;
247
248 crc = update_crc16(crc, (shift0)&0xff);
249 crc = update_crc16(crc, (shift0>>8)&0xff);
250 crc = update_crc16(crc, (shift0>>16)&0xff);
251 crc = update_crc16(crc, (shift0>>24)&0xff);
252 crc = update_crc16(crc, (shift1)&0xff);
253 crc = update_crc16(crc, (shift1>>8)&0xff);
254 crc = update_crc16(crc, (shift1>>16)&0xff);
255 crc = update_crc16(crc, (shift1>>24)&0xff);
256
257 DbpString("Info: Tag data_hi, data_lo, crc = ");
258 DbpIntegers(shift1, shift0, shift2&0xffff);
259 if (crc != (shift2&0xffff)) {
260 DbpString("Error: CRC mismatch, expected");
261 DbpIntegers(0, 0, crc);
262 } else {
263 DbpString("Info: CRC is good");
264 }
265 }
266 }
267
268 void WriteTIbyte(BYTE b)
269 {
270 int i = 0;
271
272 // modulate 8 bits out to the antenna
273 for (i=0; i<8; i++)
274 {
275 if (b&(1<<i)) {
276 // stop modulating antenna
277 PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);
278 SpinDelayUs(1000);
279 // modulate antenna
280 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
281 SpinDelayUs(1000);
282 } else {
283 // stop modulating antenna
284 PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);
285 SpinDelayUs(300);
286 // modulate antenna
287 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
288 SpinDelayUs(1700);
289 }
290 }
291 }
292
293 void AcquireTiType(void)
294 {
295 int i, j, n;
296 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
297 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS
298 #define TIBUFLEN 1250
299
300 // clear buffer
301 memset(BigBuf,0,sizeof(BigBuf));
302
303 // Set up the synchronous serial port
304 PIO_DISABLE = (1<<GPIO_SSC_DIN);
305 PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN);
306
307 // steal this pin from the SSP and use it to control the modulation
308 PIO_ENABLE = (1<<GPIO_SSC_DOUT);
309 PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);
310
311 SSC_CONTROL = SSC_CONTROL_RESET;
312 SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;
313
314 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
315 // 48/2 = 24 MHz clock must be divided by 12
316 SSC_CLOCK_DIVISOR = 12;
317
318 SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(0);
319 SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;
320 SSC_TRANSMIT_CLOCK_MODE = 0;
321 SSC_TRANSMIT_FRAME_MODE = 0;
322
323 LED_D_ON();
324
325 // modulate antenna
326 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
327
328 // Charge TI tag for 50ms.
329 SpinDelay(50);
330
331 // stop modulating antenna and listen
332 PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);
333
334 LED_D_OFF();
335
336 i = 0;
337 for(;;) {
338 if(SSC_STATUS & SSC_STATUS_RX_READY) {
339 BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer
340 i++; if(i >= TIBUFLEN) break;
341 }
342 WDT_HIT();
343 }
344
345 // return stolen pin to SSP
346 PIO_DISABLE = (1<<GPIO_SSC_DOUT);
347 PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN) | (1<<GPIO_SSC_DOUT);
348
349 char *dest = (char *)BigBuf;
350 n = TIBUFLEN*32;
351 // unpack buffer
352 for (i=TIBUFLEN-1; i>=0; i--) {
353 // DbpIntegers(0, 0, BigBuf[i]);
354 for (j=0; j<32; j++) {
355 if(BigBuf[i] & (1 << j)) {
356 dest[--n] = 1;
357 } else {
358 dest[--n] = -1;
359 }
360 }
361 }
362 }
363
364 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
365 // if crc provided, it will be written with the data verbatim (even if bogus)
366 // if not provided a valid crc will be computed from the data and written.
367 void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)
368 {
369
370 // WARNING the order of the bytes in which we calc crc below needs checking
371 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
372 // bytes in reverse or something
373
374 if(crc == 0) {
375 crc = update_crc16(crc, (idlo)&0xff);
376 crc = update_crc16(crc, (idlo>>8)&0xff);
377 crc = update_crc16(crc, (idlo>>16)&0xff);
378 crc = update_crc16(crc, (idlo>>24)&0xff);
379 crc = update_crc16(crc, (idhi)&0xff);
380 crc = update_crc16(crc, (idhi>>8)&0xff);
381 crc = update_crc16(crc, (idhi>>16)&0xff);
382 crc = update_crc16(crc, (idhi>>24)&0xff);
383 }
384 DbpString("Writing the following data to tag:");
385 DbpIntegers(idhi, idlo, crc);
386
387 // TI tags charge at 134.2Khz
388 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
389 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
390 // connects to SSP_DIN and the SSP_DOUT logic level controls
391 // whether we're modulating the antenna (high)
392 // or listening to the antenna (low)
393 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
394 LED_A_ON();
395
396 // steal this pin from the SSP and use it to control the modulation
397 PIO_ENABLE = (1<<GPIO_SSC_DOUT);
398 PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);
399
400 // writing algorithm:
401 // a high bit consists of a field off for 1ms and field on for 1ms
402 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
403 // initiate a charge time of 50ms (field on) then immediately start writing bits
404 // start by writing 0xBB (keyword) and 0xEB (password)
405 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
406 // finally end with 0x0300 (write frame)
407 // all data is sent lsb firts
408 // finish with 15ms programming time
409
410 // modulate antenna
411 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
412 SpinDelay(50); // charge time
413
414 WriteTIbyte(0xbb); // keyword
415 WriteTIbyte(0xeb); // password
416 WriteTIbyte( (idlo )&0xff );
417 WriteTIbyte( (idlo>>8 )&0xff );
418 WriteTIbyte( (idlo>>16)&0xff );
419 WriteTIbyte( (idlo>>24)&0xff );
420 WriteTIbyte( (idhi )&0xff );
421 WriteTIbyte( (idhi>>8 )&0xff );
422 WriteTIbyte( (idhi>>16)&0xff );
423 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
424 WriteTIbyte( (crc )&0xff ); // crc lo
425 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
426 WriteTIbyte(0x00); // write frame lo
427 WriteTIbyte(0x03); // write frame hi
428 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
429 SpinDelay(50); // programming time
430
431 LED_A_OFF();
432
433 // get TI tag data into the buffer
434 AcquireTiType();
435
436 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
437 DbpString("Now use tiread to check");
438 }
439
440 void SimulateTagLowFrequency(int period, int ledcontrol)
441 {
442 int i;
443 BYTE *tab = (BYTE *)BigBuf;
444
445 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);
446
447 PIO_ENABLE = (1 << GPIO_SSC_DOUT) | (1 << GPIO_SSC_CLK);
448
449 PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);
450 PIO_OUTPUT_DISABLE = (1 << GPIO_SSC_CLK);
451
452 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
453 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
454
455 i = 0;
456 for(;;) {
457 while(!(PIO_PIN_DATA_STATUS & (1<<GPIO_SSC_CLK))) {
458 if(BUTTON_PRESS()) {
459 DbpString("Stopped");
460 return;
461 }
462 WDT_HIT();
463 }
464
465 if (ledcontrol)
466 LED_D_ON();
467
468 if(tab[i])
469 OPEN_COIL();
470 else
471 SHORT_COIL();
472
473 if (ledcontrol)
474 LED_D_OFF();
475
476 while(PIO_PIN_DATA_STATUS & (1<<GPIO_SSC_CLK)) {
477 if(BUTTON_PRESS()) {
478 DbpString("Stopped");
479 return;
480 }
481 WDT_HIT();
482 }
483
484 i++;
485 if(i == period) i = 0;
486 }
487 }
488
489 /* Provides a framework for bidirectional LF tag communication
490 * Encoding is currently Hitag2, but the general idea can probably
491 * be transferred to other encodings.
492 *
493 * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME
494 * (PA15) a thresholded version of the signal from the ADC. Setting the
495 * ADC path to the low frequency peak detection signal, will enable a
496 * somewhat reasonable receiver for modulation on the carrier signal
497 * that is generated by the reader. The signal is low when the reader
498 * field is switched off, and high when the reader field is active. Due
499 * to the way that the signal looks like, mostly only the rising edge is
500 * useful, your mileage may vary.
501 *
502 * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also
503 * TIOA1, which can be used as the capture input for timer 1. This should
504 * make it possible to measure the exact edge-to-edge time, without processor
505 * intervention.
506 *
507 * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)
508 * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)
509 *
510 * The following defines are in carrier periods:
511 */
512 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
513 #define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */
514 #define HITAG_T_EOF 40 /* T_EOF should be > 36 */
515 #define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */
516
517 static void hitag_handle_frame(int t0, int frame_len, char *frame);
518 //#define DEBUG_RA_VALUES 1
519 #define DEBUG_FRAME_CONTENTS 1
520 void SimulateTagLowFrequencyBidir(int divisor, int t0)
521 {
522 #if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS
523 int i = 0;
524 #endif
525 char frame[10];
526 int frame_pos=0;
527
528 DbpString("Starting Hitag2 emulator, press button to end");
529 hitag2_init();
530
531 /* Set up simulator mode, frequency divisor which will drive the FPGA
532 * and analog mux selection.
533 */
534 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);
535 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
536 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
537 RELAY_OFF();
538
539 /* Set up Timer 1:
540 * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
541 * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising
542 * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)
543 */
544
545 PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_TC1);
546 PIO_PERIPHERAL_B_SEL = (1 << GPIO_SSC_FRAME);
547 TC1_CCR = TC_CCR_CLKDIS;
548 TC1_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_ETRGEDG_RISING | TC_CMR_ABETRG |
549 TC_CMR_LDRA_RISING | TC_CMR_LDRB_RISING;
550 TC1_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;
551
552 /* calculate the new value for the carrier period in terms of TC1 values */
553 t0 = t0/2;
554
555 int overflow = 0;
556 while(!BUTTON_PRESS()) {
557 WDT_HIT();
558 if(TC1_SR & TC_SR_LDRAS) {
559 int ra = TC1_RA;
560 if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;
561 #if DEBUG_RA_VALUES
562 if(ra > 255 || overflow) ra = 255;
563 ((char*)BigBuf)[i] = ra;
564 i = (i+1) % 8000;
565 #endif
566
567 if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {
568 /* Ignore */
569 } else if(ra >= t0*HITAG_T_1_MIN ) {
570 /* '1' bit */
571 if(frame_pos < 8*sizeof(frame)) {
572 frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );
573 frame_pos++;
574 }
575 } else if(ra >= t0*HITAG_T_0_MIN) {
576 /* '0' bit */
577 if(frame_pos < 8*sizeof(frame)) {
578 frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );
579 frame_pos++;
580 }
581 }
582
583 overflow = 0;
584 LED_D_ON();
585 } else {
586 if(TC1_CV > t0*HITAG_T_EOF) {
587 /* Minor nuisance: In Capture mode, the timer can not be
588 * stopped by a Compare C. There's no way to stop the clock
589 * in software, so we'll just have to note the fact that an
590 * overflow happened and the next loaded timer value might
591 * have wrapped. Also, this marks the end of frame, and the
592 * still running counter can be used to determine the correct
593 * time for the start of the reply.
594 */
595 overflow = 1;
596
597 if(frame_pos > 0) {
598 /* Have a frame, do something with it */
599 #if DEBUG_FRAME_CONTENTS
600 ((char*)BigBuf)[i++] = frame_pos;
601 memcpy( ((char*)BigBuf)+i, frame, 7);
602 i+=7;
603 i = i % sizeof(BigBuf);
604 #endif
605 hitag_handle_frame(t0, frame_pos, frame);
606 memset(frame, 0, sizeof(frame));
607 }
608 frame_pos = 0;
609
610 }
611 LED_D_OFF();
612 }
613 }
614 DbpString("All done");
615 }
616
617 static void hitag_send_bit(int t0, int bit) {
618 if(bit == 1) {
619 /* Manchester: Loaded, then unloaded */
620 LED_A_ON();
621 SHORT_COIL();
622 while(TC1_CV < t0*15);
623 OPEN_COIL();
624 while(TC1_CV < t0*31);
625 LED_A_OFF();
626 } else if(bit == 0) {
627 /* Manchester: Unloaded, then loaded */
628 LED_B_ON();
629 OPEN_COIL();
630 while(TC1_CV < t0*15);
631 SHORT_COIL();
632 while(TC1_CV < t0*31);
633 LED_B_OFF();
634 }
635 TC1_CCR = TC_CCR_SWTRG; /* Reset clock for the next bit */
636
637 }
638 static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)
639 {
640 OPEN_COIL();
641 PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);
642
643 /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,
644 * not that since the clock counts since the rising edge, but T_wresp is
645 * with respect to the falling edge, we need to wait actually (T_wresp - T_g)
646 * periods. The gap time T_g varies (4..10).
647 */
648 while(TC1_CV < t0*(fdt-8));
649
650 int saved_cmr = TC1_CMR;
651 TC1_CMR &= ~TC_CMR_ETRGEDG; /* Disable external trigger for the clock */
652 TC1_CCR = TC_CCR_SWTRG; /* Reset the clock and use it for response timing */
653
654 int i;
655 for(i=0; i<5; i++)
656 hitag_send_bit(t0, 1); /* Start of frame */
657
658 for(i=0; i<frame_len; i++) {
659 hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );
660 }
661
662 OPEN_COIL();
663 TC1_CMR = saved_cmr;
664 }
665
666 /* Callback structure to cleanly separate tag emulation code from the radio layer. */
667 static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)
668 {
669 hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);
670 return 0;
671 }
672 /* Frame length in bits, frame contents in MSBit first format */
673 static void hitag_handle_frame(int t0, int frame_len, char *frame)
674 {
675 hitag2_handle_command(frame, frame_len, hitag_cb, &t0);
676 }
677
678 // compose fc/8 fc/10 waveform
679 static void fc(int c, int *n) {
680 BYTE *dest = (BYTE *)BigBuf;
681 int idx;
682
683 // for when we want an fc8 pattern every 4 logical bits
684 if(c==0) {
685 dest[((*n)++)]=1;
686 dest[((*n)++)]=1;
687 dest[((*n)++)]=0;
688 dest[((*n)++)]=0;
689 dest[((*n)++)]=0;
690 dest[((*n)++)]=0;
691 dest[((*n)++)]=0;
692 dest[((*n)++)]=0;
693 }
694 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
695 if(c==8) {
696 for (idx=0; idx<6; idx++) {
697 dest[((*n)++)]=1;
698 dest[((*n)++)]=1;
699 dest[((*n)++)]=0;
700 dest[((*n)++)]=0;
701 dest[((*n)++)]=0;
702 dest[((*n)++)]=0;
703 dest[((*n)++)]=0;
704 dest[((*n)++)]=0;
705 }
706 }
707
708 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
709 if(c==10) {
710 for (idx=0; idx<5; idx++) {
711 dest[((*n)++)]=1;
712 dest[((*n)++)]=1;
713 dest[((*n)++)]=1;
714 dest[((*n)++)]=0;
715 dest[((*n)++)]=0;
716 dest[((*n)++)]=0;
717 dest[((*n)++)]=0;
718 dest[((*n)++)]=0;
719 dest[((*n)++)]=0;
720 dest[((*n)++)]=0;
721 }
722 }
723 }
724
725 // prepare a waveform pattern in the buffer based on the ID given then
726 // simulate a HID tag until the button is pressed
727 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
728 {
729 int n=0, i=0;
730 /*
731 HID tag bitstream format
732 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
733 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
734 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
735 A fc8 is inserted before every 4 bits
736 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
737 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
738 */
739
740 if (hi>0xFFF) {
741 DbpString("Tags can only have 44 bits.");
742 return;
743 }
744 fc(0,&n);
745 // special start of frame marker containing invalid bit sequences
746 fc(8, &n); fc(8, &n); // invalid
747 fc(8, &n); fc(10, &n); // logical 0
748 fc(10, &n); fc(10, &n); // invalid
749 fc(8, &n); fc(10, &n); // logical 0
750
751 WDT_HIT();
752 // manchester encode bits 43 to 32
753 for (i=11; i>=0; i--) {
754 if ((i%4)==3) fc(0,&n);
755 if ((hi>>i)&1) {
756 fc(10, &n); fc(8, &n); // low-high transition
757 } else {
758 fc(8, &n); fc(10, &n); // high-low transition
759 }
760 }
761
762 WDT_HIT();
763 // manchester encode bits 31 to 0
764 for (i=31; i>=0; i--) {
765 if ((i%4)==3) fc(0,&n);
766 if ((lo>>i)&1) {
767 fc(10, &n); fc(8, &n); // low-high transition
768 } else {
769 fc(8, &n); fc(10, &n); // high-low transition
770 }
771 }
772
773 if (ledcontrol)
774 LED_A_ON();
775 SimulateTagLowFrequency(n, ledcontrol);
776
777 if (ledcontrol)
778 LED_A_OFF();
779 }
780
781
782 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
783 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
784 {
785 BYTE *dest = (BYTE *)BigBuf;
786 int m=0, n=0, i=0, idx=0, found=0, lastval=0;
787 DWORD hi=0, lo=0;
788
789 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
790 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
791
792 // Connect the A/D to the peak-detected low-frequency path.
793 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
794
795 // Give it a bit of time for the resonant antenna to settle.
796 SpinDelay(50);
797
798 // Now set up the SSC to get the ADC samples that are now streaming at us.
799 FpgaSetupSsc();
800
801 for(;;) {
802 WDT_HIT();
803 if (ledcontrol)
804 LED_A_ON();
805 if(BUTTON_PRESS()) {
806 DbpString("Stopped");
807 if (ledcontrol)
808 LED_A_OFF();
809 return;
810 }
811
812 i = 0;
813 m = sizeof(BigBuf);
814 memset(dest,128,m);
815 for(;;) {
816 if(SSC_STATUS & (SSC_STATUS_TX_READY)) {
817 SSC_TRANSMIT_HOLDING = 0x43;
818 if (ledcontrol)
819 LED_D_ON();
820 }
821 if(SSC_STATUS & (SSC_STATUS_RX_READY)) {
822 dest[i] = (BYTE)SSC_RECEIVE_HOLDING;
823 // we don't care about actual value, only if it's more or less than a
824 // threshold essentially we capture zero crossings for later analysis
825 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
826 i++;
827 if (ledcontrol)
828 LED_D_OFF();
829 if(i >= m) {
830 break;
831 }
832 }
833 }
834
835 // FSK demodulator
836
837 // sync to first lo-hi transition
838 for( idx=1; idx<m; idx++) {
839 if (dest[idx-1]<dest[idx])
840 lastval=idx;
841 break;
842 }
843 WDT_HIT();
844
845 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
846 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
847 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
848 for( i=0; idx<m; idx++) {
849 if (dest[idx-1]<dest[idx]) {
850 dest[i]=idx-lastval;
851 if (dest[i] <= 8) {
852 dest[i]=1;
853 } else {
854 dest[i]=0;
855 }
856
857 lastval=idx;
858 i++;
859 }
860 }
861 m=i;
862 WDT_HIT();
863
864 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
865 lastval=dest[0];
866 idx=0;
867 i=0;
868 n=0;
869 for( idx=0; idx<m; idx++) {
870 if (dest[idx]==lastval) {
871 n++;
872 } else {
873 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
874 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
875 // swallowed up by rounding
876 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
877 // special start of frame markers use invalid manchester states (no transitions) by using sequences
878 // like 111000
879 if (dest[idx-1]) {
880 n=(n+1)/6; // fc/8 in sets of 6
881 } else {
882 n=(n+1)/5; // fc/10 in sets of 5
883 }
884 switch (n) { // stuff appropriate bits in buffer
885 case 0:
886 case 1: // one bit
887 dest[i++]=dest[idx-1];
888 break;
889 case 2: // two bits
890 dest[i++]=dest[idx-1];
891 dest[i++]=dest[idx-1];
892 break;
893 case 3: // 3 bit start of frame markers
894 dest[i++]=dest[idx-1];
895 dest[i++]=dest[idx-1];
896 dest[i++]=dest[idx-1];
897 break;
898 // When a logic 0 is immediately followed by the start of the next transmisson
899 // (special pattern) a pattern of 4 bit duration lengths is created.
900 case 4:
901 dest[i++]=dest[idx-1];
902 dest[i++]=dest[idx-1];
903 dest[i++]=dest[idx-1];
904 dest[i++]=dest[idx-1];
905 break;
906 default: // this shouldn't happen, don't stuff any bits
907 break;
908 }
909 n=0;
910 lastval=dest[idx];
911 }
912 }
913 m=i;
914 WDT_HIT();
915
916 // final loop, go over previously decoded manchester data and decode into usable tag ID
917 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
918 for( idx=0; idx<m-6; idx++) {
919 // search for a start of frame marker
920 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
921 {
922 found=1;
923 idx+=6;
924 if (found && (hi|lo)) {
925 DbpString("TAG ID");
926 DbpIntegers(hi, lo, (lo>>1)&0xffff);
927 /* if we're only looking for one tag */
928 if (findone)
929 {
930 *high = hi;
931 *low = lo;
932 return;
933 }
934 hi=0;
935 lo=0;
936 found=0;
937 }
938 }
939 if (found) {
940 if (dest[idx] && (!dest[idx+1]) ) {
941 hi=(hi<<1)|(lo>>31);
942 lo=(lo<<1)|0;
943 } else if ( (!dest[idx]) && dest[idx+1]) {
944 hi=(hi<<1)|(lo>>31);
945 lo=(lo<<1)|1;
946 } else {
947 found=0;
948 hi=0;
949 lo=0;
950 }
951 idx++;
952 }
953 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
954 {
955 found=1;
956 idx+=6;
957 if (found && (hi|lo)) {
958 DbpString("TAG ID");
959 DbpIntegers(hi, lo, (lo>>1)&0xffff);
960 /* if we're only looking for one tag */
961 if (findone)
962 {
963 *high = hi;
964 *low = lo;
965 return;
966 }
967 hi=0;
968 lo=0;
969 found=0;
970 }
971 }
972 }
973 WDT_HIT();
974 }
975 }
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