git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c

   1 //-----------------------------------------------------------------------------
   2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
   3 // at your option, any later version. See the LICENSE.txt file for the text of
   4 // the license.
   5 //-----------------------------------------------------------------------------
   6 // Miscellaneous routines for low frequency tag operations.
   7 // Tags supported here so far are Texas Instruments (TI), HID
   8 // Also routines for raw mode reading/simulating of LF waveform
   9 //-----------------------------------------------------------------------------
  10
  11 #include "proxmark3.h"
  12 #include "apps.h"
  13 #include "util.h"
  14 #include "hitag2.h"
  15 #include "crc16.h"
  16 #include "string.h"
  17 #include "lfdemod.h"
  18
  19
  20 /**
  21 * Does the sample acquisition. If threshold is specified, the actual sampling
  22 * is not commenced until the threshold has been reached.
  23 * @param trigger_threshold - the threshold
  24 * @param silent - is true, now outputs are made. If false, dbprints the status
  25 */
  26 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
  27 {
  28     uint8_t *dest = (uint8_t *)BigBuf;
  29     int n = sizeof(BigBuf);
  30     int i;
  31
  32     memset(dest, 0, n);
  33     i = 0;
  34     for(;;) {
  35         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
  36             AT91C_BASE_SSC->SSC_THR = 0x43;
  37             LED_D_ON();
  38         }
  39         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
  40             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
  41             LED_D_OFF();
  42             if (trigger_threshold != -1 && dest[i] < trigger_threshold)
  43                 continue;
  44             else
  45                 trigger_threshold = -1;
  46             if (++i >= n) break;
  47         }
  48     }
  49     if(!silent)
  50     {
  51         Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
  52                  dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
  53
  54     }
  55 }
  56 /**
  57 * Perform sample aquisition.
  58 */
  59 void DoAcquisition125k(int trigger_threshold)
  60 {
  61     DoAcquisition125k_internal(trigger_threshold, false);
  62 }
  63
  64 /**
  65 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
  66 * if not already loaded, sets divisor and starts up the antenna.
  67 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
  68 *                                  0 or 95 ==> 125 KHz
  69 *
  70 **/
  71 void LFSetupFPGAForADC(int divisor, bool lf_field)
  72 {
  73     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
  74     if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
  75         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
  76     else if (divisor == 0)
  77         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
  78     else
  79         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
  80
  81     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
  82
  83     // Connect the A/D to the peak-detected low-frequency path.
  84     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
  85     // Give it a bit of time for the resonant antenna to settle.
  86     SpinDelay(50);
  87     // Now set up the SSC to get the ADC samples that are now streaming at us.
  88     FpgaSetupSsc();
  89 }
  90 /**
  91 * Initializes the FPGA, and acquires the samples.
  92 **/
  93 void AcquireRawAdcSamples125k(int divisor)
  94 {
  95     LFSetupFPGAForADC(divisor, true);
  96     // Now call the acquisition routine
  97     DoAcquisition125k_internal(-1,false);
  98 }
  99 /**
 100 * Initializes the FPGA for snoop-mode, and acquires the samples.
 101 **/
 102
 103 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
 104 {
 105     LFSetupFPGAForADC(divisor, false);
 106     DoAcquisition125k(trigger_threshold);
 107 }
 108
 109 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 110 {
 111
 112     /* Make sure the tag is reset */
 113     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 114     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 115     SpinDelay(2500);
 116
 117
 118     int divisor_used = 95; // 125 KHz
 119     // see if 'h' was specified
 120
 121     if (command[strlen((char *) command) - 1] == 'h')
 122         divisor_used = 88; // 134.8 KHz
 123
 124
 125     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 126     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 127     // Give it a bit of time for the resonant antenna to settle.
 128     SpinDelay(50);
 129
 130     // And a little more time for the tag to fully power up
 131     SpinDelay(2000);
 132
 133     // Now set up the SSC to get the ADC samples that are now streaming at us.
 134     FpgaSetupSsc();
 135
 136     // now modulate the reader field
 137     while(*command != '\0' && *command != ' ') {
 138         FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 139         LED_D_OFF();
 140         SpinDelayUs(delay_off);
 141         FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 142
 143         FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 144         LED_D_ON();
 145         if(*(command++) == '0')
 146             SpinDelayUs(period_0);
 147         else
 148             SpinDelayUs(period_1);
 149     }
 150     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 151     LED_D_OFF();
 152     SpinDelayUs(delay_off);
 153     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
 154
 155     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 156
 157     // now do the read
 158     DoAcquisition125k(-1);
 159 }
 160
 161 /* blank r/w tag data stream
 162 ...0000000000000000 01111111
 163 1010101010101010101010101010101010101010101010101010101010101010
 164 0011010010100001
 165 01111111
 166 101010101010101[0]000...
 167
 168 [5555fe852c5555555555555555fe0000]
 169 */
 170 void ReadTItag(void)
 171 {
 172     // some hardcoded initial params
 173     // when we read a TI tag we sample the zerocross line at 2Mhz
 174     // TI tags modulate a 1 as 16 cycles of 123.2Khz
 175     // TI tags modulate a 0 as 16 cycles of 134.2Khz
 176 #define FSAMPLE 2000000
 177 #define FREQLO 123200
 178 #define FREQHI 134200
 179
 180     signed char *dest = (signed char *)BigBuf;
 181     int n = sizeof(BigBuf);
 182     //  int *dest = GraphBuffer;
 183     //  int n = GraphTraceLen;
 184
 185     // 128 bit shift register [shift3:shift2:shift1:shift0]
 186     uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
 187
 188     int i, cycles=0, samples=0;
 189     // how many sample points fit in 16 cycles of each frequency
 190     uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
 191     // when to tell if we're close enough to one freq or another
 192     uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 193
 194     // TI tags charge at 134.2Khz
 195     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 196     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 197
 198     // Place FPGA in passthrough mode, in this mode the CROSS_LO line
 199     // connects to SSP_DIN and the SSP_DOUT logic level controls
 200     // whether we're modulating the antenna (high)
 201     // or listening to the antenna (low)
 202     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
 203
 204     // get TI tag data into the buffer
 205     AcquireTiType();
 206
 207     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 208
 209     for (i=0; i<n-1; i++) {
 210         // count cycles by looking for lo to hi zero crossings
 211         if ( (dest[i]<0) && (dest[i+1]>0) ) {
 212             cycles++;
 213             // after 16 cycles, measure the frequency
 214             if (cycles>15) {
 215                 cycles=0;
 216                 samples=i-samples; // number of samples in these 16 cycles
 217
 218                 // TI bits are coming to us lsb first so shift them
 219                 // right through our 128 bit right shift register
 220                 shift0 = (shift0>>1) | (shift1 << 31);
 221                 shift1 = (shift1>>1) | (shift2 << 31);
 222                 shift2 = (shift2>>1) | (shift3 << 31);
 223                 shift3 >>= 1;
 224
 225                 // check if the cycles fall close to the number
 226                 // expected for either the low or high frequency
 227                 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
 228                     // low frequency represents a 1
 229                     shift3 |= (1<<31);
 230                 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
 231                     // high frequency represents a 0
 232                 } else {
 233                     // probably detected a gay waveform or noise
 234                     // use this as gaydar or discard shift register and start again
 235                     shift3 = shift2 = shift1 = shift0 = 0;
 236                 }
 237                 samples = i;
 238
 239                 // for each bit we receive, test if we've detected a valid tag
 240
 241                 // if we see 17 zeroes followed by 6 ones, we might have a tag
 242                 // remember the bits are backwards
 243                 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
 244                     // if start and end bytes match, we have a tag so break out of the loop
 245                     if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
 246                         cycles = 0xF0B; //use this as a flag (ugly but whatever)
 247                         break;
 248                     }
 249                 }
 250             }
 251         }
 252     }
 253
 254     // if flag is set we have a tag
 255     if (cycles!=0xF0B) {
 256         DbpString("Info: No valid tag detected.");
 257     } else {
 258         // put 64 bit data into shift1 and shift0
 259         shift0 = (shift0>>24) | (shift1 << 8);
 260         shift1 = (shift1>>24) | (shift2 << 8);
 261
 262         // align 16 bit crc into lower half of shift2
 263         shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
 264
 265         // if r/w tag, check ident match
 266         if ( shift3&(1<<15) ) {
 267             DbpString("Info: TI tag is rewriteable");
 268             // only 15 bits compare, last bit of ident is not valid
 269             if ( ((shift3>>16)^shift0)&0x7fff ) {
 270                 DbpString("Error: Ident mismatch!");
 271             } else {
 272                 DbpString("Info: TI tag ident is valid");
 273             }
 274         } else {
 275             DbpString("Info: TI tag is readonly");
 276         }
 277
 278         // WARNING the order of the bytes in which we calc crc below needs checking
 279         // i'm 99% sure the crc algorithm is correct, but it may need to eat the
 280         // bytes in reverse or something
 281         // calculate CRC
 282         uint32_t crc=0;
 283
 284         crc = update_crc16(crc, (shift0)&0xff);
 285         crc = update_crc16(crc, (shift0>>8)&0xff);
 286         crc = update_crc16(crc, (shift0>>16)&0xff);
 287         crc = update_crc16(crc, (shift0>>24)&0xff);
 288         crc = update_crc16(crc, (shift1)&0xff);
 289         crc = update_crc16(crc, (shift1>>8)&0xff);
 290         crc = update_crc16(crc, (shift1>>16)&0xff);
 291         crc = update_crc16(crc, (shift1>>24)&0xff);
 292
 293         Dbprintf("Info: Tag data: %x%08x, crc=%x",
 294                  (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
 295         if (crc != (shift2&0xffff)) {
 296             Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
 297         } else {
 298             DbpString("Info: CRC is good");
 299         }
 300     }
 301 }
 302
 303 void WriteTIbyte(uint8_t b)
 304 {
 305     int i = 0;
 306
 307     // modulate 8 bits out to the antenna
 308     for (i=0; i<8; i++)
 309     {
 310         if (b&(1<<i)) {
 311             // stop modulating antenna
 312             LOW(GPIO_SSC_DOUT);
 313             SpinDelayUs(1000);
 314             // modulate antenna
 315             HIGH(GPIO_SSC_DOUT);
 316             SpinDelayUs(1000);
 317         } else {
 318             // stop modulating antenna
 319             LOW(GPIO_SSC_DOUT);
 320             SpinDelayUs(300);
 321             // modulate antenna
 322             HIGH(GPIO_SSC_DOUT);
 323             SpinDelayUs(1700);
 324         }
 325     }
 326 }
 327
 328 void AcquireTiType(void)
 329 {
 330     int i, j, n;
 331     // tag transmission is <20ms, sampling at 2M gives us 40K samples max
 332     // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
 333 #define TIBUFLEN 1250
 334
 335     // clear buffer
 336     memset(BigBuf,0,sizeof(BigBuf));
 337
 338     // Set up the synchronous serial port
 339     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
 340     AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
 341
 342     // steal this pin from the SSP and use it to control the modulation
 343     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 344     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 345
 346     AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
 347     AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
 348
 349     // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
 350     // 48/2 = 24 MHz clock must be divided by 12
 351     AT91C_BASE_SSC->SSC_CMR = 12;
 352
 353     AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
 354     AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
 355     AT91C_BASE_SSC->SSC_TCMR = 0;
 356     AT91C_BASE_SSC->SSC_TFMR = 0;
 357
 358     LED_D_ON();
 359
 360     // modulate antenna
 361     HIGH(GPIO_SSC_DOUT);
 362
 363     // Charge TI tag for 50ms.
 364     SpinDelay(50);
 365
 366     // stop modulating antenna and listen
 367     LOW(GPIO_SSC_DOUT);
 368
 369     LED_D_OFF();
 370
 371     i = 0;
 372     for(;;) {
 373         if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
 374             BigBuf[i] = AT91C_BASE_SSC->SSC_RHR;        // store 32 bit values in buffer
 375             i++; if(i >= TIBUFLEN) break;
 376         }
 377         WDT_HIT();
 378     }
 379
 380     // return stolen pin to SSP
 381     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
 382     AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
 383
 384     char *dest = (char *)BigBuf;
 385     n = TIBUFLEN*32;
 386     // unpack buffer
 387     for (i=TIBUFLEN-1; i>=0; i--) {
 388         for (j=0; j<32; j++) {
 389             if(BigBuf[i] & (1 << j)) {
 390                 dest[--n] = 1;
 391             } else {
 392                 dest[--n] = -1;
 393             }
 394         }
 395     }
 396 }
 397
 398 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
 399 // if crc provided, it will be written with the data verbatim (even if bogus)
 400 // if not provided a valid crc will be computed from the data and written.
 401 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 402 {
 403     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 404     if(crc == 0) {
 405         crc = update_crc16(crc, (idlo)&0xff);
 406         crc = update_crc16(crc, (idlo>>8)&0xff);
 407         crc = update_crc16(crc, (idlo>>16)&0xff);
 408         crc = update_crc16(crc, (idlo>>24)&0xff);
 409         crc = update_crc16(crc, (idhi)&0xff);
 410         crc = update_crc16(crc, (idhi>>8)&0xff);
 411         crc = update_crc16(crc, (idhi>>16)&0xff);
 412         crc = update_crc16(crc, (idhi>>24)&0xff);
 413     }
 414     Dbprintf("Writing to tag: %x%08x, crc=%x",
 415              (unsigned int) idhi, (unsigned int) idlo, crc);
 416
 417     // TI tags charge at 134.2Khz
 418     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 419     // Place FPGA in passthrough mode, in this mode the CROSS_LO line
 420     // connects to SSP_DIN and the SSP_DOUT logic level controls
 421     // whether we're modulating the antenna (high)
 422     // or listening to the antenna (low)
 423     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
 424     LED_A_ON();
 425
 426     // steal this pin from the SSP and use it to control the modulation
 427     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
 428     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 429
 430     // writing algorithm:
 431     // a high bit consists of a field off for 1ms and field on for 1ms
 432     // a low bit consists of a field off for 0.3ms and field on for 1.7ms
 433     // initiate a charge time of 50ms (field on) then immediately start writing bits
 434     // start by writing 0xBB (keyword) and 0xEB (password)
 435     // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
 436     // finally end with 0x0300 (write frame)
 437     // all data is sent lsb firts
 438     // finish with 15ms programming time
 439
 440     // modulate antenna
 441     HIGH(GPIO_SSC_DOUT);
 442     SpinDelay(50);      // charge time
 443
 444     WriteTIbyte(0xbb); // keyword
 445     WriteTIbyte(0xeb); // password
 446     WriteTIbyte( (idlo    )&0xff );
 447     WriteTIbyte( (idlo>>8 )&0xff );
 448     WriteTIbyte( (idlo>>16)&0xff );
 449     WriteTIbyte( (idlo>>24)&0xff );
 450     WriteTIbyte( (idhi    )&0xff );
 451     WriteTIbyte( (idhi>>8 )&0xff );
 452     WriteTIbyte( (idhi>>16)&0xff );
 453     WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
 454     WriteTIbyte( (crc     )&0xff ); // crc lo
 455     WriteTIbyte( (crc>>8  )&0xff ); // crc hi
 456     WriteTIbyte(0x00); // write frame lo
 457     WriteTIbyte(0x03); // write frame hi
 458     HIGH(GPIO_SSC_DOUT);
 459     SpinDelay(50);      // programming time
 460
 461     LED_A_OFF();
 462
 463     // get TI tag data into the buffer
 464     AcquireTiType();
 465
 466     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 467     DbpString("Now use tiread to check");
 468 }
 469
 470 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 471 {
 472     int i;
 473     uint8_t *tab = (uint8_t *)BigBuf;
 474
 475     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 476     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
 477
 478     AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
 479
 480     AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
 481     AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
 482
 483 #define SHORT_COIL()    LOW(GPIO_SSC_DOUT)
 484 #define OPEN_COIL()             HIGH(GPIO_SSC_DOUT)
 485
 486     i = 0;
 487     for(;;) {
 488         while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
 489             if(BUTTON_PRESS()) {
 490                 DbpString("Stopped");
 491                 return;
 492             }
 493             WDT_HIT();
 494         }
 495
 496         if (ledcontrol)
 497             LED_D_ON();
 498
 499         if(tab[i])
 500             OPEN_COIL();
 501         else
 502             SHORT_COIL();
 503
 504         if (ledcontrol)
 505             LED_D_OFF();
 506
 507         while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
 508             if(BUTTON_PRESS()) {
 509                 DbpString("Stopped");
 510                 return;
 511             }
 512             WDT_HIT();
 513         }
 514
 515         i++;
 516         if(i == period) {
 517             i = 0;
 518             if (gap) {
 519                 SHORT_COIL();
 520                 SpinDelayUs(gap);
 521             }
 522         }
 523     }
 524 }
 525
 526 #define DEBUG_FRAME_CONTENTS 1
 527 void SimulateTagLowFrequencyBidir(int divisor, int t0)
 528 {
 529 }
 530
 531 // compose fc/8 fc/10 waveform
 532 static void fc(int c, int *n) {
 533     uint8_t *dest = (uint8_t *)BigBuf;
 534     int idx;
 535
 536     // for when we want an fc8 pattern every 4 logical bits
 537     if(c==0) {
 538         dest[((*n)++)]=1;
 539         dest[((*n)++)]=1;
 540         dest[((*n)++)]=0;
 541         dest[((*n)++)]=0;
 542         dest[((*n)++)]=0;
 543         dest[((*n)++)]=0;
 544         dest[((*n)++)]=0;
 545         dest[((*n)++)]=0;
 546     }
 547     //  an fc/8  encoded bit is a bit pattern of  11000000  x6 = 48 samples
 548     if(c==8) {
 549         for (idx=0; idx<6; idx++) {
 550             dest[((*n)++)]=1;
 551             dest[((*n)++)]=1;
 552             dest[((*n)++)]=0;
 553             dest[((*n)++)]=0;
 554             dest[((*n)++)]=0;
 555             dest[((*n)++)]=0;
 556             dest[((*n)++)]=0;
 557             dest[((*n)++)]=0;
 558         }
 559     }
 560
 561     //  an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
 562     if(c==10) {
 563         for (idx=0; idx<5; idx++) {
 564             dest[((*n)++)]=1;
 565             dest[((*n)++)]=1;
 566             dest[((*n)++)]=1;
 567             dest[((*n)++)]=0;
 568             dest[((*n)++)]=0;
 569             dest[((*n)++)]=0;
 570             dest[((*n)++)]=0;
 571             dest[((*n)++)]=0;
 572             dest[((*n)++)]=0;
 573             dest[((*n)++)]=0;
 574         }
 575     }
 576 }
 577
 578 // prepare a waveform pattern in the buffer based on the ID given then
 579 // simulate a HID tag until the button is pressed
 580 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 581 {
 582     int n=0, i=0;
 583     /*
 584      HID tag bitstream format
 585      The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
 586      A 1 bit is represented as 6 fc8 and 5 fc10 patterns
 587      A 0 bit is represented as 5 fc10 and 6 fc8 patterns
 588      A fc8 is inserted before every 4 bits
 589      A special start of frame pattern is used consisting a0b0 where a and b are neither 0
 590      nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
 591     */
 592
 593     if (hi>0xFFF) {
 594         DbpString("Tags can only have 44 bits.");
 595         return;
 596     }
 597     fc(0,&n);
 598     // special start of frame marker containing invalid bit sequences
 599     fc(8,  &n); fc(8,  &n);     // invalid
 600     fc(8,  &n); fc(10, &n); // logical 0
 601     fc(10, &n); fc(10, &n); // invalid
 602     fc(8,  &n); fc(10, &n); // logical 0
 603
 604     WDT_HIT();
 605     // manchester encode bits 43 to 32
 606     for (i=11; i>=0; i--) {
 607         if ((i%4)==3) fc(0,&n);
 608         if ((hi>>i)&1) {
 609             fc(10, &n); fc(8,  &n);             // low-high transition
 610         } else {
 611             fc(8,  &n); fc(10, &n);             // high-low transition
 612         }
 613     }
 614
 615     WDT_HIT();
 616     // manchester encode bits 31 to 0
 617     for (i=31; i>=0; i--) {
 618         if ((i%4)==3) fc(0,&n);
 619         if ((lo>>i)&1) {
 620             fc(10, &n); fc(8,  &n);             // low-high transition
 621         } else {
 622             fc(8,  &n); fc(10, &n);             // high-low transition
 623         }
 624     }
 625
 626     if (ledcontrol)
 627         LED_A_ON();
 628     SimulateTagLowFrequency(n, 0, ledcontrol);
 629
 630     if (ledcontrol)
 631         LED_A_OFF();
 632 }
 633
 634 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
 635 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 636 {
 637     uint8_t *dest = (uint8_t *)BigBuf;
 638
 639     size_t size=0; //, found=0;
 640     uint32_t hi2=0, hi=0, lo=0;
 641
 642     // Configure to go in 125Khz listen mode
 643     LFSetupFPGAForADC(95, true);
 644
 645     while(!BUTTON_PRESS()) {
 646
 647         WDT_HIT();
 648         if (ledcontrol) LED_A_ON();
 649
 650         DoAcquisition125k_internal(-1,true);
 651         size  = sizeof(BigBuf);
 652         if (size < 2000) continue;
 653         // FSK demodulator
 654
 655         int bitLen = HIDdemodFSK(dest,size,&hi2,&hi,&lo);
 656
 657         WDT_HIT();
 658
 659         if (bitLen>0 && lo>0){
 660             // final loop, go over previously decoded manchester data and decode into usable tag ID
 661             // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
 662             if (hi2 != 0){ //extra large HID tags
 663                 Dbprintf("TAG ID: %x%08x%08x (%d)",
 664                          (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
 665             }else {  //standard HID tags <38 bits
 666                 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
 667                 uint8_t bitlen = 0;
 668                 uint32_t fc = 0;
 669                 uint32_t cardnum = 0;
 670                 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
 671                     uint32_t lo2=0;
 672                     lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
 673                     uint8_t idx3 = 1;
 674                     while(lo2>1){ //find last bit set to 1 (format len bit)
 675                         lo2=lo2>>1;
 676                         idx3++;
 677                     }
 678                     bitlen =idx3+19;
 679                     fc =0;
 680                     cardnum=0;
 681                     if(bitlen==26){
 682                         cardnum = (lo>>1)&0xFFFF;
 683                         fc = (lo>>17)&0xFF;
 684                     }
 685                     if(bitlen==37){
 686                         cardnum = (lo>>1)&0x7FFFF;
 687                         fc = ((hi&0xF)<<12)|(lo>>20);
 688                     }
 689                     if(bitlen==34){
 690                         cardnum = (lo>>1)&0xFFFF;
 691                         fc= ((hi&1)<<15)|(lo>>17);
 692                     }
 693                     if(bitlen==35){
 694                         cardnum = (lo>>1)&0xFFFFF;
 695                         fc = ((hi&1)<<11)|(lo>>21);
 696                     }
 697                 }
 698                 else { //if bit 38 is not set then 37 bit format is used
 699                     bitlen= 37;
 700                     fc =0;
 701                     cardnum=0;
 702                     if(bitlen==37){
 703                         cardnum = (lo>>1)&0x7FFFF;
 704                         fc = ((hi&0xF)<<12)|(lo>>20);
 705                     }
 706                 }
 707                 //Dbprintf("TAG ID: %x%08x (%d)",
 708                 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
 709                 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
 710                          (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
 711                          (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
 712             }
 713             if (findone){
 714                 if (ledcontrol) LED_A_OFF();
 715                 return;
 716             }
 717             // reset
 718             hi2 = hi = lo = 0;
 719         }
 720         WDT_HIT();
 721         //SpinDelay(50);
 722     }
 723     DbpString("Stopped");
 724     if (ledcontrol) LED_A_OFF();
 725 }
 726
 727 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
 728 {
 729     uint8_t *dest = (uint8_t *)BigBuf;
 730
 731     size_t size=0; //, found=0;
 732     uint32_t bitLen=0;
 733     int clk=0, invert=0, errCnt=0;
 734     uint64_t lo=0;
 735     // Configure to go in 125Khz listen mode
 736     LFSetupFPGAForADC(95, true);
 737
 738     while(!BUTTON_PRESS()) {
 739
 740         WDT_HIT();
 741         if (ledcontrol) LED_A_ON();
 742
 743         DoAcquisition125k_internal(-1,true);
 744         size  = sizeof(BigBuf);
 745         if (size < 2000) continue;
 746         // FSK demodulator
 747         //int askmandemod(uint8_t *BinStream,uint32_t *BitLen,int *clk, int *invert);
 748         bitLen=size;
 749         //Dbprintf("DEBUG: Buffer got");
 750         errCnt = askmandemod(dest,&bitLen,&clk,&invert); //HIDdemodFSK(dest,size,&hi2,&hi,&lo);
 751         //Dbprintf("DEBUG: ASK Got");
 752         WDT_HIT();
 753
 754         if (errCnt>=0){
 755             lo = Em410xDecode(dest,bitLen);
 756             //Dbprintf("DEBUG: EM GOT");
 757             //printEM410x(lo);
 758             if (lo>0){
 759                 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",(uint32_t)(lo>>32),(uint32_t)lo,(uint32_t)(lo&0xFFFF),(uint32_t)((lo>>16LL) & 0xFF),(uint32_t)(lo & 0xFFFFFF));
 760             }
 761             if (findone){
 762                 if (ledcontrol) LED_A_OFF();
 763                 return;
 764             }
 765         } else{
 766             //Dbprintf("DEBUG: No Tag");
 767         }
 768         WDT_HIT();
 769         lo = 0;
 770         clk=0;
 771         invert=0;
 772         errCnt=0;
 773         size=0;
 774         //SpinDelay(50);
 775     }
 776     DbpString("Stopped");
 777     if (ledcontrol) LED_A_OFF();
 778 }
 779
 780 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 781 {
 782     uint8_t *dest = (uint8_t *)BigBuf;
 783     size_t size=0;
 784     int idx=0;
 785     uint32_t code=0, code2=0;
 786     uint8_t version=0;
 787     uint8_t facilitycode=0;
 788     uint16_t number=0;
 789     // Configure to go in 125Khz listen mode
 790     LFSetupFPGAForADC(95, true);
 791
 792     while(!BUTTON_PRESS()) {
 793         WDT_HIT();
 794         if (ledcontrol) LED_A_ON();
 795         DoAcquisition125k_internal(-1,true);
 796         //fskdemod and get start index
 797         WDT_HIT();
 798         idx = IOdemodFSK(dest,sizeof(BigBuf));
 799         if (idx>0){
 800             //valid tag found
 801
 802             //Index map
 803             //0           10          20          30          40          50          60
 804             //|           |           |           |           |           |           |
 805             //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
 806             //-----------------------------------------------------------------------------
 807             //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
 808             //
 809             //XSF(version)facility:codeone+codetwo
 810             //Handle the data
 811             if(findone){ //only print binary if we are doing one
 812                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
 813                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
 814                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
 815                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
 816                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
 817                 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
 818                 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
 819             }
 820             code = bytebits_to_byte(dest+idx,32);
 821             code2 = bytebits_to_byte(dest+idx+32,32);
 822             version = bytebits_to_byte(dest+idx+27,8); //14,4
 823             facilitycode = bytebits_to_byte(dest+idx+18,8) ;
 824             number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
 825
 826             Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
 827             // if we're only looking for one tag
 828             if (findone){
 829                 if (ledcontrol) LED_A_OFF();
 830                 //LED_A_OFF();
 831                 return;
 832             }
 833             code=code2=0;
 834             version=facilitycode=0;
 835             number=0;
 836             idx=0;
 837         }
 838         WDT_HIT();
 839     }
 840     DbpString("Stopped");
 841     if (ledcontrol) LED_A_OFF();
 842 }
 843
 844 /*------------------------------
 845  * T5555/T5557/T5567 routines
 846  *------------------------------
 847  */
 848
 849 /* T55x7 configuration register definitions */
 850 #define T55x7_POR_DELAY                 0x00000001
 851 #define T55x7_ST_TERMINATOR             0x00000008
 852 #define T55x7_PWD                       0x00000010
 853 #define T55x7_MAXBLOCK_SHIFT            5
 854 #define T55x7_AOR                       0x00000200
 855 #define T55x7_PSKCF_RF_2                0
 856 #define T55x7_PSKCF_RF_4                0x00000400
 857 #define T55x7_PSKCF_RF_8                0x00000800
 858 #define T55x7_MODULATION_DIRECT         0
 859 #define T55x7_MODULATION_PSK1           0x00001000
 860 #define T55x7_MODULATION_PSK2           0x00002000
 861 #define T55x7_MODULATION_PSK3           0x00003000
 862 #define T55x7_MODULATION_FSK1           0x00004000
 863 #define T55x7_MODULATION_FSK2           0x00005000
 864 #define T55x7_MODULATION_FSK1a          0x00006000
 865 #define T55x7_MODULATION_FSK2a          0x00007000
 866 #define T55x7_MODULATION_MANCHESTER     0x00008000
 867 #define T55x7_MODULATION_BIPHASE        0x00010000
 868 #define T55x7_BITRATE_RF_8              0
 869 #define T55x7_BITRATE_RF_16             0x00040000
 870 #define T55x7_BITRATE_RF_32             0x00080000
 871 #define T55x7_BITRATE_RF_40             0x000C0000
 872 #define T55x7_BITRATE_RF_50             0x00100000
 873 #define T55x7_BITRATE_RF_64             0x00140000
 874 #define T55x7_BITRATE_RF_100            0x00180000
 875 #define T55x7_BITRATE_RF_128            0x001C0000
 876
 877 /* T5555 (Q5) configuration register definitions */
 878 #define T5555_ST_TERMINATOR             0x00000001
 879 #define T5555_MAXBLOCK_SHIFT            0x00000001
 880 #define T5555_MODULATION_MANCHESTER     0
 881 #define T5555_MODULATION_PSK1           0x00000010
 882 #define T5555_MODULATION_PSK2           0x00000020
 883 #define T5555_MODULATION_PSK3           0x00000030
 884 #define T5555_MODULATION_FSK1           0x00000040
 885 #define T5555_MODULATION_FSK2           0x00000050
 886 #define T5555_MODULATION_BIPHASE        0x00000060
 887 #define T5555_MODULATION_DIRECT         0x00000070
 888 #define T5555_INVERT_OUTPUT             0x00000080
 889 #define T5555_PSK_RF_2                  0
 890 #define T5555_PSK_RF_4                  0x00000100
 891 #define T5555_PSK_RF_8                  0x00000200
 892 #define T5555_USE_PWD                   0x00000400
 893 #define T5555_USE_AOR                   0x00000800
 894 #define T5555_BITRATE_SHIFT             12
 895 #define T5555_FAST_WRITE                0x00004000
 896 #define T5555_PAGE_SELECT               0x00008000
 897
 898 /*
 899  * Relevant times in microsecond
 900  * To compensate antenna falling times shorten the write times
 901  * and enlarge the gap ones.
 902  */
 903 #define START_GAP 250
 904 #define WRITE_GAP 160
 905 #define WRITE_0   144 // 192
 906 #define WRITE_1   400 // 432 for T55x7; 448 for E5550
 907
 908 // Write one bit to card
 909 void T55xxWriteBit(int bit)
 910 {
 911     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 912     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 913     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 914     if (bit == 0)
 915         SpinDelayUs(WRITE_0);
 916     else
 917         SpinDelayUs(WRITE_1);
 918     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 919     SpinDelayUs(WRITE_GAP);
 920 }
 921
 922 // Write one card block in page 0, no lock
 923 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 924 {
 925     //unsigned int i;  //enio adjustment 12/10/14
 926     uint32_t i;
 927
 928     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 929     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 930     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 931
 932     // Give it a bit of time for the resonant antenna to settle.
 933     // And for the tag to fully power up
 934     SpinDelay(150);
 935
 936     // Now start writting
 937     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 938     SpinDelayUs(START_GAP);
 939
 940     // Opcode
 941     T55xxWriteBit(1);
 942     T55xxWriteBit(0); //Page 0
 943     if (PwdMode == 1){
 944         // Pwd
 945         for (i = 0x80000000; i != 0; i >>= 1)
 946             T55xxWriteBit(Pwd & i);
 947     }
 948     // Lock bit
 949     T55xxWriteBit(0);
 950
 951     // Data
 952     for (i = 0x80000000; i != 0; i >>= 1)
 953         T55xxWriteBit(Data & i);
 954
 955     // Block
 956     for (i = 0x04; i != 0; i >>= 1)
 957         T55xxWriteBit(Block & i);
 958
 959     // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
 960     // so wait a little more)
 961     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 962     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 963     SpinDelay(20);
 964     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 965 }
 966
 967 // Read one card block in page 0
 968 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 969 {
 970     uint8_t *dest = (uint8_t *)BigBuf;
 971     //int m=0, i=0; //enio adjustment 12/10/14
 972     uint32_t m=0, i=0;
 973     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
 974     m = sizeof(BigBuf);
 975     // Clear destination buffer before sending the command
 976     memset(dest, 128, m);
 977     // Connect the A/D to the peak-detected low-frequency path.
 978     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 979     // Now set up the SSC to get the ADC samples that are now streaming at us.
 980     FpgaSetupSsc();
 981
 982     LED_D_ON();
 983     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 984     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 985
 986     // Give it a bit of time for the resonant antenna to settle.
 987     // And for the tag to fully power up
 988     SpinDelay(150);
 989
 990     // Now start writting
 991     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 992     SpinDelayUs(START_GAP);
 993
 994     // Opcode
 995     T55xxWriteBit(1);
 996     T55xxWriteBit(0); //Page 0
 997     if (PwdMode == 1){
 998         // Pwd
 999         for (i = 0x80000000; i != 0; i >>= 1)
1000             T55xxWriteBit(Pwd & i);
1001     }
1002     // Lock bit
1003     T55xxWriteBit(0);
1004     // Block
1005     for (i = 0x04; i != 0; i >>= 1)
1006         T55xxWriteBit(Block & i);
1007
1008     // Turn field on to read the response
1009     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1010     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1011
1012     // Now do the acquisition
1013     i = 0;
1014     for(;;) {
1015         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1016             AT91C_BASE_SSC->SSC_THR = 0x43;
1017         }
1018         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1019             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1020             // we don't care about actual value, only if it's more or less than a
1021             // threshold essentially we capture zero crossings for later analysis
1022             //                  if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1023             i++;
1024             if (i >= m) break;
1025         }
1026     }
1027
1028     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1029     LED_D_OFF();
1030     DbpString("DONE!");
1031 }
1032
1033 // Read card traceability data (page 1)
1034 void T55xxReadTrace(void){
1035     uint8_t *dest = (uint8_t *)BigBuf;
1036     int m=0, i=0;
1037
1038     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1039     m = sizeof(BigBuf);
1040     // Clear destination buffer before sending the command
1041     memset(dest, 128, m);
1042     // Connect the A/D to the peak-detected low-frequency path.
1043     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1044     // Now set up the SSC to get the ADC samples that are now streaming at us.
1045     FpgaSetupSsc();
1046
1047     LED_D_ON();
1048     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1049     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1050
1051     // Give it a bit of time for the resonant antenna to settle.
1052     // And for the tag to fully power up
1053     SpinDelay(150);
1054
1055     // Now start writting
1056     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1057     SpinDelayUs(START_GAP);
1058
1059     // Opcode
1060     T55xxWriteBit(1);
1061     T55xxWriteBit(1); //Page 1
1062
1063     // Turn field on to read the response
1064     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1065     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1066
1067     // Now do the acquisition
1068     i = 0;
1069     for(;;) {
1070         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1071             AT91C_BASE_SSC->SSC_THR = 0x43;
1072         }
1073         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1074             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1075             i++;
1076             if (i >= m) break;
1077         }
1078     }
1079
1080     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1081     LED_D_OFF();
1082     DbpString("DONE!");
1083 }
1084
1085 /*-------------- Cloning routines -----------*/
1086 // Copy HID id to card and setup block 0 config
1087 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1088 {
1089     int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1090     int last_block = 0;
1091
1092     if (longFMT){
1093         // Ensure no more than 84 bits supplied
1094         if (hi2>0xFFFFF) {
1095             DbpString("Tags can only have 84 bits.");
1096             return;
1097         }
1098         // Build the 6 data blocks for supplied 84bit ID
1099         last_block = 6;
1100         data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1101         for (int i=0;i<4;i++) {
1102             if (hi2 & (1<<(19-i)))
1103                 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1104             else
1105                 data1 |= (1<<((3-i)*2)); // 0 -> 01
1106         }
1107
1108         data2 = 0;
1109         for (int i=0;i<16;i++) {
1110             if (hi2 & (1<<(15-i)))
1111                 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1112             else
1113                 data2 |= (1<<((15-i)*2)); // 0 -> 01
1114         }
1115
1116         data3 = 0;
1117         for (int i=0;i<16;i++) {
1118             if (hi & (1<<(31-i)))
1119                 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1120             else
1121                 data3 |= (1<<((15-i)*2)); // 0 -> 01
1122         }
1123
1124         data4 = 0;
1125         for (int i=0;i<16;i++) {
1126             if (hi & (1<<(15-i)))
1127                 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1128             else
1129                 data4 |= (1<<((15-i)*2)); // 0 -> 01
1130         }
1131
1132         data5 = 0;
1133         for (int i=0;i<16;i++) {
1134             if (lo & (1<<(31-i)))
1135                 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1136             else
1137                 data5 |= (1<<((15-i)*2)); // 0 -> 01
1138         }
1139
1140         data6 = 0;
1141         for (int i=0;i<16;i++) {
1142             if (lo & (1<<(15-i)))
1143                 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1144             else
1145                 data6 |= (1<<((15-i)*2)); // 0 -> 01
1146         }
1147     }
1148     else {
1149         // Ensure no more than 44 bits supplied
1150         if (hi>0xFFF) {
1151             DbpString("Tags can only have 44 bits.");
1152             return;
1153         }
1154
1155         // Build the 3 data blocks for supplied 44bit ID
1156         last_block = 3;
1157
1158         data1 = 0x1D000000; // load preamble
1159
1160         for (int i=0;i<12;i++) {
1161             if (hi & (1<<(11-i)))
1162                 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1163             else
1164                 data1 |= (1<<((11-i)*2)); // 0 -> 01
1165         }
1166
1167         data2 = 0;
1168         for (int i=0;i<16;i++) {
1169             if (lo & (1<<(31-i)))
1170                 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1171             else
1172                 data2 |= (1<<((15-i)*2)); // 0 -> 01
1173         }
1174
1175         data3 = 0;
1176         for (int i=0;i<16;i++) {
1177             if (lo & (1<<(15-i)))
1178                 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1179             else
1180                 data3 |= (1<<((15-i)*2)); // 0 -> 01
1181         }
1182     }
1183
1184     LED_D_ON();
1185     // Program the data blocks for supplied ID
1186     // and the block 0 for HID format
1187     T55xxWriteBlock(data1,1,0,0);
1188     T55xxWriteBlock(data2,2,0,0);
1189     T55xxWriteBlock(data3,3,0,0);
1190
1191     if (longFMT) { // if long format there are 6 blocks
1192         T55xxWriteBlock(data4,4,0,0);
1193         T55xxWriteBlock(data5,5,0,0);
1194         T55xxWriteBlock(data6,6,0,0);
1195     }
1196
1197     // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1198     T55xxWriteBlock(T55x7_BITRATE_RF_50    |
1199                     T55x7_MODULATION_FSK2a |
1200                     last_block << T55x7_MAXBLOCK_SHIFT,
1201                     0,0,0);
1202
1203     LED_D_OFF();
1204
1205     DbpString("DONE!");
1206 }
1207
1208 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1209 {
1210     int data1=0, data2=0; //up to six blocks for long format
1211
1212     data1 = hi;  // load preamble
1213     data2 = lo;
1214
1215     LED_D_ON();
1216     // Program the data blocks for supplied ID
1217     // and the block 0 for HID format
1218     T55xxWriteBlock(data1,1,0,0);
1219     T55xxWriteBlock(data2,2,0,0);
1220
1221     //Config Block
1222     T55xxWriteBlock(0x00147040,0,0,0);
1223     LED_D_OFF();
1224
1225     DbpString("DONE!");
1226 }
1227
1228 // Define 9bit header for EM410x tags
1229 #define EM410X_HEADER           0x1FF
1230 #define EM410X_ID_LENGTH        40
1231
1232 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1233 {
1234     int i, id_bit;
1235     uint64_t id = EM410X_HEADER;
1236     uint64_t rev_id = 0;        // reversed ID
1237     int c_parity[4];    // column parity
1238     int r_parity = 0;   // row parity
1239     uint32_t clock = 0;
1240
1241     // Reverse ID bits given as parameter (for simpler operations)
1242     for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1243         if (i < 32) {
1244             rev_id = (rev_id << 1) | (id_lo & 1);
1245             id_lo >>= 1;
1246         } else {
1247             rev_id = (rev_id << 1) | (id_hi & 1);
1248             id_hi >>= 1;
1249         }
1250     }
1251
1252     for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1253         id_bit = rev_id & 1;
1254
1255         if (i % 4 == 0) {
1256             // Don't write row parity bit at start of parsing
1257             if (i)
1258                 id = (id << 1) | r_parity;
1259             // Start counting parity for new row
1260             r_parity = id_bit;
1261         } else {
1262             // Count row parity
1263             r_parity ^= id_bit;
1264         }
1265
1266         // First elements in column?
1267         if (i < 4)
1268             // Fill out first elements
1269             c_parity[i] = id_bit;
1270         else
1271             // Count column parity
1272             c_parity[i % 4] ^= id_bit;
1273
1274         // Insert ID bit
1275         id = (id << 1) | id_bit;
1276         rev_id >>= 1;
1277     }
1278
1279     // Insert parity bit of last row
1280     id = (id << 1) | r_parity;
1281
1282     // Fill out column parity at the end of tag
1283     for (i = 0; i < 4; ++i)
1284         id = (id << 1) | c_parity[i];
1285
1286     // Add stop bit
1287     id <<= 1;
1288
1289     Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1290     LED_D_ON();
1291
1292     // Write EM410x ID
1293     T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1294     T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1295
1296     // Config for EM410x (RF/64, Manchester, Maxblock=2)
1297     if (card) {
1298         // Clock rate is stored in bits 8-15 of the card value
1299         clock = (card & 0xFF00) >> 8;
1300         Dbprintf("Clock rate: %d", clock);
1301         switch (clock)
1302         {
1303         case 32:
1304             clock = T55x7_BITRATE_RF_32;
1305             break;
1306         case 16:
1307             clock = T55x7_BITRATE_RF_16;
1308             break;
1309         case 0:
1310             // A value of 0 is assumed to be 64 for backwards-compatibility
1311             // Fall through...
1312         case 64:
1313             clock = T55x7_BITRATE_RF_64;
1314             break;
1315         default:
1316             Dbprintf("Invalid clock rate: %d", clock);
1317             return;
1318         }
1319
1320         // Writing configuration for T55x7 tag
1321         T55xxWriteBlock(clock       |
1322                         T55x7_MODULATION_MANCHESTER |
1323                         2 << T55x7_MAXBLOCK_SHIFT,
1324                         0, 0, 0);
1325     }
1326     else
1327         // Writing configuration for T5555(Q5) tag
1328         T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1329                         T5555_MODULATION_MANCHESTER   |
1330                         2 << T5555_MAXBLOCK_SHIFT,
1331                         0, 0, 0);
1332
1333     LED_D_OFF();
1334     Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1335              (uint32_t)(id >> 32), (uint32_t)id);
1336 }
1337
1338 // Clone Indala 64-bit tag by UID to T55x7
1339 void CopyIndala64toT55x7(int hi, int lo)
1340 {
1341
1342     //Program the 2 data blocks for supplied 64bit UID
1343     // and the block 0 for Indala64 format
1344     T55xxWriteBlock(hi,1,0,0);
1345     T55xxWriteBlock(lo,2,0,0);
1346     //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1347     T55xxWriteBlock(T55x7_BITRATE_RF_32    |
1348                     T55x7_MODULATION_PSK1 |
1349                     2 << T55x7_MAXBLOCK_SHIFT,
1350                     0, 0, 0);
1351     //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1352     //  T5567WriteBlock(0x603E1042,0);
1353
1354     DbpString("DONE!");
1355
1356 }
1357
1358 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1359 {
1360
1361     //Program the 7 data blocks for supplied 224bit UID
1362     // and the block 0 for Indala224 format
1363     T55xxWriteBlock(uid1,1,0,0);
1364     T55xxWriteBlock(uid2,2,0,0);
1365     T55xxWriteBlock(uid3,3,0,0);
1366     T55xxWriteBlock(uid4,4,0,0);
1367     T55xxWriteBlock(uid5,5,0,0);
1368     T55xxWriteBlock(uid6,6,0,0);
1369     T55xxWriteBlock(uid7,7,0,0);
1370     //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1371     T55xxWriteBlock(T55x7_BITRATE_RF_32    |
1372                     T55x7_MODULATION_PSK1 |
1373                     7 << T55x7_MAXBLOCK_SHIFT,
1374                     0,0,0);
1375     //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1376     //  T5567WriteBlock(0x603E10E2,0);
1377
1378     DbpString("DONE!");
1379
1380 }
1381
1382
1383 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1384 #define max(x,y) ( x<y ? y:x)
1385
1386 int DemodPCF7931(uint8_t **outBlocks) {
1387     uint8_t BitStream[256];
1388     uint8_t Blocks[8][16];
1389     uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1390     int GraphTraceLen = sizeof(BigBuf);
1391     int i, j, lastval, bitidx, half_switch;
1392     int clock = 64;
1393     int tolerance = clock / 8;
1394     int pmc, block_done;
1395     int lc, warnings = 0;
1396     int num_blocks = 0;
1397     int lmin=128, lmax=128;
1398     uint8_t dir;
1399
1400     AcquireRawAdcSamples125k(0);
1401
1402     lmin = 64;
1403     lmax = 192;
1404
1405     i = 2;
1406
1407     /* Find first local max/min */
1408     if(GraphBuffer[1] > GraphBuffer[0]) {
1409         while(i < GraphTraceLen) {
1410             if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1411                 break;
1412             i++;
1413         }
1414         dir = 0;
1415     }
1416     else {
1417         while(i < GraphTraceLen) {
1418             if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1419                 break;
1420             i++;
1421         }
1422         dir = 1;
1423     }
1424
1425     lastval = i++;
1426     half_switch = 0;
1427     pmc = 0;
1428     block_done = 0;
1429
1430     for (bitidx = 0; i < GraphTraceLen; i++)
1431     {
1432         if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1433         {
1434             lc = i - lastval;
1435             lastval = i;
1436
1437             // Switch depending on lc length:
1438             // Tolerance is 1/8 of clock rate (arbitrary)
1439             if (abs(lc-clock/4) < tolerance) {
1440                 // 16T0
1441                 if((i - pmc) == lc) { /* 16T0 was previous one */
1442                     /* It's a PMC ! */
1443                     i += (128+127+16+32+33+16)-1;
1444                     lastval = i;
1445                     pmc = 0;
1446                     block_done = 1;
1447                 }
1448                 else {
1449                     pmc = i;
1450                 }
1451             } else if (abs(lc-clock/2) < tolerance) {
1452                 // 32TO
1453                 if((i - pmc) == lc) { /* 16T0 was previous one */
1454                     /* It's a PMC ! */
1455                     i += (128+127+16+32+33)-1;
1456                     lastval = i;
1457                     pmc = 0;
1458                     block_done = 1;
1459                 }
1460                 else if(half_switch == 1) {
1461                     BitStream[bitidx++] = 0;
1462                     half_switch = 0;
1463                 }
1464                 else
1465                     half_switch++;
1466             } else if (abs(lc-clock) < tolerance) {
1467                 // 64TO
1468                 BitStream[bitidx++] = 1;
1469             } else {
1470                 // Error
1471                 warnings++;
1472                 if (warnings > 10)
1473                 {
1474                     Dbprintf("Error: too many detection errors, aborting.");
1475                     return 0;
1476                 }
1477             }
1478
1479             if(block_done == 1) {
1480                 if(bitidx == 128) {
1481                     for(j=0; j<16; j++) {
1482                         Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1483                                 64*BitStream[j*8+6]+
1484                                 32*BitStream[j*8+5]+
1485                                 16*BitStream[j*8+4]+
1486                                 8*BitStream[j*8+3]+
1487                                 4*BitStream[j*8+2]+
1488                                 2*BitStream[j*8+1]+
1489                                 BitStream[j*8];
1490                     }
1491                     num_blocks++;
1492                 }
1493                 bitidx = 0;
1494                 block_done = 0;
1495                 half_switch = 0;
1496             }
1497             if(i < GraphTraceLen)
1498             {
1499                 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1500                 else dir = 1;
1501             }
1502         }
1503         if(bitidx==255)
1504             bitidx=0;
1505         warnings = 0;
1506         if(num_blocks == 4) break;
1507     }
1508     memcpy(outBlocks, Blocks, 16*num_blocks);
1509     return num_blocks;
1510 }
1511
1512 int IsBlock0PCF7931(uint8_t *Block) {
1513     // Assume RFU means 0 :)
1514     if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1515         return 1;
1516     if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1517         return 1;
1518     return 0;
1519 }
1520
1521 int IsBlock1PCF7931(uint8_t *Block) {
1522     // Assume RFU means 0 :)
1523     if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1524         if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1525             return 1;
1526
1527     return 0;
1528 }
1529
1530 #define ALLOC 16
1531
1532 void ReadPCF7931() {
1533     uint8_t Blocks[8][17];
1534     uint8_t tmpBlocks[4][16];
1535     int i, j, ind, ind2, n;
1536     int num_blocks = 0;
1537     int max_blocks = 8;
1538     int ident = 0;
1539     int error = 0;
1540     int tries = 0;
1541
1542     memset(Blocks, 0, 8*17*sizeof(uint8_t));
1543
1544     do {
1545         memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1546         n = DemodPCF7931((uint8_t**)tmpBlocks);
1547         if(!n)
1548             error++;
1549         if(error==10 && num_blocks == 0) {
1550             Dbprintf("Error, no tag or bad tag");
1551             return;
1552         }
1553         else if (tries==20 || error==10) {
1554             Dbprintf("Error reading the tag");
1555             Dbprintf("Here is the partial content");
1556             goto end;
1557         }
1558
1559         for(i=0; i<n; i++)
1560             Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1561                      tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1562                     tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1563         if(!ident) {
1564             for(i=0; i<n; i++) {
1565                 if(IsBlock0PCF7931(tmpBlocks[i])) {
1566                     // Found block 0 ?
1567                     if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1568                         // Found block 1!
1569                         // \o/
1570                         ident = 1;
1571                         memcpy(Blocks[0], tmpBlocks[i], 16);
1572                         Blocks[0][ALLOC] = 1;
1573                         memcpy(Blocks[1], tmpBlocks[i+1], 16);
1574                         Blocks[1][ALLOC] = 1;
1575                         max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1576                         // Debug print
1577                         Dbprintf("(dbg) Max blocks: %d", max_blocks);
1578                         num_blocks = 2;
1579                         // Handle following blocks
1580                         for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1581                             if(j==n) j=0;
1582                             if(j==i) break;
1583                             memcpy(Blocks[ind2], tmpBlocks[j], 16);
1584                             Blocks[ind2][ALLOC] = 1;
1585                         }
1586                         break;
1587                     }
1588                 }
1589             }
1590         }
1591         else {
1592             for(i=0; i<n; i++) { // Look for identical block in known blocks
1593                 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1594                     for(j=0; j<max_blocks; j++) {
1595                         if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1596                             // Found an identical block
1597                             for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1598                                 if(ind2 < 0)
1599                                     ind2 = max_blocks;
1600                                 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1601                                     // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1602                                     memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1603                                     Blocks[ind2][ALLOC] = 1;
1604                                     num_blocks++;
1605                                     if(num_blocks == max_blocks) goto end;
1606                                 }
1607                             }
1608                             for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1609                                 if(ind2 > max_blocks)
1610                                     ind2 = 0;
1611                                 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1612                                     // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1613                                     memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1614                                     Blocks[ind2][ALLOC] = 1;
1615                                     num_blocks++;
1616                                     if(num_blocks == max_blocks) goto end;
1617                                 }
1618                             }
1619                         }
1620                     }
1621                 }
1622             }
1623         }
1624         tries++;
1625         if (BUTTON_PRESS()) return;
1626     } while (num_blocks != max_blocks);
1627 end:
1628     Dbprintf("-----------------------------------------");
1629     Dbprintf("Memory content:");
1630     Dbprintf("-----------------------------------------");
1631     for(i=0; i<max_blocks; i++) {
1632         if(Blocks[i][ALLOC]==1)
1633             Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1634                      Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1635                     Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1636         else
1637             Dbprintf("<missing block %d>", i);
1638     }
1639     Dbprintf("-----------------------------------------");
1640
1641     return ;
1642 }
1643
1644
1645 //-----------------------------------
1646 // EM4469 / EM4305 routines
1647 //-----------------------------------
1648 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1649 #define FWD_CMD_WRITE 0xA
1650 #define FWD_CMD_READ 0x9
1651 #define FWD_CMD_DISABLE 0x5
1652
1653
1654 uint8_t forwardLink_data[64]; //array of forwarded bits
1655 uint8_t * forward_ptr; //ptr for forward message preparation
1656 uint8_t fwd_bit_sz; //forwardlink bit counter
1657 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1658
1659 //====================================================================
1660 // prepares command bits
1661 // see EM4469 spec
1662 //====================================================================
1663 //--------------------------------------------------------------------
1664 uint8_t Prepare_Cmd( uint8_t cmd ) {
1665     //--------------------------------------------------------------------
1666
1667     *forward_ptr++ = 0; //start bit
1668     *forward_ptr++ = 0; //second pause for 4050 code
1669
1670     *forward_ptr++ = cmd;
1671     cmd >>= 1;
1672     *forward_ptr++ = cmd;
1673     cmd >>= 1;
1674     *forward_ptr++ = cmd;
1675     cmd >>= 1;
1676     *forward_ptr++ = cmd;
1677
1678     return 6; //return number of emited bits
1679 }
1680
1681 //====================================================================
1682 // prepares address bits
1683 // see EM4469 spec
1684 //====================================================================
1685
1686 //--------------------------------------------------------------------
1687 uint8_t Prepare_Addr( uint8_t addr ) {
1688     //--------------------------------------------------------------------
1689
1690     register uint8_t line_parity;
1691
1692     uint8_t i;
1693     line_parity = 0;
1694     for(i=0;i<6;i++) {
1695         *forward_ptr++ = addr;
1696         line_parity ^= addr;
1697         addr >>= 1;
1698     }
1699
1700     *forward_ptr++ = (line_parity & 1);
1701
1702     return 7; //return number of emited bits
1703 }
1704
1705 //====================================================================
1706 // prepares data bits intreleaved with parity bits
1707 // see EM4469 spec
1708 //====================================================================
1709
1710 //--------------------------------------------------------------------
1711 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1712     //--------------------------------------------------------------------
1713
1714     register uint8_t line_parity;
1715     register uint8_t column_parity;
1716     register uint8_t i, j;
1717     register uint16_t data;
1718
1719     data = data_low;
1720     column_parity = 0;
1721
1722     for(i=0; i<4; i++) {
1723         line_parity = 0;
1724         for(j=0; j<8; j++) {
1725             line_parity ^= data;
1726             column_parity ^= (data & 1) << j;
1727             *forward_ptr++ = data;
1728             data >>= 1;
1729         }
1730         *forward_ptr++ = line_parity;
1731         if(i == 1)
1732             data = data_hi;
1733     }
1734
1735     for(j=0; j<8; j++) {
1736         *forward_ptr++ = column_parity;
1737         column_parity >>= 1;
1738     }
1739     *forward_ptr = 0;
1740
1741     return 45; //return number of emited bits
1742 }
1743
1744 //====================================================================
1745 // Forward Link send function
1746 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1747 // fwd_bit_count set with number of bits to be sent
1748 //====================================================================
1749 void SendForward(uint8_t fwd_bit_count) {
1750
1751     fwd_write_ptr = forwardLink_data;
1752     fwd_bit_sz = fwd_bit_count;
1753
1754     LED_D_ON();
1755
1756     //Field on
1757     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1758     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1759     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1760
1761     // Give it a bit of time for the resonant antenna to settle.
1762     // And for the tag to fully power up
1763     SpinDelay(150);
1764
1765     // force 1st mod pulse (start gap must be longer for 4305)
1766     fwd_bit_sz--; //prepare next bit modulation
1767     fwd_write_ptr++;
1768     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1769     SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1770     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1771     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1772     SpinDelayUs(16*8); //16 cycles on (8us each)
1773
1774     // now start writting
1775     while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1776         if(((*fwd_write_ptr++) & 1) == 1)
1777             SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1778         else {
1779             //These timings work for 4469/4269/4305 (with the 55*8 above)
1780             FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1781             SpinDelayUs(23*8); //16-4 cycles off (8us each)
1782             FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1783             FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1784             SpinDelayUs(9*8); //16 cycles on (8us each)
1785         }
1786     }
1787 }
1788
1789 void EM4xLogin(uint32_t Password) {
1790
1791     uint8_t fwd_bit_count;
1792
1793     forward_ptr = forwardLink_data;
1794     fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1795     fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1796
1797     SendForward(fwd_bit_count);
1798
1799     //Wait for command to complete
1800     SpinDelay(20);
1801
1802 }
1803
1804 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1805
1806     uint8_t fwd_bit_count;
1807     uint8_t *dest = (uint8_t *)BigBuf;
1808     int m=0, i=0;
1809
1810     //If password mode do login
1811     if (PwdMode == 1) EM4xLogin(Pwd);
1812
1813     forward_ptr = forwardLink_data;
1814     fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1815     fwd_bit_count += Prepare_Addr( Address );
1816
1817     m = sizeof(BigBuf);
1818     // Clear destination buffer before sending the command
1819     memset(dest, 128, m);
1820     // Connect the A/D to the peak-detected low-frequency path.
1821     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1822     // Now set up the SSC to get the ADC samples that are now streaming at us.
1823     FpgaSetupSsc();
1824
1825     SendForward(fwd_bit_count);
1826
1827     // Now do the acquisition
1828     i = 0;
1829     for(;;) {
1830         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1831             AT91C_BASE_SSC->SSC_THR = 0x43;
1832         }
1833         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1834             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1835             i++;
1836             if (i >= m) break;
1837         }
1838     }
1839     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1840     LED_D_OFF();
1841 }
1842
1843 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1844
1845     uint8_t fwd_bit_count;
1846
1847     //If password mode do login
1848     if (PwdMode == 1) EM4xLogin(Pwd);
1849
1850     forward_ptr = forwardLink_data;
1851     fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1852     fwd_bit_count += Prepare_Addr( Address );
1853     fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1854
1855     SendForward(fwd_bit_count);
1856
1857     //Wait for write to complete
1858     SpinDelay(20);
1859     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1860     LED_D_OFF();
1861 }