afb49c3c791df9ac1214cbef5a554f8c5505d5f2
[proxmark3-svn] / bootrom / bootrom.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Main code for the bootloader
7 //-----------------------------------------------------------------------------
8
9 #include <proxmark3.h>
10 #include "usb_cdc.h"
11 #include "cmd.h"
12 //#include "usb_hid.h"
13
14 void DbpString(char *str) {
15 byte_t len = 0;
16 while (str[len] != 0x00) {
17 len++;
18 }
19 cmd_send(CMD_DEBUG_PRINT_STRING,len,0,0,(byte_t*)str,len);
20 }
21
22 struct common_area common_area __attribute__((section(".commonarea")));
23 unsigned int start_addr, end_addr, bootrom_unlocked;
24 extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
25
26 static void ConfigClocks(void)
27 {
28 // we are using a 16 MHz crystal as the basis for everything
29 // slow clock runs at 32Khz typical regardless of crystal
30
31 // enable system clock and USB clock
32 AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;
33
34 // enable the clock to the following peripherals
35 AT91C_BASE_PMC->PMC_PCER =
36 (1<<AT91C_ID_PIOA) |
37 (1<<AT91C_ID_ADC) |
38 (1<<AT91C_ID_SPI) |
39 (1<<AT91C_ID_SSC) |
40 (1<<AT91C_ID_PWMC) |
41 (1<<AT91C_ID_UDP);
42
43 // worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
44 // if SLCK slow clock runs at its worst case (max) frequency of 42khz
45 // max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
46
47 // enable main oscillator and set startup delay
48 AT91C_BASE_PMC->PMC_MOR =
49 AT91C_CKGR_MOSCEN |
50 PMC_MAIN_OSC_STARTUP_DELAY(8);
51
52 // wait for main oscillator to stabilize
53 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
54 ;
55
56 // PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
57 // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
58 // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
59 AT91C_BASE_PMC->PMC_PLLR =
60 PMC_PLL_DIVISOR(2) |
61 PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
62 PMC_PLL_FREQUENCY_RANGE(0) |
63 PMC_PLL_MULTIPLIER(12) |
64 PMC_PLL_USB_DIVISOR(1);
65
66 // wait for PLL to lock
67 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
68 ;
69
70 // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
71 // datasheet recommends that this register is programmed in two operations
72 // when changing to PLL, program the prescaler first then the source
73 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
74
75 // wait for main clock ready signal
76 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
77 ;
78
79 // set the source to PLL
80 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
81
82 // wait for main clock ready signal
83 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
84 ;
85 }
86
87 static void Fatal(void)
88 {
89 LED_D_OFF();
90 LED_C_OFF();
91 LED_B_OFF();
92 LED_A_OFF();
93 for(;;);
94 }
95
96 void UsbPacketReceived(uint8_t *packet, int len) {
97 int i, dont_ack=0;
98 UsbCommand* c = (UsbCommand *)packet;
99 volatile uint32_t *p;
100
101 if(len != sizeof(UsbCommand)) {
102 Fatal();
103 }
104
105 uint32_t arg0 = (uint32_t)c->arg[0];
106
107 switch(c->cmd) {
108 case CMD_DEVICE_INFO: {
109 dont_ack = 1;
110 // c->cmd = CMD_DEVICE_INFO;
111 arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
112 DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
113 if(common_area.flags.osimage_present) {
114 arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
115 }
116 // UsbSendPacket(packet, len);
117 cmd_send(CMD_DEVICE_INFO,arg0,1,2,0,0);
118 } break;
119
120 case CMD_SETUP_WRITE: {
121 /* The temporary write buffer of the embedded flash controller is mapped to the
122 * whole memory region, only the last 8 bits are decoded.
123 */
124 p = (volatile uint32_t *)&_flash_start;
125 for(i = 0; i < 12; i++) {
126 p[i+arg0] = c->d.asDwords[i];
127 }
128 } break;
129
130 case CMD_FINISH_WRITE: {
131 uint32_t* flash_mem = (uint32_t*)(&_flash_start);
132 // p = (volatile uint32_t *)&_flash_start;
133 for (size_t j=0; j<2; j++) {
134 for(i = 0+(64*j); i < 64+(64*j); i++) {
135 //p[i+60] = c->d.asDwords[i];
136 flash_mem[i] = c->d.asDwords[i];
137 }
138
139 uint32_t flash_address = arg0 + (0x100*j);
140
141 /* Check that the address that we are supposed to write to is within our allowed region */
142 if( ((flash_address+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (flash_address < start_addr) ) {
143 /* Disallow write */
144 dont_ack = 1;
145 // c->cmd = CMD_NACK;
146 // UsbSendPacket(packet, len);
147 cmd_send(CMD_NACK,0,0,0,0,0);
148 } else {
149 uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
150 /* Translate address to flash page and do flash, update here for the 512k part */
151 AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
152 MC_FLASH_COMMAND_PAGEN(page_n) |
153 AT91C_MC_FCMD_START_PROG;
154 // arg0 = (address - ((uint32_t)flash_s));
155 }
156
157 // Wait until flashing of page finishes
158 uint32_t sr;
159 while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
160 if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
161 dont_ack = 1;
162 // c->cmd = CMD_NACK;
163 cmd_send(CMD_NACK,0,0,0,0,0);
164 // UsbSendPacket(packet, len);
165 }
166 }
167 } break;
168
169 case CMD_HARDWARE_RESET: {
170 // USB_D_PLUS_PULLUP_OFF();
171 usb_disable();
172 AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
173 } break;
174
175 case CMD_START_FLASH: {
176 if(c->arg[2] == START_FLASH_MAGIC) bootrom_unlocked = 1;
177 else bootrom_unlocked = 0;
178 {
179 int prot_start = (int)&_bootrom_start;
180 int prot_end = (int)&_bootrom_end;
181 int allow_start = (int)&_flash_start;
182 int allow_end = (int)&_flash_end;
183 int cmd_start = c->arg[0];
184 int cmd_end = c->arg[1];
185
186 /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
187 * bootrom area. In any case they must be within the flash area.
188 */
189 if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))
190 && (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
191 start_addr = cmd_start;
192 end_addr = cmd_end;
193 } else {
194 start_addr = end_addr = 0;
195 dont_ack = 1;
196 // c->cmd = CMD_NACK;
197 // UsbSendPacket(packet, len);
198 cmd_send(CMD_NACK,0,0,0,0,0);
199 }
200 }
201 } break;
202
203 default: {
204 Fatal();
205 } break;
206 }
207
208 if(!dont_ack) {
209 // c->cmd = CMD_ACK;
210 // UsbSendPacket(packet, len);
211 cmd_send(CMD_ACK,arg0,0,0,0,0);
212 }
213 }
214
215 static void flash_mode(int externally_entered)
216 {
217 start_addr = 0;
218 end_addr = 0;
219 bootrom_unlocked = 0;
220 byte_t rx[sizeof(UsbCommand)];
221 size_t rx_len;
222
223 usb_enable();
224 for (volatile size_t i=0; i<0x100000; i++);
225 LED_D_ON();
226 LED_C_ON();
227 LED_B_ON();
228 LED_A_ON();
229
230 // UsbStart();
231 for(;;) {
232 WDT_HIT();
233
234 if (usb_poll()) {
235 rx_len = usb_read(rx,sizeof(UsbCommand));
236 if (rx_len) {
237 // DbpString("starting to flash");
238 UsbPacketReceived(rx,rx_len);
239 }
240 }
241
242 // UsbPoll(TRUE);
243
244 if(!externally_entered && !BUTTON_PRESS()) {
245 /* Perform a reset to leave flash mode */
246 // USB_D_PLUS_PULLUP_OFF();
247 usb_disable();
248 LED_B_ON();
249 AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
250 for(;;);
251 }
252 if(externally_entered && BUTTON_PRESS()) {
253 /* Let the user's button press override the automatic leave */
254 externally_entered = 0;
255 }
256 }
257 }
258
259 extern uint32_t _osimage_entry;
260 void BootROM(void)
261 {
262 //------------
263 // First set up all the I/O pins; GPIOs configured directly, other ones
264 // just need to be assigned to the appropriate peripheral.
265
266 // Kill all the pullups, especially the one on USB D+; leave them for
267 // the unused pins, though.
268 AT91C_BASE_PIOA->PIO_PPUDR =
269 GPIO_USB_PU |
270 GPIO_LED_A |
271 GPIO_LED_B |
272 GPIO_LED_C |
273 GPIO_LED_D |
274 GPIO_FPGA_DIN |
275 GPIO_FPGA_DOUT |
276 GPIO_FPGA_CCLK |
277 GPIO_FPGA_NINIT |
278 GPIO_FPGA_NPROGRAM |
279 GPIO_FPGA_DONE |
280 GPIO_MUXSEL_HIPKD |
281 GPIO_MUXSEL_HIRAW |
282 GPIO_MUXSEL_LOPKD |
283 GPIO_MUXSEL_LORAW |
284 GPIO_RELAY |
285 GPIO_NVDD_ON;
286 // (and add GPIO_FPGA_ON)
287 // These pins are outputs
288 AT91C_BASE_PIOA->PIO_OER =
289 GPIO_LED_A |
290 GPIO_LED_B |
291 GPIO_LED_C |
292 GPIO_LED_D |
293 GPIO_RELAY |
294 GPIO_NVDD_ON;
295 // PIO controls the following pins
296 AT91C_BASE_PIOA->PIO_PER =
297 GPIO_USB_PU |
298 GPIO_LED_A |
299 GPIO_LED_B |
300 GPIO_LED_C |
301 GPIO_LED_D;
302
303 // USB_D_PLUS_PULLUP_OFF();
304 usb_disable();
305 LED_D_OFF();
306 LED_C_ON();
307 LED_B_OFF();
308 LED_A_OFF();
309
310 AT91C_BASE_EFC0->EFC_FMR =
311 AT91C_MC_FWS_1FWS |
312 MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
313
314 // Initialize all system clocks
315 ConfigClocks();
316
317 LED_A_ON();
318
319 int common_area_present = 0;
320 switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
321 case AT91C_RSTC_RSTTYP_WATCHDOG:
322 case AT91C_RSTC_RSTTYP_SOFTWARE:
323 case AT91C_RSTC_RSTTYP_USER:
324 /* In these cases the common_area in RAM should be ok, retain it if it's there */
325 if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
326 common_area_present = 1;
327 }
328 break;
329 default: /* Otherwise, initialize it from scratch */
330 break;
331 }
332
333 if(!common_area_present){
334 /* Common area not ok, initialize it */
335 int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
336 ((char*)&common_area)[i] = 0;
337 }
338 common_area.magic = COMMON_AREA_MAGIC;
339 common_area.version = 1;
340 common_area.flags.bootrom_present = 1;
341 }
342
343 common_area.flags.bootrom_present = 1;
344 if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
345 common_area.command = COMMON_AREA_COMMAND_NONE;
346 flash_mode(1);
347 } else if(BUTTON_PRESS()) {
348 flash_mode(0);
349 } else if(_osimage_entry == 0xffffffffU) {
350 flash_mode(1);
351 } else {
352 // jump to Flash address of the osimage entry point (LSBit set for thumb mode)
353 __asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
354 }
355 }
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