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1 //-----------------------------------------------------------------------------
2 // The way that we connect things in low-frequency read mode. In this case
3 // we are generating the unmodulated low frequency carrier.
4 // The A/D samples at that same rate and the result is serialized.
5 //
6 // Jonathan Westhues, April 2006
7 // iZsh <izsh at fail0verflow.com>, June 2014
8 //-----------------------------------------------------------------------------
9
10 module lo_read(
11 input pck0, input [7:0] pck_cnt, input pck_divclk,
12 output pwr_lo, output pwr_hi,
13 output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
14 input [7:0] adc_d, output adc_clk,
15 output ssp_frame, output ssp_din, output ssp_clk,
16 output dbg
17 );
18
19 reg [7:0] to_arm_shiftreg;
20
21 // this task also runs at pck0 frequency (24Mhz) and is used to serialize
22 // the ADC output which is then clocked into the ARM SSP.
23
24 // because pck_divclk always transitions when pck_cnt = 0 we use the
25 // pck_div counter to sync our other signals off it
26 // we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
27 always @(posedge pck0)
28 begin
29 if((pck_cnt == 8'd7) && !pck_divclk)
30 to_arm_shiftreg <= adc_d;
31 else begin
32 to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
33 // simulation showed a glitch occuring due to the LSB of the shifter
34 // not being set as we shift bits out
35 // this ensures the ssp_din remains low after a transfer and suppresses
36 // the glitch that would occur when the last data shifted out ended in
37 // a 1 bit and the next data shifted out started with a 0 bit
38 to_arm_shiftreg[0] <= 1'b0;
39 end
40 end
41
42 // ADC samples on falling edge of adc_clk, data available on the rising edge
43
44 // example of ssp transfer of binary value 1100101
45 // start of transfer is indicated by the rise of the ssp_frame signal
46 // ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
47 // the ARM by the falling edge of ssp_clk
48 // _______________________________
49 // ssp_frame__| |__
50 // _______ ___ ___
51 // ssp_din __| |_______| |___| |______
52 // _ _ _ _ _ _ _ _ _ _
53 // ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
54
55 // serialized SSP data is gated by ant_lo to suppress unwanted signal
56 assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
57 // SSP clock always runs at 24Mhz
58 assign ssp_clk = pck0;
59 // SSP frame is gated by ant_lo and goes high when pck_divider=8..15
60 assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
61 // unused signals tied low
62 assign pwr_hi = 1'b0;
63 assign pwr_oe1 = 1'b0;
64 assign pwr_oe2 = 1'b0;
65 assign pwr_oe3 = 1'b0;
66 assign pwr_oe4 = 1'b0;
67 // this is the antenna driver signal
68 assign pwr_lo = pck_divclk;
69 // ADC clock out of phase with antenna driver
70 assign adc_clk = ~pck_divclk;
71 // ADC clock also routed to debug pin
72 assign dbg = adc_clk;
73 endmodule
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