modify USB communications
[proxmark3-svn] / bootrom / bootrom.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Main code for the bootloader
7 //-----------------------------------------------------------------------------
8
9 #include "proxmark3.h"
10 #include "usb_cdc.h"
11
12 void DbpString(char *str) {
13 uint8_t len = 0;
14 while (str[len] != 0x00) {
15 len++;
16 }
17 cmd_send_old(CMD_DEBUG_PRINT_STRING,len,0,0,(uint8_t*)str,len);
18 }
19
20 struct common_area common_area __attribute__((section(".commonarea")));
21 unsigned int start_addr, end_addr, bootrom_unlocked;
22 extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
23
24 static void ConfigClocks(void)
25 {
26 // we are using a 16 MHz crystal as the basis for everything
27 // slow clock runs at 32Khz typical regardless of crystal
28
29 // enable system clock and USB clock
30 AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;
31
32 // enable the clock to the following peripherals
33 AT91C_BASE_PMC->PMC_PCER =
34 (1<<AT91C_ID_PIOA) |
35 (1<<AT91C_ID_ADC) |
36 (1<<AT91C_ID_SPI) |
37 (1<<AT91C_ID_SSC) |
38 (1<<AT91C_ID_PWMC) |
39 (1<<AT91C_ID_UDP);
40
41 // worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
42 // if SLCK slow clock runs at its worst case (max) frequency of 42khz
43 // max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
44
45 // enable main oscillator and set startup delay
46 AT91C_BASE_PMC->PMC_MOR =
47 AT91C_CKGR_MOSCEN |
48 PMC_MAIN_OSC_STARTUP_DELAY(8);
49
50 // wait for main oscillator to stabilize
51 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
52 ;
53
54 // PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
55 // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
56 // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
57 AT91C_BASE_PMC->PMC_PLLR =
58 PMC_PLL_DIVISOR(2) |
59 PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
60 PMC_PLL_FREQUENCY_RANGE(0) |
61 PMC_PLL_MULTIPLIER(12) |
62 PMC_PLL_USB_DIVISOR(1);
63
64 // wait for PLL to lock
65 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
66 ;
67
68 // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
69 // datasheet recommends that this register is programmed in two operations
70 // when changing to PLL, program the prescaler first then the source
71 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
72
73 // wait for main clock ready signal
74 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
75 ;
76
77 // set the source to PLL
78 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
79
80 // wait for main clock ready signal
81 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
82 ;
83 }
84
85 static void Fatal(void)
86 {
87 for(;;);
88 }
89
90 void UsbPacketReceived(UsbCommand *c) {
91 int i, dont_ack=0;
92 volatile uint32_t *p;
93
94 uint32_t arg0 = (uint32_t)c->arg[0];
95
96 switch(c->cmd) {
97 case CMD_DEVICE_INFO: {
98 dont_ack = 1;
99 arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT
100 | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM
101 | DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
102 if(common_area.flags.osimage_present) {
103 arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
104 }
105 cmd_send_old(CMD_DEVICE_INFO,arg0,1,2,0,0);
106 } break;
107
108 case CMD_SETUP_WRITE: {
109 /* The temporary write buffer of the embedded flash controller is mapped to the
110 * whole memory region, only the last 8 bits are decoded.
111 */
112 p = (volatile uint32_t *)&_flash_start;
113 for(i = 0; i < 12; i++) {
114 p[i+arg0] = c->d.asDwords[i];
115 }
116 } break;
117
118 case CMD_FINISH_WRITE: {
119 uint32_t* flash_mem = (uint32_t*)(&_flash_start);
120 for (size_t j=0; j<2; j++) {
121 for(i = 0+(64*j); i < 64+(64*j); i++) {
122 flash_mem[i] = c->d.asDwords[i];
123 }
124
125 uint32_t flash_address = arg0 + (0x100*j);
126
127 /* Check that the address that we are supposed to write to is within our allowed region */
128 if( ((flash_address+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (flash_address < start_addr) ) {
129 /* Disallow write */
130 dont_ack = 1;
131 cmd_send_old(CMD_NACK,0,0,0,0,0);
132 } else {
133 uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
134 /* Translate address to flash page and do flash, update here for the 512k part */
135 AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
136 MC_FLASH_COMMAND_PAGEN(page_n) |
137 AT91C_MC_FCMD_START_PROG;
138 }
139
140 // Wait until flashing of page finishes
141 uint32_t sr;
142 while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
143 if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
144 dont_ack = 1;
145 cmd_send_old(CMD_NACK,0,0,0,0,0);
146 }
147 }
148 } break;
149
150 case CMD_HARDWARE_RESET: {
151 usb_disable();
152 AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
153 } break;
154
155 case CMD_START_FLASH: {
156 if(c->arg[2] == START_FLASH_MAGIC) bootrom_unlocked = 1;
157 else bootrom_unlocked = 0;
158 {
159 int prot_start = (int)&_bootrom_start;
160 int prot_end = (int)&_bootrom_end;
161 int allow_start = (int)&_flash_start;
162 int allow_end = (int)&_flash_end;
163 int cmd_start = c->arg[0];
164 int cmd_end = c->arg[1];
165
166 /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
167 * bootrom area. In any case they must be within the flash area.
168 */
169 if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))
170 && (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
171 start_addr = cmd_start;
172 end_addr = cmd_end;
173 } else {
174 start_addr = end_addr = 0;
175 dont_ack = 1;
176 cmd_send_old(CMD_NACK,0,0,0,0,0);
177 }
178 }
179 } break;
180
181 default: {
182 Fatal();
183 } break;
184 }
185
186 if(!dont_ack) {
187 cmd_send_old(CMD_ACK,arg0,0,0,0,0);
188 }
189 }
190
191 static void flash_mode(int externally_entered)
192 {
193 start_addr = 0;
194 end_addr = 0;
195 bootrom_unlocked = 0;
196 UsbCommand rx;
197
198 usb_enable();
199 for (volatile size_t i=0; i<0x100000; i++) {};
200
201 for(;;) {
202 WDT_HIT();
203
204 if (cmd_receive(&rx)) {
205 UsbPacketReceived(&rx);
206 }
207
208 if(!externally_entered && !BUTTON_PRESS()) {
209 /* Perform a reset to leave flash mode */
210 usb_disable();
211 LED_B_ON();
212 AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
213 for(;;);
214 }
215 if(externally_entered && BUTTON_PRESS()) {
216 /* Let the user's button press override the automatic leave */
217 externally_entered = 0;
218 }
219 }
220 }
221
222 extern uint32_t _osimage_entry;
223 void BootROM(void)
224 {
225 //------------
226 // First set up all the I/O pins; GPIOs configured directly, other ones
227 // just need to be assigned to the appropriate peripheral.
228
229 // Kill all the pullups, especially the one on USB D+; leave them for
230 // the unused pins, though.
231 AT91C_BASE_PIOA->PIO_PPUDR =
232 GPIO_USB_PU |
233 GPIO_LED_A |
234 GPIO_LED_B |
235 GPIO_LED_C |
236 GPIO_LED_D |
237 GPIO_FPGA_DIN |
238 GPIO_FPGA_DOUT |
239 GPIO_FPGA_CCLK |
240 GPIO_FPGA_NINIT |
241 GPIO_FPGA_NPROGRAM |
242 GPIO_FPGA_DONE |
243 GPIO_MUXSEL_HIPKD |
244 GPIO_MUXSEL_HIRAW |
245 GPIO_MUXSEL_LOPKD |
246 GPIO_MUXSEL_LORAW |
247 GPIO_RELAY |
248 GPIO_NVDD_ON;
249 // (and add GPIO_FPGA_ON)
250 // These pins are outputs
251 AT91C_BASE_PIOA->PIO_OER =
252 GPIO_LED_A |
253 GPIO_LED_B |
254 GPIO_LED_C |
255 GPIO_LED_D |
256 GPIO_RELAY |
257 GPIO_NVDD_ON;
258 // PIO controls the following pins
259 AT91C_BASE_PIOA->PIO_PER =
260 GPIO_USB_PU |
261 GPIO_LED_A |
262 GPIO_LED_B |
263 GPIO_LED_C |
264 GPIO_LED_D;
265
266 // USB_D_PLUS_PULLUP_OFF();
267 usb_disable();
268 LED_D_OFF();
269 LED_C_ON();
270 LED_B_OFF();
271 LED_A_OFF();
272
273 AT91C_BASE_EFC0->EFC_FMR =
274 AT91C_MC_FWS_1FWS |
275 MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
276
277 // Initialize all system clocks
278 ConfigClocks();
279
280 LED_A_ON();
281
282 int common_area_present = 0;
283 switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
284 case AT91C_RSTC_RSTTYP_WATCHDOG:
285 case AT91C_RSTC_RSTTYP_SOFTWARE:
286 case AT91C_RSTC_RSTTYP_USER:
287 /* In these cases the common_area in RAM should be ok, retain it if it's there */
288 if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
289 common_area_present = 1;
290 }
291 break;
292 default: /* Otherwise, initialize it from scratch */
293 break;
294 }
295
296 if(!common_area_present){
297 /* Common area not ok, initialize it */
298 int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
299 ((char*)&common_area)[i] = 0;
300 }
301 common_area.magic = COMMON_AREA_MAGIC;
302 common_area.version = 1;
303 common_area.flags.bootrom_present = 1;
304 }
305
306 common_area.flags.bootrom_present = 1;
307 if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
308 common_area.command = COMMON_AREA_COMMAND_NONE;
309 flash_mode(1);
310 } else if(BUTTON_PRESS()) {
311 flash_mode(0);
312 } else if(_osimage_entry == 0xffffffffU) {
313 flash_mode(1);
314 } else {
315 // jump to Flash address of the osimage entry point (LSBit set for thumb mode)
316 __asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
317 }
318 }
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