FPGA changes ISO14443B:
[proxmark3-svn] / fpga / hi_read_rx_xcorr.v
1 //-----------------------------------------------------------------------------
2 //
3 // Jonathan Westhues, April 2006
4 //-----------------------------------------------------------------------------
5
6 module hi_read_rx_xcorr(
7 pck0, ck_1356meg, ck_1356megb,
8 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
9 adc_d, adc_clk,
10 ssp_frame, ssp_din, ssp_dout, ssp_clk,
11 cross_hi, cross_lo,
12 dbg,
13 xcorr_is_848, snoop, xcorr_quarter_freq
14 );
15 input pck0, ck_1356meg, ck_1356megb;
16 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
17 input [7:0] adc_d;
18 output adc_clk;
19 input ssp_dout;
20 output ssp_frame, ssp_din, ssp_clk;
21 input cross_hi, cross_lo;
22 output dbg;
23 input xcorr_is_848, snoop, xcorr_quarter_freq;
24
25 // Carrier is steady on through this, unless we're snooping.
26 assign pwr_hi = ck_1356megb & (~snoop);
27 assign pwr_oe1 = 1'b0;
28 assign pwr_oe3 = 1'b0;
29 assign pwr_oe4 = 1'b0;
30
31 reg [2:0] fc_div;
32 always @(negedge ck_1356megb)
33 fc_div <= fc_div + 1;
34
35 (* clock_signal = "yes" *) reg adc_clk; // sample frequency, always 16 * fc
36 always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
37 if (xcorr_is_848 & ~xcorr_quarter_freq) // fc = 847.5 kHz, standard ISO14443B
38 adc_clk <= ck_1356megb;
39 else if (~xcorr_is_848 & ~xcorr_quarter_freq) // fc = 423.75 kHz
40 adc_clk <= fc_div[0];
41 else if (xcorr_is_848 & xcorr_quarter_freq) // fc = 211.875 kHz
42 adc_clk <= fc_div[1];
43 else // fc = 105.9375 kHz
44 adc_clk <= fc_div[2];
45
46 // When we're a reader, we just need to do the BPSK demod; but when we're an
47 // eavesdropper, we also need to pick out the commands sent by the reader,
48 // using AM. Do this the same way that we do it for the simulated tag.
49 reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
50 reg [11:0] has_been_low_for;
51 always @(negedge adc_clk)
52 begin
53 if(& adc_d[7:0]) after_hysteresis <= 1'b1;
54 else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
55
56 if(after_hysteresis)
57 begin
58 has_been_low_for <= 7'b0;
59 end
60 else
61 begin
62 if(has_been_low_for == 12'd4095)
63 begin
64 has_been_low_for <= 12'd0;
65 after_hysteresis <= 1'b1;
66 end
67 else
68 has_been_low_for <= has_been_low_for + 1;
69 end
70 end
71
72 // Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,
73 // so we need a 6-bit counter.
74 reg [5:0] corr_i_cnt;
75 // And a couple of registers in which to accumulate the correlations.
76 // We would add at most 32 times the difference between unmodulated and modulated signal. It should
77 // be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
78 // 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
79 reg signed [11:0] corr_i_accum;
80 reg signed [11:0] corr_q_accum;
81 // we will report maximum 8 significant bits
82 reg signed [7:0] corr_i_out;
83 reg signed [7:0] corr_q_out;
84 // clock and frame signal for communication to ARM
85 reg ssp_clk;
86 reg ssp_frame;
87
88
89 always @(negedge adc_clk)
90 begin
91 corr_i_cnt <= corr_i_cnt + 1;
92 end
93
94
95 // ADC data appears on the rising edge, so sample it on the falling edge
96 always @(negedge adc_clk)
97 begin
98 // These are the correlators: we correlate against in-phase and quadrature
99 // versions of our reference signal, and keep the (signed) result to
100 // send out later over the SSP.
101 if(corr_i_cnt == 6'd0)
102 begin
103 if(snoop)
104 begin
105 // Send 7 most significant bits of tag signal (signed), plus 1 bit reader signal
106 corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
107 corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
108 after_hysteresis_prev_prev <= after_hysteresis;
109 end
110 else
111 begin
112 // 8 bits of tag signal
113 corr_i_out <= corr_i_accum[11:4];
114 corr_q_out <= corr_q_accum[11:4];
115 end
116
117 corr_i_accum <= adc_d;
118 corr_q_accum <= adc_d;
119 end
120 else
121 begin
122 if(corr_i_cnt[3])
123 corr_i_accum <= corr_i_accum - adc_d;
124 else
125 corr_i_accum <= corr_i_accum + adc_d;
126
127 if(corr_i_cnt[3] == corr_i_cnt[2]) // phase shifted by pi/2
128 corr_q_accum <= corr_q_accum + adc_d;
129 else
130 corr_q_accum <= corr_q_accum - adc_d;
131
132 end
133
134 // The logic in hi_simulate.v reports 4 samples per bit. We report two
135 // (I, Q) pairs per bit, so we should do 2 samples per pair.
136 if(corr_i_cnt == 6'd32)
137 after_hysteresis_prev <= after_hysteresis;
138
139 // Then the result from last time is serialized and send out to the ARM.
140 // We get one report each cycle, and each report is 16 bits, so the
141 // ssp_clk should be the adc_clk divided by 64/16 = 4.
142
143 if(corr_i_cnt[1:0] == 2'b10)
144 ssp_clk <= 1'b0;
145
146 if(corr_i_cnt[1:0] == 2'b00)
147 begin
148 ssp_clk <= 1'b1;
149 // Don't shift if we just loaded new data, obviously.
150 if(corr_i_cnt != 6'd0)
151 begin
152 corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
153 corr_q_out[7:1] <= corr_q_out[6:0];
154 end
155 end
156
157 // set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
158 // (send two frames with 8 Bits each)
159 if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
160 ssp_frame = 1'b1;
161 else
162 ssp_frame = 1'b0;
163
164 end
165
166 assign ssp_din = corr_i_out[7];
167
168 assign dbg = corr_i_cnt[3];
169
170 // Unused.
171 assign pwr_lo = 1'b0;
172 assign pwr_oe2 = 1'b0;
173
174 endmodule
Impressum, Datenschutz