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FIX: lf hitag : Mea culpa, simulation should not have reader_field on. thanks to...
[proxmark3-svn] / armsrc / hitagS.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // HitagS emulation (preliminary test version)
7 //
8 // (c) 2016 Oguzhan Cicek, Hendrik Schwartke, Ralf Spenneberg
9 // <info@os-s.de>
10 //-----------------------------------------------------------------------------
11 // Some code was copied from Hitag2.c
12 //-----------------------------------------------------------------------------
13 #include <stdlib.h>
14 #include "proxmark3.h"
15 #include "apps.h"
16 #include "util.h"
17 #include "hitagS.h"
18 #include "hitag2.h"
19 #include "string.h"
20 #include "BigBuf.h"
21
22 #define CRC_PRESET 0xFF
23 #define CRC_POLYNOM 0x1D
24
25 #define u8 uint8_t
26 #define u32 uint32_t
27 #define u64 uint64_t
28 #define rev8(x) ((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7))
29 #define rev16(x) (rev8 (x)+(rev8 (x>> 8)<< 8))
30 #define rev32(x) (rev16(x)+(rev16(x>>16)<<16))
31 #define rev64(x) (rev32(x)+(rev32(x>>32)<<32))
32 #define bit(x,n) (((x)>>(n))&1)
33 #define bit32(x,n) ((((x)[(n)>>5])>>((n)))&1)
34 #define inv32(x,i,n) ((x)[(i)>>5]^=((u32)(n))<<((i)&31))
35 #define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))
36
37 static bool bQuiet;
38 static bool bSuccessful;
39 static struct hitagS_tag tag;
40 static byte_t page_to_be_written = 0;
41 static int block_data_left = 0;
42 typedef enum modulation {
43 AC2K = 0,
44 AC4K,
45 MC4K,
46 MC8K
47 } MOD;
48 static MOD m = AC2K; //used modulation
49 static uint32_t temp_uid;
50 static int temp2 = 0;
51 static int sof_bits; //number of start-of-frame bits
52 static byte_t pwdh0, pwdl0, pwdl1; //password bytes
53 static uint32_t rnd = 0x74124485; //randomnumber
54 static int test = 0;
55 size_t blocknr;
56 bool end=false;
57
58 // Single bit Hitag2 functions:
59 #define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))
60 static const u32 ht2_f4a = 0x2C79; // 0010 1100 0111 1001
61 static const u32 ht2_f4b = 0x6671; // 0110 0110 0111 0001
62 static const u32 ht2_f5c = 0x7907287B; // 0111 1001 0000 0111 0010 1000 0111 1011
63 #define ht2bs_4a(a,b,c,d) (~(((a|b)&c)^(a|d)^b))
64 #define ht2bs_4b(a,b,c,d) (~(((d|c)&(a^b))^(d|a|b)))
65 #define ht2bs_5c(a,b,c,d,e) (~((((((c^e)|d)&a)^b)&(c^b))^(((d^e)|a)&((d^b)|c))))
66 #define uf20bs u32
67
68 static u32 f20(const u64 x) {
69 u32 i5;
70
71 i5 = ((ht2_f4a >> i4(x, 1, 2, 4, 5)) & 1) * 1
72 + ((ht2_f4b >> i4(x, 7, 11, 13, 14)) & 1) * 2
73 + ((ht2_f4b >> i4(x, 16, 20, 22, 25)) & 1) * 4
74 + ((ht2_f4b >> i4(x, 27, 28, 30, 32)) & 1) * 8
75 + ((ht2_f4a >> i4(x, 33, 42, 43, 45)) & 1) * 16;
76
77 return (ht2_f5c >> i5) & 1;
78 }
79 static u64 hitag2_round(u64 *state) {
80 u64 x = *state;
81
82 x = (x >> 1)
83 + ((((x >> 0) ^ (x >> 2) ^ (x >> 3) ^ (x >> 6) ^ (x >> 7) ^ (x >> 8)
84 ^ (x >> 16) ^ (x >> 22) ^ (x >> 23) ^ (x >> 26) ^ (x >> 30)
85 ^ (x >> 41) ^ (x >> 42) ^ (x >> 43) ^ (x >> 46) ^ (x >> 47))
86 & 1) << 47);
87
88 *state = x;
89 return f20(x);
90 }
91 static u64 hitag2_init(const u64 key, const u32 serial, const u32 IV) {
92 u32 i;
93 u64 x = ((key & 0xFFFF) << 32) + serial;
94 for (i = 0; i < 32; i++) {
95 x >>= 1;
96 x += (u64) (f20(x) ^ (((IV >> i) ^ (key >> (i + 16))) & 1)) << 47;
97 }
98 return x;
99 }
100 static u32 hitag2_byte(u64 *x) {
101 u32 i, c;
102
103 for (i = 0, c = 0; i < 8; i++)
104 c += (u32) hitag2_round(x) << (i ^ 7);
105 return c;
106 }
107
108 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
109 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
110 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
111 // T0 = TIMER_CLOCK1 / 125000 = 192
112 #define T0 192
113
114 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
115 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
116
117 #define HITAG_FRAME_LEN 20
118 #define HITAG_T_STOP 36 /* T_EOF should be > 36 */
119 #define HITAG_T_LOW 8 /* T_LOW should be 4..10 */
120 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
121 #define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */
122 //#define HITAG_T_EOF 40 /* T_EOF should be > 36 */
123 #define HITAG_T_EOF 80 /* T_EOF should be > 36 */
124 #define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */
125 #define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */
126 #define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */
127
128 #define HITAG_T_TAG_ONE_HALF_PERIOD 10
129 #define HITAG_T_TAG_TWO_HALF_PERIOD 25
130 #define HITAG_T_TAG_THREE_HALF_PERIOD 41
131 #define HITAG_T_TAG_FOUR_HALF_PERIOD 57
132
133 #define HITAG_T_TAG_HALF_PERIOD 16
134 #define HITAG_T_TAG_FULL_PERIOD 32
135
136 #define HITAG_T_TAG_CAPTURE_ONE_HALF 13
137 #define HITAG_T_TAG_CAPTURE_TWO_HALF 25
138 #define HITAG_T_TAG_CAPTURE_THREE_HALF 41
139 #define HITAG_T_TAG_CAPTURE_FOUR_HALF 57
140
141 #define DEBUG 0
142
143 /*
144 * Implementation of the crc8 calculation from Hitag S
145 * from http://www.proxmark.org/files/Documents/125%20kHz%20-%20Hitag/HitagS.V11.pdf
146 */
147 void calc_crc(unsigned char * crc, unsigned char data, unsigned char Bitcount) {
148 *crc ^= data; // crc = crc (exor) data
149 do {
150 if (*crc & 0x80) // if (MSB-CRC == 1)
151 {
152 *crc <<= 1; // CRC = CRC Bit-shift left
153 *crc ^= CRC_POLYNOM; // CRC = CRC (exor) CRC_POLYNOM
154 } else {
155 *crc <<= 1; // CRC = CRC Bit-shift left
156 }
157 } while (--Bitcount);
158 }
159
160 static void hitag_send_bit(int bit) {
161 LED_A_ON();
162 // Reset clock for the next bit
163 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
164
165 switch (m) {
166 case AC2K:
167 if (bit == 0) {
168 // AC Coding --__
169 HIGH(GPIO_SSC_DOUT);
170 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
171 ;
172 LOW(GPIO_SSC_DOUT);
173 while (AT91C_BASE_TC0->TC_CV < T0 * 64)
174 ;
175 } else {
176 // AC coding -_-_
177 HIGH(GPIO_SSC_DOUT);
178 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
179 ;
180 LOW(GPIO_SSC_DOUT);
181 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
182 ;
183 HIGH(GPIO_SSC_DOUT);
184 while (AT91C_BASE_TC0->TC_CV < T0 * 48)
185 ;
186 LOW(GPIO_SSC_DOUT);
187 while (AT91C_BASE_TC0->TC_CV < T0 * 64)
188 ;;
189 }
190 LED_A_OFF();
191 break;
192 case AC4K:
193 if (bit == 0) {
194 // AC Coding --__
195 HIGH(GPIO_SSC_DOUT);
196 while (AT91C_BASE_TC0->TC_CV < T0 * HITAG_T_TAG_HALF_PERIOD)
197 ;
198 LOW(GPIO_SSC_DOUT);
199 while (AT91C_BASE_TC0->TC_CV < T0 * HITAG_T_TAG_FULL_PERIOD)
200 ;
201 } else {
202 // AC coding -_-_
203 HIGH(GPIO_SSC_DOUT);
204 while (AT91C_BASE_TC0->TC_CV < T0 * 8)
205 ;
206 LOW(GPIO_SSC_DOUT);
207 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
208 ;
209 HIGH(GPIO_SSC_DOUT);
210 while (AT91C_BASE_TC0->TC_CV < T0 * 24)
211 ;
212 LOW(GPIO_SSC_DOUT);
213 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
214 ;;
215 }
216 LED_A_OFF();
217 break;
218 case MC4K:
219 if (bit == 0) {
220 // Manchester: Unloaded, then loaded |__--|
221 LOW(GPIO_SSC_DOUT);
222 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
223 ;
224 HIGH(GPIO_SSC_DOUT);
225 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
226 ;
227 } else {
228 // Manchester: Loaded, then unloaded |--__|
229 HIGH(GPIO_SSC_DOUT);
230 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
231 ;
232 LOW(GPIO_SSC_DOUT);
233 while (AT91C_BASE_TC0->TC_CV < T0 * 32)
234 ;
235 }
236 LED_A_OFF();
237 break;
238 case MC8K:
239 if (bit == 0) {
240 // Manchester: Unloaded, then loaded |__--|
241 LOW(GPIO_SSC_DOUT);
242 while (AT91C_BASE_TC0->TC_CV < T0 * 8)
243 ;
244 HIGH(GPIO_SSC_DOUT);
245 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
246 ;
247 } else {
248 // Manchester: Loaded, then unloaded |--__|
249 HIGH(GPIO_SSC_DOUT);
250 while (AT91C_BASE_TC0->TC_CV < T0 * 8)
251 ;
252 LOW(GPIO_SSC_DOUT);
253 while (AT91C_BASE_TC0->TC_CV < T0 * 16)
254 ;
255 }
256 LED_A_OFF();
257 break;
258 default:
259 break;
260 }
261 }
262
263 static void hitag_send_frame(const byte_t* frame, size_t frame_len) {
264 // Send start of frame
265
266 for (size_t i = 0; i < sof_bits; i++) {
267 hitag_send_bit(1);
268 }
269
270 // Send the content of the frame
271 for (size_t i = 0; i < frame_len; i++) {
272 hitag_send_bit((frame[i / 8] >> (7 - (i % 8))) & 1);
273 }
274 // Drop the modulation
275 LOW(GPIO_SSC_DOUT);
276 }
277
278 static void hitag_reader_send_bit(int bit) {
279 //Dbprintf("BIT: %d",bit);
280 LED_A_ON();
281 // Reset clock for the next bit
282 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
283
284 // Binary puls length modulation (BPLM) is used to encode the data stream
285 // This means that a transmission of a one takes longer than that of a zero
286
287 // Enable modulation, which means, drop the the field
288 HIGH(GPIO_SSC_DOUT);
289 if (test == 1) {
290 // Wait for 4-10 times the carrier period
291 while (AT91C_BASE_TC0->TC_CV < T0 * 6)
292 ;
293 // SpinDelayUs(8*8);
294
295 // Disable modulation, just activates the field again
296 LOW(GPIO_SSC_DOUT);
297
298 if (bit == 0) {
299 // Zero bit: |_-|
300 while (AT91C_BASE_TC0->TC_CV < T0 * 11)
301 ;
302 // SpinDelayUs(16*8);
303 } else {
304 // One bit: |_--|
305 while (AT91C_BASE_TC0->TC_CV < T0 * 14)
306 ;
307 // SpinDelayUs(22*8);
308 }
309 } else {
310 // Wait for 4-10 times the carrier period
311 while (AT91C_BASE_TC0->TC_CV < T0 * 6)
312 ;
313 // SpinDelayUs(8*8);
314
315 // Disable modulation, just activates the field again
316 LOW(GPIO_SSC_DOUT);
317
318 if (bit == 0) {
319 // Zero bit: |_-|
320 while (AT91C_BASE_TC0->TC_CV < T0 * 22)
321 ;
322 // SpinDelayUs(16*8);
323 } else {
324 // One bit: |_--|
325 while (AT91C_BASE_TC0->TC_CV < T0 * 28)
326 ;
327 // SpinDelayUs(22*8);
328 }
329 }
330
331 LED_A_OFF();
332 }
333
334 static void hitag_reader_send_frame(const byte_t* frame, size_t frame_len) {
335 // Send the content of the frame
336 for (size_t i = 0; i < frame_len; i++) {
337 if (frame[0] == 0xf8) {
338 //Dbprintf("BIT: %d",(frame[i / 8] >> (7 - (i % 8))) & 1);
339 }
340 hitag_reader_send_bit((frame[i / 8] >> (7 - (i % 8))) & 1);
341 }
342 // Send EOF
343 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
344 // Enable modulation, which means, drop the the field
345 HIGH(GPIO_SSC_DOUT);
346 // Wait for 4-10 times the carrier period
347 while (AT91C_BASE_TC0->TC_CV < T0 * 6)
348 ;
349 // Disable modulation, just activates the field again
350 LOW(GPIO_SSC_DOUT);
351 }
352
353 /*
354 * to check if the right uid was selected
355 */
356 static int check_select(byte_t* rx, uint32_t uid) {
357 unsigned char resp[48];
358 int i;
359 uint32_t ans = 0x0;
360 for (i = 0; i < 48; i++)
361 resp[i] = (rx[i / 8] >> (7 - (i % 8))) & 0x1;
362 for (i = 0; i < 32; i++)
363 ans += resp[5 + i] << (31 - i);
364 /*if (rx[0] == 0x01 && rx[1] == 0x15 && rx[2] == 0xc1 && rx[3] == 0x14
365 && rx[4] == 0x65 && rx[5] == 0x38)
366 Dbprintf("got uid %X", ans);*/
367 temp_uid = ans;
368 if (ans == tag.uid)
369 return 1;
370 return 0;
371 }
372
373 /*
374 * handles all commands from a reader
375 */
376 static void hitagS_handle_reader_command(byte_t* rx, const size_t rxlen,
377 byte_t* tx, size_t* txlen) {
378 byte_t rx_air[HITAG_FRAME_LEN];
379 byte_t page;
380 int i;
381 u64 state;
382 unsigned char crc;
383
384 // Copy the (original) received frame how it is send over the air
385 memcpy(rx_air, rx, nbytes(rxlen));
386 // Reset the transmission frame length
387 *txlen = 0;
388 // Try to find out which command was send by selecting on length (in bits)
389 switch (rxlen) {
390 case 5: {
391 //UID request with a selected response protocol mode
392 tag.pstate = HT_READY;
393 tag.tstate = HT_NO_OP;
394 if ((rx[0] & 0xf0) == 0x30) {
395 tag.mode = HT_STANDARD;
396 sof_bits = 1;
397 m = AC2K;
398 }
399 if ((rx[0] & 0xf0) == 0xc0) {
400 tag.mode = HT_ADVANCED;
401 sof_bits = 3;
402 m = AC2K;
403 }
404
405 if ((rx[0] & 0xf0) == 0xd0) {
406 tag.mode = HT_FAST_ADVANCED;
407 sof_bits = 3;
408 m = AC4K;
409 }
410 //send uid as a response
411 *txlen = 32;
412 for (i = 0; i < 4; i++)
413 tx[i] = (tag.uid >> (24 - (i * 8))) & 0xff;
414 }
415 break;
416 case 45: {
417 //select command from reader received
418 if (check_select(rx, tag.uid) == 1) {
419 //if the right tag was selected
420 *txlen = 32;
421 switch (tag.mode) {
422 case HT_STANDARD:
423 sof_bits = 1;
424 m = MC4K;
425 break;
426 case HT_ADVANCED:
427 sof_bits = 6;
428 m = MC4K;
429 break;
430 case HT_FAST_ADVANCED:
431 sof_bits = 6;
432 m = MC8K;
433 break;
434 default:
435 break;
436 }
437
438 //send configuration
439 for (i = 0; i < 4; i++)
440 tx[i] = (tag.pages[0][1] >> (i * 8)) & 0xff;
441 tx[3] = 0xff;
442 if (tag.mode != HT_STANDARD) {
443 *txlen = 40;
444 crc = CRC_PRESET;
445 for (i = 0; i < 4; i++)
446 calc_crc(&crc, tx[i], 8);
447 tx[4] = crc;
448 }
449 }
450 }
451 break;
452 case 64: {
453 //challenge message received
454 Dbprintf("Challenge for UID: %X", temp_uid);
455 temp2++;
456 *txlen = 32;
457 state = hitag2_init(rev64(tag.key), rev32(tag.pages[0][0]),
458 rev32(((rx[3] << 24) + (rx[2] << 16) + (rx[1] << 8) + rx[0])));
459 Dbprintf(
460 ",{0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X}",
461 rx[0], rx[1], rx[2], rx[3], rx[4], rx[5], rx[6], rx[7]);
462 switch (tag.mode) {
463 case HT_STANDARD:
464 sof_bits = 1;
465 m = MC4K;
466 break;
467 case HT_ADVANCED:
468 sof_bits = 6;
469 m = MC4K;
470 break;
471 case HT_FAST_ADVANCED:
472 sof_bits = 6;
473 m = MC8K;
474 break;
475 default:
476 break;
477 }
478
479 for (i = 0; i < 4; i++)
480 hitag2_byte(&state);
481 //send con2,pwdh0,pwdl0,pwdl1 encrypted as a response
482 tx[0] = hitag2_byte(&state) ^ ((tag.pages[0][1] >> 16) & 0xff);
483 tx[1] = hitag2_byte(&state) ^ tag.pwdh0;
484 tx[2] = hitag2_byte(&state) ^ tag.pwdl0;
485 tx[3] = hitag2_byte(&state) ^ tag.pwdl1;
486 if (tag.mode != HT_STANDARD) {
487 //add crc8
488 *txlen = 40;
489 crc = CRC_PRESET;
490 calc_crc(&crc, ((tag.pages[0][1] >> 16) & 0xff), 8);
491 calc_crc(&crc, tag.pwdh0, 8);
492 calc_crc(&crc, tag.pwdl0, 8);
493 calc_crc(&crc, tag.pwdl1, 8);
494 tx[4] = (crc ^ hitag2_byte(&state));
495 }
496 /*
497 * some readers do not allow to authenticate multiple times in a row with the same tag.
498 * use this to change the uid between authentications.
499 */
500
501 /*
502 if (temp2 % 2 == 0) {
503 tag.uid = 0x11223344;
504 tag.pages[0][0] = 0x44332211;
505 } else {
506 tag.uid = 0x55667788;
507 tag.pages[0][0] = 0x88776655;
508 }
509 */
510 }
511 case 40:
512 //data received to be written
513 if (tag.tstate == HT_WRITING_PAGE_DATA) {
514 tag.tstate = HT_NO_OP;
515 tag.pages[page_to_be_written / 4][page_to_be_written % 4] = (rx[0]
516 << 0) + (rx[1] << 8) + (rx[2] << 16) + (rx[3] << 24);
517 //send ack
518 *txlen = 2;
519 tx[0] = 0x40;
520 page_to_be_written = 0;
521 switch (tag.mode) {
522 case HT_STANDARD:
523 sof_bits = 1;
524 m = MC4K;
525 break;
526 case HT_ADVANCED:
527 sof_bits = 6;
528 m = MC4K;
529 break;
530 case HT_FAST_ADVANCED:
531 sof_bits = 6;
532 m = MC8K;
533 break;
534 default:
535 break;
536 }
537 } else if (tag.tstate == HT_WRITING_BLOCK_DATA) {
538 tag.pages[page_to_be_written / 4][page_to_be_written % 4] = (rx[0]
539 << 24) + (rx[1] << 16) + (rx[2] << 8) + rx[3];
540 //send ack
541 *txlen = 2;
542 tx[0] = 0x40;
543 switch (tag.mode) {
544 case HT_STANDARD:
545 sof_bits = 1;
546 m = MC4K;
547 break;
548 case HT_ADVANCED:
549 sof_bits = 6;
550 m = MC4K;
551 break;
552 case HT_FAST_ADVANCED:
553 sof_bits = 6;
554 m = MC8K;
555 break;
556 default:
557 break;
558 }
559 page_to_be_written++;
560 block_data_left--;
561 if (block_data_left == 0) {
562 tag.tstate = HT_NO_OP;
563 page_to_be_written = 0;
564 }
565 }
566 break;
567 case 20: {
568 //write page, write block, read page or read block command received
569 if ((rx[0] & 0xf0) == 0xc0) //read page
570 {
571 //send page data
572 page = ((rx[0] & 0x0f) * 16) + ((rx[1] & 0xf0) / 16);
573 *txlen = 32;
574 tx[0] = (tag.pages[page / 4][page % 4]) & 0xff;
575 tx[1] = (tag.pages[page / 4][page % 4] >> 8) & 0xff;
576 tx[2] = (tag.pages[page / 4][page % 4] >> 16) & 0xff;
577 tx[3] = (tag.pages[page / 4][page % 4] >> 24) & 0xff;
578 if (tag.LKP && page == 1)
579 tx[3] = 0xff;
580
581 switch (tag.mode) {
582 case HT_STANDARD:
583 sof_bits = 1;
584 m = MC4K;
585 break;
586 case HT_ADVANCED:
587 sof_bits = 6;
588 m = MC4K;
589 break;
590 case HT_FAST_ADVANCED:
591 sof_bits = 6;
592 m = MC8K;
593 break;
594 default:
595 break;
596 }
597
598 if (tag.mode != HT_STANDARD) {
599 //add crc8
600 *txlen = 40;
601 crc = CRC_PRESET;
602 for (i = 0; i < 4; i++)
603 calc_crc(&crc, tx[i], 8);
604 tx[4] = crc;
605 }
606
607 if (tag.LKP && (page == 2 || page == 3)) {
608 //if reader asks for key or password and the LKP-mark is set do not respond
609 sof_bits = 0;
610 *txlen = 0;
611 }
612 } else if ((rx[0] & 0xf0) == 0xd0) //read block
613 {
614 page = ((rx[0] & 0x0f) * 16) + ((rx[1] & 0xf0) / 16);
615 *txlen = 32 * 4;
616 //send page,...,page+3 data
617 for (i = 0; i < 4; i++) {
618 tx[0 + i * 4] = (tag.pages[page / 4][page % 4]) & 0xff;
619 tx[1 + i * 4] = (tag.pages[page / 4][page % 4] >> 8) & 0xff;
620 tx[2 + i * 4] = (tag.pages[page / 4][page % 4] >> 16) & 0xff;
621 tx[3 + i * 4] = (tag.pages[page / 4][page % 4] >> 24) & 0xff;
622 page++;
623 }
624
625 switch (tag.mode) {
626 case HT_STANDARD:
627 sof_bits = 1;
628 m = MC4K;
629 break;
630 case HT_ADVANCED:
631 sof_bits = 6;
632 m = MC4K;
633 break;
634 case HT_FAST_ADVANCED:
635 sof_bits = 6;
636 m = MC8K;
637 break;
638 default:
639 break;
640 }
641
642 if (tag.mode != HT_STANDARD) {
643 //add crc8
644 *txlen = 32 * 4 + 8;
645 crc = CRC_PRESET;
646 for (i = 0; i < 16; i++)
647 calc_crc(&crc, tx[i], 8);
648 tx[16] = crc;
649 }
650
651 if ((page - 4) % 4 != 0 || (tag.LKP && (page - 4) == 0)) {
652 sof_bits = 0;
653 *txlen = 0;
654 }
655 } else if ((rx[0] & 0xf0) == 0x80) //write page
656 {
657 page = ((rx[0] & 0x0f) * 16) + ((rx[1] & 0xf0) / 16);
658
659 switch (tag.mode) {
660 case HT_STANDARD:
661 sof_bits = 1;
662 m = MC4K;
663 break;
664 case HT_ADVANCED:
665 sof_bits = 6;
666 m = MC4K;
667 break;
668 case HT_FAST_ADVANCED:
669 sof_bits = 6;
670 m = MC8K;
671 break;
672 default:
673 break;
674 }
675 if ((tag.LCON && page == 1)
676 || (tag.LKP && (page == 2 || page == 3))) {
677 //deny
678 *txlen = 0;
679 } else {
680 //allow
681 *txlen = 2;
682 tx[0] = 0x40;
683 page_to_be_written = page;
684 tag.tstate = HT_WRITING_PAGE_DATA;
685 }
686
687 } else if ((rx[0] & 0xf0) == 0x90) //write block
688 {
689 page = ((rx[0] & 0x0f) * 6) + ((rx[1] & 0xf0) / 16);
690 switch (tag.mode) {
691 case HT_STANDARD:
692 sof_bits = 1;
693 m = MC4K;
694 break;
695 case HT_ADVANCED:
696 sof_bits = 6;
697 m = MC4K;
698 break;
699 case HT_FAST_ADVANCED:
700 sof_bits = 6;
701 m = MC8K;
702 break;
703 default:
704 break;
705 }
706 if (page % 4 != 0 || page == 0) {
707 //deny
708 *txlen = 0;
709 } else {
710 //allow
711 *txlen = 2;
712 tx[0] = 0x40;
713 page_to_be_written = page;
714 block_data_left = 4;
715 tag.tstate = HT_WRITING_BLOCK_DATA;
716 }
717 }
718 }
719 break;
720 default:
721
722 break;
723 }
724 }
725
726 /*
727 * to autenticate to a tag with the given key or challenge
728 */
729 static int hitagS_handle_tag_auth(hitag_function htf,uint64_t key, uint64_t NrAr, byte_t* rx, const size_t rxlen, byte_t* tx,
730 size_t* txlen) {
731 byte_t rx_air[HITAG_FRAME_LEN];
732 int response_bit[200];
733 int i, j, z, k;
734 unsigned char mask = 1;
735 unsigned char uid[32];
736 byte_t uid1 = 0x00, uid2 = 0x00, uid3 = 0x00, uid4 = 0x00;
737 unsigned char crc;
738 u64 state;
739 byte_t auth_ks[4];
740 byte_t conf_pages[3];
741 memcpy(rx_air, rx, nbytes(rxlen));
742 *txlen = 0;
743
744 if (tag.pstate == HT_READY && rxlen >= 67) {
745 //received uid
746 if(end==true) {
747 Dbprintf("authentication failed!");
748 return -1;
749 }
750 z = 0;
751 for (i = 0; i < 10; i++) {
752 for (j = 0; j < 8; j++) {
753 response_bit[z] = 0;
754 if ((rx[i] & ((mask << 7) >> j)) != 0)
755 response_bit[z] = 1;
756 z++;
757 }
758 }
759 k = 0;
760 for (i = 5; i < z; i += 2) {
761 uid[k] = response_bit[i];
762 k++;
763 if (k > 31)
764 break;
765 }
766 uid1 = (uid[0] << 7) | (uid[1] << 6) | (uid[2] << 5) | (uid[3] << 4)
767 | (uid[4] << 3) | (uid[5] << 2) | (uid[6] << 1) | uid[7];
768 uid2 = (uid[8] << 7) | (uid[9] << 6) | (uid[10] << 5) | (uid[11] << 4)
769 | (uid[12] << 3) | (uid[13] << 2) | (uid[14] << 1) | uid[15];
770 uid3 = (uid[16] << 7) | (uid[17] << 6) | (uid[18] << 5) | (uid[19] << 4)
771 | (uid[20] << 3) | (uid[21] << 2) | (uid[22] << 1) | uid[23];
772 uid4 = (uid[24] << 7) | (uid[25] << 6) | (uid[26] << 5) | (uid[27] << 4)
773 | (uid[28] << 3) | (uid[29] << 2) | (uid[30] << 1) | uid[31];
774 if (DEBUG)
775 Dbprintf("UID: %02X %02X %02X %02X", uid1, uid2, uid3, uid4);
776 tag.uid = (uid4 << 24 | uid3 << 16 | uid2 << 8 | uid1);
777
778 //select uid
779 *txlen = 45;
780 crc = CRC_PRESET;
781 calc_crc(&crc, 0x00, 5);
782 calc_crc(&crc, uid1, 8);
783 calc_crc(&crc, uid2, 8);
784 calc_crc(&crc, uid3, 8);
785 calc_crc(&crc, uid4, 8);
786 for (i = 0; i < 100; i++) {
787 response_bit[i] = 0;
788 }
789 for (i = 0; i < 5; i++) {
790 response_bit[i] = 0;
791 }
792 for (i = 5; i < 37; i++) {
793 response_bit[i] = uid[i - 5];
794 }
795 for (j = 0; j < 8; j++) {
796 response_bit[i] = 0;
797 if ((crc & ((mask << 7) >> j)) != 0)
798 response_bit[i] = 1;
799 i++;
800 }
801 k = 0;
802 for (i = 0; i < 6; i++) {
803 tx[i] = (response_bit[k] << 7) | (response_bit[k + 1] << 6)
804 | (response_bit[k + 2] << 5) | (response_bit[k + 3] << 4)
805 | (response_bit[k + 4] << 3) | (response_bit[k + 5] << 2)
806 | (response_bit[k + 6] << 1) | response_bit[k + 7];
807 k += 8;
808 }
809 tag.pstate = HT_INIT;
810 } else if (tag.pstate == HT_INIT && rxlen == 44) {
811 // received configuration after select command
812 z = 0;
813 for (i = 0; i < 6; i++) {
814 for (j = 0; j < 8; j++) {
815 response_bit[z] = 0;
816 if ((rx[i] & ((mask << 7) >> j)) != 0)
817 response_bit[z] = 1;
818 z++;
819 }
820 }
821 conf_pages[0] = ((response_bit[4] << 7) | (response_bit[5] << 6)
822 | (response_bit[6] << 5) | (response_bit[7] << 4)
823 | (response_bit[8] << 3) | (response_bit[9] << 2)
824 | (response_bit[10] << 1) | response_bit[11]);
825 //check wich memorysize this tag has
826 if (response_bit[10] == 0 && response_bit[11] == 0)
827 tag.max_page = 32 / 32;
828 if (response_bit[10] == 0 && response_bit[11] == 1)
829 tag.max_page = 256 / 32;
830 if (response_bit[10] == 1 && response_bit[11] == 0)
831 tag.max_page = 2048 / 32;
832 conf_pages[1] = ((response_bit[12] << 7) | (response_bit[13] << 6)
833 | (response_bit[14] << 5) | (response_bit[15] << 4)
834 | (response_bit[16] << 3) | (response_bit[17] << 2)
835 | (response_bit[18] << 1) | response_bit[19]);
836 tag.auth = response_bit[12];
837 tag.TTFC = response_bit[13];
838 //tag.TTFDR in response_bit[14] and response_bit[15]
839 //tag.TTFM in response_bit[16] and response_bit[17]
840 tag.LCON = response_bit[18];
841 tag.LKP = response_bit[19];
842 conf_pages[2] = ((response_bit[20] << 7) | (response_bit[21] << 6)
843 | (response_bit[22] << 5) | (response_bit[23] << 4)
844 | (response_bit[24] << 3) | (response_bit[25] << 2)
845 | (response_bit[26] << 1) | response_bit[27]);
846 tag.LCK7 = response_bit[20];
847 tag.LCK6 = response_bit[21];
848 tag.LCK5 = response_bit[22];
849 tag.LCK4 = response_bit[23];
850 tag.LCK3 = response_bit[24];
851 tag.LCK2 = response_bit[25];
852 tag.LCK1 = response_bit[26];
853 tag.LCK0 = response_bit[27];
854
855 if (DEBUG)
856 Dbprintf("conf0: %02X conf1: %02X conf2: %02X", conf_pages[0],
857 conf_pages[1], conf_pages[2]);
858 if (tag.auth == 1) {
859 //if the tag is in authentication mode try the key or challenge
860 *txlen = 64;
861 if(end!=true){
862 if(htf==02||htf==04){ //RHTS_KEY //WHTS_KEY
863 state = hitag2_init(rev64(key), rev32(tag.uid),
864 rev32(rnd));
865
866 for (i = 0; i < 4; i++) {
867 auth_ks[i] = hitag2_byte(&state) ^ 0xff;
868 }
869 *txlen = 64;
870 tx[0] = rnd & 0xff;
871 tx[1] = (rnd >> 8) & 0xff;
872 tx[2] = (rnd >> 16) & 0xff;
873 tx[3] = (rnd >> 24) & 0xff;
874
875 tx[4] = auth_ks[0];
876 tx[5] = auth_ks[1];
877 tx[6] = auth_ks[2];
878 tx[7] = auth_ks[3];
879 if (DEBUG)
880 Dbprintf("%02X %02X %02X %02X %02X %02X %02X %02X", tx[0],
881 tx[1], tx[2], tx[3], tx[4], tx[5], tx[6], tx[7]);
882 } else if(htf==01 || htf==03) { //RHTS_CHALLENGE //WHTS_CHALLENGE
883 for (i = 0; i < 8; i++)
884 tx[i]=((NrAr>>(56-(i*8)))&0xff);
885 }
886 end=true;
887 tag.pstate = HT_AUTHENTICATE;
888 } else {
889 Dbprintf("authentication failed!");
890 return -1;
891 }
892 } else if (tag.auth == 0) {
893 tag.pstate = HT_SELECTED;
894 }
895
896 } else if (tag.pstate == HT_AUTHENTICATE && rxlen == 44) {
897 //encrypted con2,password received.
898 crc = CRC_PRESET;
899 calc_crc(&crc, 0x80, 1);
900 calc_crc(&crc, ((rx[0] & 0x0f) * 16 + ((rx[1] & 0xf0) / 16)), 8);
901 calc_crc(&crc, ((rx[1] & 0x0f) * 16 + ((rx[2] & 0xf0) / 16)), 8);
902 calc_crc(&crc, ((rx[2] & 0x0f) * 16 + ((rx[3] & 0xf0) / 16)), 8);
903 calc_crc(&crc, ((rx[3] & 0x0f) * 16 + ((rx[4] & 0xf0) / 16)), 8);
904 if (DEBUG) {
905 Dbprintf("UID:::%X", tag.uid);
906 Dbprintf("RND:::%X", rnd);
907 }
908
909 //decrypt password
910 pwdh0=0;
911 pwdl0=0;
912 pwdl1=0;
913 if(htf==02 || htf==04){ //RHTS_KEY //WHTS_KEY
914 {
915 state = hitag2_init(rev64(key), rev32(tag.uid), rev32(rnd));
916 for (i = 0; i < 5; i++)
917 hitag2_byte(&state);
918 pwdh0 = ((rx[1] & 0x0f) * 16 + ((rx[2] & 0xf0) / 16))
919 ^ hitag2_byte(&state);
920 pwdl0 = ((rx[2] & 0x0f) * 16 + ((rx[3] & 0xf0) / 16))
921 ^ hitag2_byte(&state);
922 pwdl1 = ((rx[3] & 0x0f) * 16 + ((rx[4] & 0xf0) / 16))
923 ^ hitag2_byte(&state);
924 }
925
926 if (DEBUG)
927 Dbprintf("pwdh0 %02X pwdl0 %02X pwdl1 %02X", pwdh0, pwdl0, pwdl1);
928
929
930 //Dbprintf("%X %02X", rnd, ((rx[4] & 0x0f) * 16) + ((rx[5] & 0xf0) / 16));
931 //rnd += 1;
932 }
933 tag.pstate = HT_SELECTED; //tag is now ready for read/write commands
934 }
935 return 0;
936
937 }
938
939 /*
940 * Emulates a Hitag S Tag with the given data from the .hts file
941 */
942 void SimulateHitagSTag(bool tag_mem_supplied, byte_t* data) {
943 int frame_count;
944 int response;
945 int overflow;
946 int i, j;
947 byte_t rx[HITAG_FRAME_LEN];
948 size_t rxlen = 0;
949 //bool bQuitTraceFull = false;
950 bQuiet = false;
951 byte_t txbuf[HITAG_FRAME_LEN];
952 byte_t* tx = txbuf;
953 size_t txlen = 0;
954 // free eventually allocated BigBuf memory
955 BigBuf_free(); BigBuf_Clear_ext(false);
956
957 // Clean up trace and prepare it for storing frames
958 set_tracing(TRUE);
959 clear_trace();
960
961 DbpString("Starting HitagS simulation");
962 LED_D_ON();
963
964 tag.pstate = HT_READY;
965 tag.tstate = HT_NO_OP;
966 tag.tstate = HT_NO_OP;
967 for (i = 0; i < 16; i++)
968 for (j = 0; j < 4; j++)
969 tag.pages[i][j] = 0x0;
970 //read tag data into memory
971 if (tag_mem_supplied) {
972 DbpString("Loading hitagS memory...");
973 memcpy((byte_t*)tag.pages,data,4*64);
974 }
975 tag.uid=(uint32_t)tag.pages[0];
976 Dbprintf("Hitag S simulation started");
977 tag.key=(intptr_t)tag.pages[3];
978 tag.key<<=16;
979 tag.key+=((tag.pages[2][0])<<8)+tag.pages[2][1];
980 tag.pwdl0=tag.pages[2][3];
981 tag.pwdl1=tag.pages[2][2];
982 tag.pwdh0=tag.pages[1][0];
983 //con0
984 tag.max_page=64;
985 if((tag.pages[1][3]&0x2)==0 && (tag.pages[1][3]&0x1)==1)
986 tag.max_page=8;
987 if((tag.pages[1][3]&0x2)==0 && (tag.pages[1][3]&0x1)==0)
988 tag.max_page=0;
989 //con1
990 tag.auth=0;
991 if((tag.pages[1][2]&0x80)==1)
992 tag.auth=1;
993 tag.LCON=0;
994 if((tag.pages[1][2]&0x2)==1)
995 tag.LCON=1;
996 tag.LKP=0;
997 if((tag.pages[1][2]&0x1)==1)
998 tag.LKP=1;
999 //con2
1000 //0=read write 1=read only
1001 tag.LCK7=0;
1002 if((tag.pages[1][1]&0x80)==1)
1003 tag.LCK7=1;
1004 tag.LCK6=0;
1005 if((tag.pages[1][1]&0x40)==1)
1006 tag.LCK6=1;
1007 tag.LCK5=0;
1008 if((tag.pages[1][1]&0x20)==1)
1009 tag.LCK5=1;
1010 tag.LCK4=0;
1011 if((tag.pages[1][1]&0x10)==1)
1012 tag.LCK4=1;
1013 tag.LCK3=0;
1014 if((tag.pages[1][1]&0x8)==1)
1015 tag.LCK3=1;
1016 tag.LCK2=0;
1017 if((tag.pages[1][1]&0x4)==1)
1018 tag.LCK2=1;
1019 tag.LCK1=0;
1020 if((tag.pages[1][1]&0x2)==1)
1021 tag.LCK1=1;
1022 tag.LCK0=0;
1023 if((tag.pages[1][1]&0x1)==1)
1024 tag.LCK0=1;
1025
1026 // Set up simulator mode, frequency divisor which will drive the FPGA
1027 // and analog mux selection.
1028 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1029 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
1030 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1031 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1032 RELAY_OFF();
1033
1034 // Configure output pin that is connected to the FPGA (for modulating)
1035 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1036 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1037
1038 // Disable modulation at default, which means release resistance
1039 LOW(GPIO_SSC_DOUT);
1040
1041 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1042 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1043
1044 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
1045 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1046 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1047
1048 // Disable timer during configuration
1049 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1050
1051 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1052 // external trigger rising edge, load RA on rising edge of TIOA.
1053 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1054 | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
1055
1056 // Reset the received frame, frame count and timing info
1057 memset(rx, 0x00, sizeof(rx));
1058 frame_count = 0;
1059 response = 0;
1060 overflow = 0;
1061
1062 // Enable and reset counter
1063 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1064
1065 while (!BUTTON_PRESS()) {
1066 // Watchdog hit
1067 WDT_HIT();
1068
1069 // Receive frame, watch for at most T0*EOF periods
1070 while (AT91C_BASE_TC1->TC_CV < T0 * HITAG_T_EOF) {
1071 // Check if rising edge in modulation is detected
1072 if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1073 // Retrieve the new timing values
1074 int ra = (AT91C_BASE_TC1->TC_RA / T0) + overflow;
1075 overflow = 0;
1076
1077 // Reset timer every frame, we have to capture the last edge for timing
1078 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1079
1080 LED_B_ON();
1081
1082 // Capture reader frame
1083 if (ra >= HITAG_T_STOP) {
1084 if (rxlen != 0) {
1085 //DbpString("wierd0?");
1086 }
1087 // Capture the T0 periods that have passed since last communication or field drop (reset)
1088 response = (ra - HITAG_T_LOW);
1089 } else if (ra >= HITAG_T_1_MIN) {
1090 // '1' bit
1091 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1092 rxlen++;
1093 } else if (ra >= HITAG_T_0_MIN) {
1094 // '0' bit
1095 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1096 rxlen++;
1097 } else {
1098 // Ignore wierd value, is to small to mean anything
1099 }
1100 }
1101 }
1102
1103 // Check if frame was captured
1104 if (rxlen > 0) {
1105 frame_count++;
1106 if (!bQuiet) {
1107 if (!LogTraceHitag(rx, rxlen, response, 0, true)) {
1108 DbpString("Trace full");
1109 clear_trace();
1110 }
1111 }
1112
1113 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1114 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1115
1116 // Process the incoming frame (rx) and prepare the outgoing frame (tx)
1117 hitagS_handle_reader_command(rx, rxlen, tx, &txlen);
1118
1119 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
1120 // not that since the clock counts since the rising edge, but T_Wait1 is
1121 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
1122 // periods. The gap time T_Low varies (4..10). All timer values are in
1123 // terms of T0 units
1124 while (AT91C_BASE_TC0->TC_CV < T0 * (HITAG_T_WAIT_1 - HITAG_T_LOW))
1125 ;
1126
1127 // Send and store the tag answer (if there is any)
1128 if (txlen > 0) {
1129 // Transmit the tag frame
1130 hitag_send_frame(tx, txlen);
1131 // Store the frame in the trace
1132 if (!bQuiet) {
1133 if (!LogTraceHitag(tx, txlen, 0, 0, false)) {
1134 DbpString("Trace full");
1135 clear_trace();
1136 }
1137 }
1138 }
1139
1140 // Reset the received frame and response timing info
1141 memset(rx, 0x00, sizeof(rx));
1142 response = 0;
1143
1144 // Enable and reset external trigger in timer for capturing future frames
1145 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1146 LED_B_OFF();
1147 }
1148 // Reset the frame length
1149 rxlen = 0;
1150 // Save the timer overflow, will be 0 when frame was received
1151 overflow += (AT91C_BASE_TC1->TC_CV / T0);
1152 // Reset the timer to restart while-loop that receives frames
1153 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
1154 }
1155 LED_B_OFF();
1156 LED_D_OFF();
1157 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1158 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1159 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1160 }
1161
1162 /*
1163 * Authenticates to the Tag with the given key or challenge.
1164 * If the key was given the password will be decrypted.
1165 * Reads every page of a hitag S transpoder.
1166 */
1167 void ReadHitagS(hitag_function htf, hitag_data* htd) {
1168 int i, j, z, k;
1169 int frame_count;
1170 int response_bit[200];
1171 int response;
1172 byte_t rx[HITAG_FRAME_LEN];
1173 size_t rxlen = 0;
1174 byte_t txbuf[HITAG_FRAME_LEN];
1175 byte_t* tx = txbuf;
1176 size_t txlen = 0;
1177 int lastbit;
1178 bool bSkip;
1179 int reset_sof;
1180 int tag_sof;
1181 int t_wait = HITAG_T_WAIT_MAX;
1182 bool bStop;
1183 bool bQuitTraceFull = false;
1184 int sendNum = 0;
1185 unsigned char mask = 1;
1186 unsigned char crc;
1187 unsigned char pageData[32];
1188 page_to_be_written = 0;
1189
1190 //read given key/challenge
1191 byte_t NrAr_[8];
1192 uint64_t key=0;
1193 uint64_t NrAr=0;
1194 byte_t key_[6];
1195 switch(htf) {
1196 case 01: { //RHTS_CHALLENGE
1197 DbpString("Authenticating using nr,ar pair:");
1198 memcpy(NrAr_,htd->auth.NrAr,8);
1199 Dbhexdump(8,NrAr_,false);
1200 NrAr=NrAr_[7] | ((uint64_t)NrAr_[6]) << 8 | ((uint64_t)NrAr_[5]) << 16 | ((uint64_t)NrAr_[4]) << 24 | ((uint64_t)NrAr_[3]) << 32 |
1201 ((uint64_t)NrAr_[2]) << 40| ((uint64_t)NrAr_[1]) << 48 | ((uint64_t)NrAr_[0]) << 56;
1202 } break;
1203 case 02: { //RHTS_KEY
1204 DbpString("Authenticating using key:");
1205 memcpy(key_,htd->crypto.key,6);
1206 Dbhexdump(6,key_,false);
1207 key=key_[5] | ((uint64_t)key_[4]) << 8 | ((uint64_t)key_[3]) << 16 | ((uint64_t)key_[2]) << 24 | ((uint64_t)key_[1]) << 32 | ((uint64_t)key_[0]) << 40;
1208 } break;
1209 default: {
1210 Dbprintf("Error , unknown function: %d",htf);
1211 return;
1212 } break;
1213 }
1214
1215
1216
1217 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1218 // Reset the return status
1219 bSuccessful = false;
1220
1221 // Clean up trace and prepare it for storing frames
1222 set_tracing(TRUE);
1223 clear_trace();
1224
1225 bQuiet = false;
1226 bQuitTraceFull = true;
1227
1228 LED_D_ON();
1229
1230 // Configure output and enable pin that is connected to the FPGA (for modulating)
1231 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1232 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1233
1234 // Set fpga in edge detect with reader field, we can modulate as reader now
1235 FpgaWriteConfWord(
1236 FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1237
1238 // Set Frequency divisor which will drive the FPGA and analog mux selection
1239 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1240 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1241 RELAY_OFF();
1242
1243 // Disable modulation at default, which means enable the field
1244 LOW(GPIO_SSC_DOUT);
1245
1246 // Give it a bit of time for the resonant antenna to settle.
1247 SpinDelay(30);
1248
1249 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1250 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1251
1252 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1253 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1254 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1255
1256 // Disable timer during configuration
1257 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1258
1259 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1260 // external trigger rising edge, load RA on falling edge of TIOA.
1261 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1262
1263 | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
1264
1265 // Enable and reset counters
1266 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1267 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1268
1269 // Reset the received frame, frame count and timing info
1270 frame_count = 0;
1271 response = 0;
1272 lastbit = 1;
1273 bStop = false;
1274
1275 reset_sof = 1;
1276 t_wait = 200;
1277
1278 while (!bStop && !BUTTON_PRESS()) {
1279 // Watchdog hit
1280 WDT_HIT();
1281
1282 // Check if frame was captured and store it
1283 if (rxlen > 0) {
1284 frame_count++;
1285 if (!bQuiet) {
1286 if (!LogTraceHitag(rx, rxlen, response, 0, false)) {
1287 DbpString("Trace full");
1288 if (bQuitTraceFull) {
1289 break;
1290 } else {
1291 bQuiet = true;
1292 }
1293 }
1294 }
1295 }
1296
1297 // By default reset the transmission buffer
1298 tx = txbuf;
1299 txlen = 0;
1300
1301 if (rxlen == 0) {
1302 //start authentication
1303 txlen = 5;
1304 memcpy(tx, "\xc0", nbytes(txlen));
1305 tag.pstate = HT_READY;
1306 tag.tstate = HT_NO_OP;
1307 } else if (tag.pstate != HT_SELECTED) {
1308 if (hitagS_handle_tag_auth(htf, key,NrAr,rx, rxlen, tx, &txlen) == -1)
1309 bStop = !false;
1310 }
1311 if (tag.pstate == HT_SELECTED && tag.tstate == HT_NO_OP && rxlen > 0) {
1312 //send read request
1313 tag.tstate = HT_READING_PAGE;
1314 txlen = 20;
1315 crc = CRC_PRESET;
1316 tx[0] = 0xc0 + (sendNum / 16);
1317 calc_crc(&crc, tx[0], 8);
1318 calc_crc(&crc, 0x00 + ((sendNum % 16) * 16), 4);
1319 tx[1] = 0x00 + ((sendNum % 16) * 16) + (crc / 16);
1320 tx[2] = 0x00 + (crc % 16) * 16;
1321 } else if (tag.pstate == HT_SELECTED && tag.tstate == HT_READING_PAGE
1322 && rxlen > 0) {
1323 //save received data
1324 z = 0;
1325 for (i = 0; i < 5; i++) {
1326 for (j = 0; j < 8; j++) {
1327 response_bit[z] = 0;
1328 if ((rx[i] & ((mask << 7) >> j)) != 0)
1329 response_bit[z] = 1;
1330 z++;
1331 }
1332 }
1333 k = 0;
1334 for (i = 4; i < 36; i++) {
1335 pageData[k] = response_bit[i];
1336 k++;
1337 }
1338 for (i = 0; i < 4; i++)
1339 tag.pages[sendNum / 4][sendNum % 4] = 0x0;
1340 for (i = 0; i < 4; i++) {
1341 tag.pages[sendNum / 4][sendNum % 4] += ((pageData[i * 8] << 7)
1342 | (pageData[1 + (i * 8)] << 6)
1343 | (pageData[2 + (i * 8)] << 5)
1344 | (pageData[3 + (i * 8)] << 4)
1345 | (pageData[4 + (i * 8)] << 3)
1346 | (pageData[5 + (i * 8)] << 2)
1347 | (pageData[6 + (i * 8)] << 1) | pageData[7 + (i * 8)])
1348 << (i * 8);
1349 }
1350 if (tag.auth && tag.LKP && sendNum == 1) {
1351 Dbprintf("Page[%2d]: %02X %02X %02X %02X", sendNum, pwdh0,
1352 (tag.pages[sendNum / 4][sendNum % 4] >> 16) & 0xff,
1353 (tag.pages[sendNum / 4][sendNum % 4] >> 8) & 0xff,
1354 tag.pages[sendNum / 4][sendNum % 4] & 0xff);
1355 } else {
1356 Dbprintf("Page[%2d]: %02X %02X %02X %02X", sendNum,
1357 (tag.pages[sendNum / 4][sendNum % 4] >> 24) & 0xff,
1358 (tag.pages[sendNum / 4][sendNum % 4] >> 16) & 0xff,
1359 (tag.pages[sendNum / 4][sendNum % 4] >> 8) & 0xff,
1360 tag.pages[sendNum / 4][sendNum % 4] & 0xff);
1361 }
1362
1363 sendNum++;
1364 //display key and password if possible
1365 if (sendNum == 2 && tag.auth == 1 && tag.LKP) {
1366 if (htf == 02) { //RHTS_KEY
1367 Dbprintf("Page[ 2]: %02X %02X %02X %02X",
1368 (byte_t)(key >> 8) & 0xff,
1369 (byte_t) key & 0xff, pwdl1, pwdl0);
1370 Dbprintf("Page[ 3]: %02X %02X %02X %02X",
1371 (byte_t)(key >> 40) & 0xff,
1372 (byte_t)(key >> 32) & 0xff,
1373 (byte_t)(key >> 24) & 0xff,
1374 (byte_t)(key >> 16) & 0xff);
1375 } else {
1376 //if the authentication is done with a challenge the key and password are unknown
1377 Dbprintf("Page[ 2]: __ __ __ __");
1378 Dbprintf("Page[ 3]: __ __ __ __");
1379 }
1380 }
1381
1382 txlen = 20;
1383 crc = CRC_PRESET;
1384 tx[0] = 0xc0 + (sendNum / 16);
1385 calc_crc(&crc, tx[0], 8);
1386 calc_crc(&crc, 0x00 + ((sendNum % 16) * 16), 4);
1387 tx[1] = 0x00 + ((sendNum % 16) * 16) + (crc / 16);
1388 tx[2] = 0x00 + (crc % 16) * 16;
1389 if (sendNum >= tag.max_page) {
1390 bStop = !false;
1391 }
1392 }
1393
1394 // Send and store the reader command
1395 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1396 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1397
1398 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1399 // Since the clock counts since the last falling edge, a 'one' means that the
1400 // falling edge occured halfway the period. with respect to this falling edge,
1401 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1402 // All timer values are in terms of T0 units
1403
1404 while (AT91C_BASE_TC0->TC_CV
1405 < T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit)))
1406 ;
1407
1408 // Transmit the reader frame
1409 hitag_reader_send_frame(tx, txlen);
1410
1411 // Enable and reset external trigger in timer for capturing future frames
1412 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1413
1414 // Add transmitted frame to total count
1415 if (txlen > 0) {
1416 frame_count++;
1417 if (!bQuiet) {
1418 // Store the frame in the trace
1419 if (!LogTraceHitag(tx, txlen, HITAG_T_WAIT_2, 0, true)) {
1420 if (bQuitTraceFull) {
1421 DbpString("Trace full");
1422 break;
1423 } else {
1424 bQuiet = true;
1425 }
1426 }
1427 }
1428 }
1429
1430 // Reset values for receiving frames
1431 memset(rx, 0x00, sizeof(rx));
1432 rxlen = 0;
1433 lastbit = 1;
1434 bSkip = true;
1435 tag_sof = reset_sof;
1436 response = 0;
1437
1438 // Receive frame, watch for at most T0*EOF periods
1439 while (AT91C_BASE_TC1->TC_CV < T0 * HITAG_T_WAIT_MAX) {
1440 // Check if falling edge in tag modulation is detected
1441 if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1442 // Retrieve the new timing values
1443 int ra = (AT91C_BASE_TC1->TC_RA / T0);
1444
1445 // Reset timer every frame, we have to capture the last edge for timing
1446 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
1447
1448 LED_B_ON();
1449
1450 // Capture tag frame (manchester decoding using only falling edges)
1451 if (ra >= HITAG_T_EOF) {
1452 if (rxlen != 0) {
1453 //DbpString("wierd1?");
1454 }
1455 // Capture the T0 periods that have passed since last communication or field drop (reset)
1456 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
1457 response = ra - HITAG_T_TAG_HALF_PERIOD;
1458 } else if (ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
1459 // Manchester coding example |-_|_-|-_| (101)
1460 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1461 rxlen++;
1462 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1463 rxlen++;
1464 } else if (ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
1465 // Manchester coding example |_-|...|_-|-_| (0...01)
1466 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1467 rxlen++;
1468 // We have to skip this half period at start and add the 'one' the second time
1469 if (!bSkip) {
1470 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1471 rxlen++;
1472 }
1473 lastbit = !lastbit;
1474 bSkip = !bSkip;
1475 } else if (ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
1476 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
1477 if (tag_sof) {
1478 // Ignore bits that are transmitted during SOF
1479 tag_sof--;
1480 } else {
1481 // bit is same as last bit
1482 rx[rxlen / 8] |= lastbit << (7 - (rxlen % 8));
1483 rxlen++;
1484 }
1485 } else {
1486 // Ignore wierd value, is to small to mean anything
1487 }
1488 }
1489
1490 // We can break this loop if we received the last bit from a frame
1491 if (AT91C_BASE_TC1->TC_CV > T0 * HITAG_T_EOF) {
1492 if (rxlen > 0)
1493 break;
1494 }
1495 }
1496 }
1497 end=false;
1498 LED_B_OFF();
1499 LED_D_OFF();
1500 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1501 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1502 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1503 cmd_send(CMD_ACK, bSuccessful, 0, 0, 0, 0);
1504 }
1505
1506 /*
1507 * Authenticates to the Tag with the given Key or Challenge.
1508 * Writes the given 32Bit data into page_
1509 */
1510 void WritePageHitagS(hitag_function htf, hitag_data* htd,int page_) {
1511 int frame_count;
1512 int response;
1513 byte_t rx[HITAG_FRAME_LEN];
1514 size_t rxlen = 0;
1515 byte_t txbuf[HITAG_FRAME_LEN];
1516 byte_t* tx = txbuf;
1517 size_t txlen = 0;
1518 int lastbit;
1519 bool bSkip;
1520 int reset_sof;
1521 int tag_sof;
1522 int t_wait = HITAG_T_WAIT_MAX;
1523 bool bStop;
1524 bool bQuitTraceFull = false;
1525 int page = page_;
1526 unsigned char crc;
1527 byte_t data[4]= {0,0,0,0};
1528
1529 //read given key/challenge, the page and the data
1530 byte_t NrAr_[8];
1531 uint64_t key=0;
1532 uint64_t NrAr=0;
1533 byte_t key_[6];
1534 switch(htf) {
1535 case 03: { //WHTS_CHALLENGE
1536 memcpy(data,htd->auth.data,4);
1537 DbpString("Authenticating using nr,ar pair:");
1538 memcpy(NrAr_,htd->auth.NrAr,8);
1539 Dbhexdump(8,NrAr_,false);
1540 NrAr=NrAr_[7] | ((uint64_t)NrAr_[6]) << 8 | ((uint64_t)NrAr_[5]) << 16 | ((uint64_t)NrAr_[4]) << 24 | ((uint64_t)NrAr_[3]) << 32 |
1541 ((uint64_t)NrAr_[2]) << 40| ((uint64_t)NrAr_[1]) << 48 | ((uint64_t)NrAr_[0]) << 56;
1542 } break;
1543 case 04: { //WHTS_KEY
1544 memcpy(data,htd->crypto.data,4);
1545 DbpString("Authenticating using key:");
1546 memcpy(key_,htd->crypto.key,6);
1547 Dbhexdump(6,key_,false);
1548 key=key_[5] | ((uint64_t)key_[4]) << 8 | ((uint64_t)key_[3]) << 16 | ((uint64_t)key_[2]) << 24 | ((uint64_t)key_[1]) << 32 | ((uint64_t)key_[0]) << 40;
1549 } break;
1550 default: {
1551 Dbprintf("Error , unknown function: %d",htf);
1552 return;
1553 } break;
1554 }
1555
1556 Dbprintf("Page: %d",page_);
1557 Dbprintf("DATA: %02X %02X %02X %02X", data[0], data[1], data[2], data[3]);
1558 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1559 // Reset the return status
1560 bSuccessful = false;
1561
1562 tag.pstate = HT_READY;
1563 tag.tstate = HT_NO_OP;
1564
1565 // Clean up trace and prepare it for storing frames
1566 set_tracing(TRUE);
1567 clear_trace();
1568
1569 bQuiet = false;
1570 bQuitTraceFull = true;
1571
1572 LED_D_ON();
1573
1574 // Configure output and enable pin that is connected to the FPGA (for modulating)
1575 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1576 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1577
1578 // Set fpga in edge detect with reader field, we can modulate as reader now
1579 FpgaWriteConfWord(
1580 FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1581
1582 // Set Frequency divisor which will drive the FPGA and analog mux selection
1583 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1584 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1585 RELAY_OFF();
1586
1587 // Disable modulation at default, which means enable the field
1588 LOW(GPIO_SSC_DOUT);
1589
1590 // Give it a bit of time for the resonant antenna to settle.
1591 SpinDelay(30);
1592
1593 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1594 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1595
1596 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1597 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1598 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1599
1600 // Disable timer during configuration
1601 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1602
1603 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1604 // external trigger rising edge, load RA on falling edge of TIOA.
1605 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1606 | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG
1607 | AT91C_TC_LDRA_FALLING;
1608
1609 // Enable and reset counters
1610 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1611 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1612
1613 // Reset the received frame, frame count and timing info
1614 frame_count = 0;
1615 response = 0;
1616 lastbit = 1;
1617 bStop = false;
1618
1619 reset_sof = 1;
1620 t_wait = 200;
1621
1622 while (!bStop && !BUTTON_PRESS()) {
1623 // Watchdog hit
1624 WDT_HIT();
1625
1626 // Check if frame was captured and store it
1627 if (rxlen > 0) {
1628 frame_count++;
1629 if (!bQuiet) {
1630 if (!LogTraceHitag(rx, rxlen, response, 0, false)) {
1631 DbpString("Trace full");
1632 if (bQuitTraceFull) {
1633 break;
1634 } else {
1635 bQuiet = true;
1636 }
1637 }
1638 }
1639 }
1640
1641 //check for valid input
1642 if (page == 0) {
1643 Dbprintf(
1644 "usage: lf hitag writer [03 | 04] [CHALLENGE | KEY] [page] [byte0] [byte1] [byte2] [byte3]");
1645 bStop = !false;
1646 }
1647
1648 // By default reset the transmission buffer
1649 tx = txbuf;
1650 txlen = 0;
1651
1652 if (rxlen == 0 && tag.tstate == HT_WRITING_PAGE_ACK) {
1653 //no write access on this page
1654 Dbprintf("no write access on page %d", page_);
1655 bStop = !false;
1656 } else if (rxlen == 0 && tag.tstate != HT_WRITING_PAGE_DATA) {
1657 //start the authetication
1658 txlen = 5;
1659 memcpy(tx, "\xc0", nbytes(txlen));
1660 tag.pstate = HT_READY;
1661 tag.tstate = HT_NO_OP;
1662 } else if (tag.pstate != HT_SELECTED) {
1663 //try to authenticate with the given key or challenge
1664 if (hitagS_handle_tag_auth(htf,key,NrAr,rx, rxlen, tx, &txlen) == -1)
1665 bStop = !false;
1666 }
1667 if (tag.pstate == HT_SELECTED && tag.tstate == HT_NO_OP && rxlen > 0) {
1668 //check if the given page exists
1669 if (page > tag.max_page) {
1670 Dbprintf("page number too big");
1671 bStop = !false;
1672 }
1673 //ask Tag for write permission
1674 tag.tstate = HT_WRITING_PAGE_ACK;
1675 txlen = 20;
1676 crc = CRC_PRESET;
1677 tx[0] = 0x90 + (page / 16);
1678 calc_crc(&crc, tx[0], 8);
1679 calc_crc(&crc, 0x00 + ((page % 16) * 16), 4);
1680 tx[1] = 0x00 + ((page % 16) * 16) + (crc / 16);
1681 tx[2] = 0x00 + (crc % 16) * 16;
1682 } else if (tag.pstate == HT_SELECTED && tag.tstate == HT_WRITING_PAGE_ACK
1683 && rxlen == 6 && rx[0] == 0xf4) {
1684 //ACK recieved to write the page. send data
1685 tag.tstate = HT_WRITING_PAGE_DATA;
1686 txlen = 40;
1687 crc = CRC_PRESET;
1688 calc_crc(&crc, data[3], 8);
1689 calc_crc(&crc, data[2], 8);
1690 calc_crc(&crc, data[1], 8);
1691 calc_crc(&crc, data[0], 8);
1692 tx[0] = data[3];
1693 tx[1] = data[2];
1694 tx[2] = data[1];
1695 tx[3] = data[0];
1696 tx[4] = crc;
1697 } else if (tag.pstate == HT_SELECTED && tag.tstate == HT_WRITING_PAGE_DATA
1698 && rxlen == 6 && rx[0] == 0xf4) {
1699 //received ACK
1700 Dbprintf("Successful!");
1701 bStop = !false;
1702 }
1703
1704 // Send and store the reader command
1705 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1706 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1707
1708 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1709 // Since the clock counts since the last falling edge, a 'one' means that the
1710 // falling edge occured halfway the period. with respect to this falling edge,
1711 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1712 // All timer values are in terms of T0 units
1713
1714 while (AT91C_BASE_TC0->TC_CV
1715 < T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit)))
1716 ;
1717
1718 // Transmit the reader frame
1719 hitag_reader_send_frame(tx, txlen);
1720
1721 // Enable and reset external trigger in timer for capturing future frames
1722 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1723
1724 // Add transmitted frame to total count
1725 if (txlen > 0) {
1726 frame_count++;
1727 if (!bQuiet) {
1728 // Store the frame in the trace
1729 if (!LogTraceHitag(tx, txlen, HITAG_T_WAIT_2, 0, true)) {
1730 if (bQuitTraceFull) {
1731 DbpString("Trace full");
1732 break;
1733 } else {
1734 bQuiet = true;
1735 }
1736 }
1737 }
1738 }
1739
1740 // Reset values for receiving frames
1741 memset(rx, 0x00, sizeof(rx));
1742 rxlen = 0;
1743 lastbit = 1;
1744 bSkip = true;
1745 tag_sof = reset_sof;
1746 response = 0;
1747
1748 // Receive frame, watch for at most T0*EOF periods
1749 while (AT91C_BASE_TC1->TC_CV < T0 * HITAG_T_WAIT_MAX) {
1750 // Check if falling edge in tag modulation is detected
1751 if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1752 // Retrieve the new timing values
1753 int ra = (AT91C_BASE_TC1->TC_RA / T0);
1754
1755 // Reset timer every frame, we have to capture the last edge for timing
1756 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
1757
1758 LED_B_ON();
1759
1760 // Capture tag frame (manchester decoding using only falling edges)
1761 if (ra >= HITAG_T_EOF) {
1762 if (rxlen != 0) {
1763 //DbpString("wierd1?");
1764 }
1765 // Capture the T0 periods that have passed since last communication or field drop (reset)
1766 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
1767 response = ra - HITAG_T_TAG_HALF_PERIOD;
1768 } else if (ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
1769 // Manchester coding example |-_|_-|-_| (101)
1770 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1771 rxlen++;
1772 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1773 rxlen++;
1774 } else if (ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
1775 // Manchester coding example |_-|...|_-|-_| (0...01)
1776 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
1777 rxlen++;
1778 // We have to skip this half period at start and add the 'one' the second time
1779 if (!bSkip) {
1780 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
1781 rxlen++;
1782 }
1783 lastbit = !lastbit;
1784 bSkip = !bSkip;
1785 } else if (ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
1786 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
1787 if (tag_sof) {
1788 // Ignore bits that are transmitted during SOF
1789 tag_sof--;
1790 } else {
1791 // bit is same as last bit
1792 rx[rxlen / 8] |= lastbit << (7 - (rxlen % 8));
1793 rxlen++;
1794 }
1795 } else {
1796 // Ignore wierd value, is to small to mean anything
1797 }
1798 }
1799
1800 // We can break this loop if we received the last bit from a frame
1801 if (AT91C_BASE_TC1->TC_CV > T0 * HITAG_T_EOF) {
1802 if (rxlen > 0)
1803 break;
1804 }
1805 }
1806 }
1807 end=false;
1808 LED_B_OFF();
1809 LED_D_OFF();
1810 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1811 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1812 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1813 cmd_send(CMD_ACK, bSuccessful, 0, 0, 0, 0);
1814 }
1815
1816 /*
1817 * Tries to authenticate to a Hitag S Transponder with the given challenges from a .cc file.
1818 * Displays all Challenges that failed.
1819 * When collecting Challenges to break the key it is possible that some data
1820 * is not received correctly due to Antenna problems. This function
1821 * detects these challenges.
1822 */
1823 void check_challenges(bool file_given, byte_t* data) {
1824 int i, j, z, k;
1825 byte_t uid_byte[4];
1826 int frame_count;
1827 int response;
1828 byte_t rx[HITAG_FRAME_LEN];
1829 byte_t unlocker[60][8];
1830 int u1 = 0;
1831 size_t rxlen = 0;
1832 byte_t txbuf[HITAG_FRAME_LEN];
1833 byte_t* tx = txbuf;
1834 size_t txlen = 0;
1835 int lastbit;
1836 bool bSkip;
1837 int reset_sof;
1838 int tag_sof;
1839 int t_wait = HITAG_T_WAIT_MAX;
1840 int STATE = 0;
1841 bool bStop;
1842 bool bQuitTraceFull = false;
1843 int response_bit[200];
1844 unsigned char mask = 1;
1845 unsigned char uid[32];
1846 unsigned char crc;
1847
1848 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1849 // Reset the return status
1850 bSuccessful = false;
1851
1852 // Clean up trace and prepare it for storing frames
1853 set_tracing(TRUE);
1854 clear_trace();
1855
1856 bQuiet = false;
1857 bQuitTraceFull = true;
1858
1859 LED_D_ON();
1860
1861 // Configure output and enable pin that is connected to the FPGA (for modulating)
1862 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1863 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1864
1865 // Set fpga in edge detect with reader field, we can modulate as reader now
1866 FpgaWriteConfWord(
1867 FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1868
1869 // Set Frequency divisor which will drive the FPGA and analog mux selection
1870 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1871 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1872 RELAY_OFF();
1873
1874 // Disable modulation at default, which means enable the field
1875 LOW(GPIO_SSC_DOUT);
1876
1877 // Give it a bit of time for the resonant antenna to settle.
1878 SpinDelay(30);
1879
1880 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1881 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1882
1883 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1884 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1885 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1886
1887 // Disable timer during configuration
1888 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1889
1890 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1891 // external trigger rising edge, load RA on falling edge of TIOA.
1892 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1893
1894 | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
1895
1896 // Enable and reset counters
1897 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1898 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1899
1900 // Reset the received frame, frame count and timing info
1901 frame_count = 0;
1902 response = 0;
1903 lastbit = 1;
1904 bStop = false;
1905
1906 reset_sof = 1;
1907 t_wait = 200;
1908
1909 if (file_given) {
1910 DbpString("Loading challenges...");
1911 memcpy((byte_t*)unlocker,data,60*8);
1912 }
1913
1914 while (file_given && !bStop && !BUTTON_PRESS()) {
1915 // Watchdog hit
1916 WDT_HIT();
1917
1918 // Check if frame was captured and store it
1919 if (rxlen > 0) {
1920 frame_count++;
1921 if (!bQuiet) {
1922 if (!LogTraceHitag(rx, rxlen, response, 0, false)) {
1923 DbpString("Trace full");
1924 if (bQuitTraceFull) {
1925 break;
1926 } else {
1927 bQuiet = true;
1928 }
1929 }
1930 }
1931 }
1932
1933 tx = txbuf;
1934 txlen = 0;
1935 if (rxlen == 0) {
1936 if (STATE == 2)
1937 // challenge failed
1938 Dbprintf("Challenge failed: %02X %02X %02X %02X %02X %02X %02X %02X",
1939 unlocker[u1 - 1][0], unlocker[u1 - 1][1],
1940 unlocker[u1 - 1][2], unlocker[u1 - 1][3],
1941 unlocker[u1 - 1][4], unlocker[u1 - 1][5],
1942 unlocker[u1 - 1][6], unlocker[u1 - 1][7]);
1943 STATE = 0;
1944 txlen = 5;
1945 //start new authentication
1946 memcpy(tx, "\xc0", nbytes(txlen));
1947 } else if (rxlen >= 67 && STATE == 0) {
1948 //received uid
1949 z = 0;
1950 for (i = 0; i < 10; i++) {
1951 for (j = 0; j < 8; j++) {
1952 response_bit[z] = 0;
1953 if ((rx[i] & ((mask << 7) >> j)) != 0)
1954 response_bit[z] = 1;
1955 z++;
1956 }
1957 }
1958 k = 0;
1959 for (i = 5; i < z; i += 2) {
1960 uid[k] = response_bit[i];
1961 k++;
1962 if (k > 31)
1963 break;
1964 }
1965 uid_byte[0] = (uid[0] << 7) | (uid[1] << 6) | (uid[2] << 5)
1966 | (uid[3] << 4) | (uid[4] << 3) | (uid[5] << 2)
1967 | (uid[6] << 1) | uid[7];
1968 uid_byte[1] = (uid[8] << 7) | (uid[9] << 6) | (uid[10] << 5)
1969 | (uid[11] << 4) | (uid[12] << 3) | (uid[13] << 2)
1970 | (uid[14] << 1) | uid[15];
1971 uid_byte[2] = (uid[16] << 7) | (uid[17] << 6) | (uid[18] << 5)
1972 | (uid[19] << 4) | (uid[20] << 3) | (uid[21] << 2)
1973 | (uid[22] << 1) | uid[23];
1974 uid_byte[3] = (uid[24] << 7) | (uid[25] << 6) | (uid[26] << 5)
1975 | (uid[27] << 4) | (uid[28] << 3) | (uid[29] << 2)
1976 | (uid[30] << 1) | uid[31];
1977 //Dbhexdump(10, rx, rxlen);
1978 STATE = 1;
1979 txlen = 45;
1980 crc = CRC_PRESET;
1981 calc_crc(&crc, 0x00, 5);
1982 calc_crc(&crc, uid_byte[0], 8);
1983 calc_crc(&crc, uid_byte[1], 8);
1984 calc_crc(&crc, uid_byte[2], 8);
1985 calc_crc(&crc, uid_byte[3], 8);
1986 for (i = 0; i < 100; i++) {
1987 response_bit[i] = 0;
1988 }
1989 for (i = 0; i < 5; i++) {
1990 response_bit[i] = 0;
1991 }
1992 for (i = 5; i < 37; i++) {
1993 response_bit[i] = uid[i - 5];
1994 }
1995 for (j = 0; j < 8; j++) {
1996 response_bit[i] = 0;
1997 if ((crc & ((mask << 7) >> j)) != 0)
1998 response_bit[i] = 1;
1999 i++;
2000 }
2001 k = 0;
2002 for (i = 0; i < 6; i++) {
2003 tx[i] = (response_bit[k] << 7) | (response_bit[k + 1] << 6)
2004 | (response_bit[k + 2] << 5)
2005 | (response_bit[k + 3] << 4)
2006 | (response_bit[k + 4] << 3)
2007 | (response_bit[k + 5] << 2)
2008 | (response_bit[k + 6] << 1) | response_bit[k + 7];
2009 k += 8;
2010 }
2011
2012 } else if (STATE == 1 && rxlen == 44) {
2013 //received configuration
2014 STATE = 2;
2015 z = 0;
2016 for (i = 0; i < 6; i++) {
2017 for (j = 0; j < 8; j++) {
2018 response_bit[z] = 0;
2019 if ((rx[i] & ((mask << 7) >> j)) != 0)
2020 response_bit[z] = 1;
2021 z++;
2022 }
2023 }
2024 txlen = 64;
2025
2026 if (u1 >= (sizeof(unlocker) / sizeof(unlocker[0])))
2027 bStop = !false;
2028 for (i = 0; i < 8; i++)
2029 tx[i] = unlocker[u1][i];
2030 u1++;
2031
2032 } else if (STATE == 2 && rxlen >= 44) {
2033 STATE = 0;
2034 }
2035
2036 // Send and store the reader command
2037 // Disable timer 1 with external trigger to avoid triggers during our own modulation
2038 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
2039
2040 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
2041 // Since the clock counts since the last falling edge, a 'one' means that the
2042 // falling edge occured halfway the period. with respect to this falling edge,
2043 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
2044 // All timer values are in terms of T0 units
2045
2046 while (AT91C_BASE_TC0->TC_CV
2047 < T0 * (t_wait + (HITAG_T_TAG_HALF_PERIOD * lastbit)))
2048 ;
2049
2050 // Transmit the reader frame
2051 hitag_reader_send_frame(tx, txlen);
2052
2053 // Enable and reset external trigger in timer for capturing future frames
2054 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
2055
2056 // Add transmitted frame to total count
2057 if (txlen > 0) {
2058 frame_count++;
2059 if (!bQuiet) {
2060 // Store the frame in the trace
2061 if (!LogTraceHitag(tx, txlen, HITAG_T_WAIT_2, 0, true)) {
2062 if (bQuitTraceFull) {
2063 DbpString("Trace full");
2064 break;
2065 } else {
2066 bQuiet = true;
2067 }
2068 }
2069 }
2070 }
2071
2072 // Reset values for receiving frames
2073 memset(rx, 0x00, sizeof(rx));
2074 rxlen = 0;
2075 lastbit = 1;
2076 bSkip = true;
2077 tag_sof = reset_sof;
2078 response = 0;
2079
2080 // Receive frame, watch for at most T0*EOF periods
2081 while (AT91C_BASE_TC1->TC_CV < T0 * HITAG_T_WAIT_MAX) {
2082 // Check if falling edge in tag modulation is detected
2083 if (AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
2084 // Retrieve the new timing values
2085 int ra = (AT91C_BASE_TC1->TC_RA / T0);
2086
2087 // Reset timer every frame, we have to capture the last edge for timing
2088 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
2089
2090 LED_B_ON();
2091
2092 // Capture tag frame (manchester decoding using only falling edges)
2093 if (ra >= HITAG_T_EOF) {
2094 if (rxlen != 0) {
2095 //DbpString("wierd1?");
2096 }
2097 // Capture the T0 periods that have passed since last communication or field drop (reset)
2098 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
2099 response = ra - HITAG_T_TAG_HALF_PERIOD;
2100 } else if (ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
2101 // Manchester coding example |-_|_-|-_| (101)
2102 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
2103 rxlen++;
2104 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
2105 rxlen++;
2106 } else if (ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
2107 // Manchester coding example |_-|...|_-|-_| (0...01)
2108 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
2109 rxlen++;
2110 // We have to skip this half period at start and add the 'one' the second time
2111 if (!bSkip) {
2112 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
2113 rxlen++;
2114 }
2115 lastbit = !lastbit;
2116 bSkip = !bSkip;
2117 } else if (ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
2118 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
2119 if (tag_sof) {
2120 // Ignore bits that are transmitted during SOF
2121 tag_sof--;
2122 } else {
2123 // bit is same as last bit
2124 rx[rxlen / 8] |= lastbit << (7 - (rxlen % 8));
2125 rxlen++;
2126 }
2127 } else {
2128 // Ignore wierd value, is to small to mean anything
2129 }
2130 }
2131
2132 // We can break this loop if we received the last bit from a frame
2133 if (AT91C_BASE_TC1->TC_CV > T0 * HITAG_T_EOF) {
2134 if (rxlen > 0)
2135 break;
2136 }
2137 }
2138 }
2139 LED_B_OFF();
2140 LED_D_OFF();
2141 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
2142 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
2143 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2144 cmd_send(CMD_ACK, bSuccessful, 0, 0, 0, 0);
2145 }
2146
2147
2148
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