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1 //-----------------------------------------------------------------------------
2 // ISO14443-A support for the Proxmark III
3 // Gerhard de Koning Gans, April 2008
4 //-----------------------------------------------------------------------------
5
6 // constants for the different modes:
7 `define SNIFFER 3'b000
8 `define TAGSIM_LISTEN 3'b001
9 `define TAGSIM_MOD 3'b010
10 `define READER_LISTEN 3'b011
11 `define READER_MOD 3'b100
12
13 module hi_iso14443a(
14 pck0, ck_1356meg, ck_1356megb,
15 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
16 adc_d, adc_clk,
17 ssp_frame, ssp_din, ssp_dout, ssp_clk,
18 cross_hi, cross_lo,
19 dbg,
20 mod_type
21 );
22 input pck0, ck_1356meg, ck_1356megb;
23 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
24 input [7:0] adc_d;
25 output adc_clk;
26 input ssp_dout;
27 output ssp_frame, ssp_din, ssp_clk;
28 input cross_hi, cross_lo;
29 output dbg;
30 input [2:0] mod_type;
31
32 reg ssp_clk;
33 reg ssp_frame;
34
35 wire adc_clk;
36 assign adc_clk = ck_1356meg;
37
38 reg after_hysteresis, pre_after_hysteresis, after_hysteresis_prev1, after_hysteresis_prev2, after_hysteresis_prev3, after_hysteresis_prev4;
39 reg [11:0] has_been_low_for;
40 reg [8:0] saw_deep_modulation;
41 reg [2:0] deep_counter;
42 reg deep_modulation;
43
44 always @(negedge adc_clk)
45 begin
46 if(& adc_d[7:6]) after_hysteresis <= 1'b1; // adc_d >= 196 (U >= 3,28V) -> after_hysteris = 1
47 else if(~(| adc_d[7:4])) after_hysteresis <= 1'b0; // if adc_d <= 15 (U <= 1,13V) -> after_hysteresis = 0
48
49 pre_after_hysteresis <= after_hysteresis;
50
51 if(~(| adc_d[7:0])) // if adc_d == 0 (U <= 0,94V)
52 begin
53 if(deep_counter == 3'd7) // adc_d == 0 for 7 adc_clk ticks -> deep_modulation (by reader)
54 begin
55 deep_modulation <= 1'b1;
56 saw_deep_modulation <= 8'd0;
57 end
58 else
59 deep_counter <= deep_counter + 1;
60 end
61 else
62 begin
63 deep_counter <= 3'd0;
64 if(saw_deep_modulation == 8'd255) // adc_d != 0 for 255 adc_clk ticks -> deep_modulation is over, now waiting for tag's response
65 deep_modulation <= 1'b0;
66 else
67 saw_deep_modulation <= saw_deep_modulation + 1;
68 end
69
70 if(after_hysteresis)
71 begin
72 has_been_low_for <= 12'd0;
73 end
74 else
75 begin
76 if(has_been_low_for == 12'd4095)
77 begin
78 has_been_low_for <= 12'd0;
79 after_hysteresis <= 1'b1; // reset after_hysteresis to 1 if it had been 0 for 4096 cycles (no field)
80 end
81 else
82 begin
83 has_been_low_for <= has_been_low_for + 1;
84 end
85 end
86 end
87
88
89
90 // Report every 4 subcarrier cycles
91 // 128 periods of carrier frequency => 7-bit counter [negedge_cnt]
92 reg [6:0] negedge_cnt;
93 reg bit1, bit2, bit3, bit4;
94 reg curbit;
95
96 // storage for four previous samples:
97 reg [7:0] adc_d_1;
98 reg [7:0] adc_d_2;
99 reg [7:0] adc_d_3;
100 reg [7:0] adc_d_4;
101
102 // the filtered signal (filter performs noise reduction and edge detection)
103 // (gaussian derivative)
104 wire signed [10:0] adc_d_filtered;
105 assign adc_d_filtered = (adc_d_4 << 1) + adc_d_3 - adc_d_1 - (adc_d << 1);
106
107 // Registers to store steepest edges detected:
108 reg [7:0] rx_mod_falling_edge_max;
109 reg [7:0] rx_mod_rising_edge_max;
110
111 // A register to send 8 Bit results to the arm
112 reg [7:0] to_arm;
113
114
115 reg bit_to_arm;
116 reg fdt_indicator, fdt_elapsed;
117 reg [10:0] fdt_counter;
118 //reg [47:0] mod_sig_buf;
119 reg [31:0] mod_sig_buf;
120 //reg [5:0] mod_sig_ptr;
121 reg [4:0] mod_sig_ptr;
122 reg [3:0] mod_sig_flip;
123 reg mod_sig, mod_sig_coil;
124 reg temp_buffer_reset;
125 reg sendbit;
126 reg [3:0] sub_carrier_cnt;
127 reg[3:0] reader_falling_edge_time;
128
129 // ADC data appears on the rising edge, so sample it on the falling edge
130 always @(negedge adc_clk)
131 begin
132 // ------------------------------------------------------------------------------------------------------------------------------------------------------------------
133 // relevant for TAGSIM_MOD only. Timing of Tag's answer relative to a command received from a reader
134 // ISO14443-3 specifies:
135 // fdt = 1172, if last bit was 0.
136 // fdt = 1236, if last bit was 1.
137 // the FPGA takes care for the 1172 delay. To achieve the additional 1236-1172=64 ticks delay, the ARM must send an additional correction bit (before the start bit).
138 // The correction bit will be coded as 00010000, i.e. it adds 4 bits to the transmission stream, causing the required delay.
139 if(fdt_counter == 11'd547) fdt_indicator <= 1'b1; // The ARM must not send earlier to prevent mod_sig_buf overflow.
140 // The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks. fdt_indicator
141 // could appear at ssp_din after 1 tick, 16 ticks for the transfer, 128 ticks until response is sended.
142 // 1148 - 464 - 1 - 128 - 8 = 547
143
144 if ((mod_type == `TAGSIM_MOD) || (mod_type == `TAGSIM_LISTEN))
145 begin
146 if(fdt_counter == 11'd1148) // the RF part delays the rising edge by approx 5 adc_clk_ticks, the ADC needs 3 clk_ticks for A/D conversion,
147 // 16 ticks delay by mod_sig_buf
148 // 1172 - 5 - 3 - 16 = 1148.
149 begin
150 if(fdt_elapsed)
151 begin
152 if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig; // start modulating (if mod_sig is already set)
153 sub_carrier_cnt[3:0] <= sub_carrier_cnt[3:0] + 1;
154 end
155 else
156 begin
157 mod_sig_flip <= negedge_cnt[3:0]; // start modulation at this time
158 sub_carrier_cnt[3:0] <= 0; // subcarrier phase in sync with start of modulation
159 mod_sig_coil <= mod_sig; // assign signal to coil
160 fdt_elapsed = 1'b1;
161 if(~(| mod_sig_ptr[4:0])) mod_sig_ptr <= 5'd9; // if mod_sig_ptr == 0 -> didn't receive a 1 yet. Delay next 1 by n*128 ticks.
162 else temp_buffer_reset = 1'b1; // else fix the buffer size at current position
163 end
164 end
165 else
166 begin
167 fdt_counter <= fdt_counter + 1; // Count until 1155
168 end
169 end
170 else // other modes: don't use the delay line.
171 begin
172 mod_sig_coil <= ssp_dout;
173 end
174
175
176 //-------------------------------------------------------------------------------------------------------------------------------------------
177 // Relevant for READER_LISTEN only
178 // look for steepest falling and rising edges:
179
180 if(negedge_cnt[3:0] == 4'd1) // reset modulation detector. Save current edge.
181 begin
182 if (adc_d_filtered > 0)
183 begin
184 rx_mod_falling_edge_max <= adc_d_filtered;
185 rx_mod_rising_edge_max <= 0;
186 end
187 else
188 begin
189 rx_mod_falling_edge_max <= 0;
190 rx_mod_rising_edge_max <= -adc_d_filtered;
191 end
192 end
193 else // detect modulation
194 begin
195 if (adc_d_filtered > 0)
196 begin
197 if (adc_d_filtered > rx_mod_falling_edge_max)
198 rx_mod_falling_edge_max <= adc_d_filtered;
199 end
200 else
201 begin
202 if (-adc_d_filtered > rx_mod_rising_edge_max)
203 rx_mod_rising_edge_max <= -adc_d_filtered;
204 end
205 end
206
207 // detect modulation signal: if modulating, there must be a falling and a rising edge
208 if (rx_mod_falling_edge_max > 6 && rx_mod_rising_edge_max > 6)
209 curbit <= 1'b1; // modulation
210 else
211 curbit <= 1'b0; // no modulation
212
213
214 // store previous samples for filtering and edge detection:
215 adc_d_4 <= adc_d_3;
216 adc_d_3 <= adc_d_2;
217 adc_d_2 <= adc_d_1;
218 adc_d_1 <= adc_d;
219
220
221 // Relevant for TAGSIM_MOD only (timing the Tag's answer. See above)
222 // When we see end of a modulation and we are emulating a Tag, start fdt_counter.
223 // Reset fdt_counter when modulation is detected.
224 if(~after_hysteresis /* && mod_sig_buf_empty */ && mod_type == `TAGSIM_LISTEN)
225 begin
226 fdt_counter <= 11'd0;
227 fdt_elapsed = 1'b0;
228 fdt_indicator <= 1'b0;
229 temp_buffer_reset = 1'b0;
230 mod_sig_ptr <= 5'b00000;
231 mod_sig = 1'b0;
232 end
233
234
235 if(negedge_cnt[3:0] == 4'd1)
236 begin
237 // What do we communicate to the ARM
238 if(mod_type == `TAGSIM_LISTEN)
239 sendbit = after_hysteresis;
240 else if(mod_type == `TAGSIM_MOD)
241 /* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
242 else */
243 sendbit = fdt_indicator;
244 else if (mod_type == `READER_LISTEN)
245 sendbit = curbit;
246 else
247 sendbit = 1'b0;
248 end
249
250
251
252 // check timing of a falling edge in reader signal
253 if (pre_after_hysteresis && ~after_hysteresis)
254 reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
255
256
257
258 // sync clock to external reader's clock:
259 if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_MOD || mod_type == `TAGSIM_LISTEN))
260 begin
261 // adjust clock if necessary:
262 if (reader_falling_edge_time < 4'd8 && reader_falling_edge_time > 4'd1)
263 begin
264 negedge_cnt <= negedge_cnt; // freeze time
265 end
266 else if (reader_falling_edge_time == 4'd8)
267 begin
268 negedge_cnt <= negedge_cnt + 1; // the desired state. Advance as usual;
269 end
270 else
271 begin
272 negedge_cnt[3:0] <= 4'd15; // time warp
273 end
274 reader_falling_edge_time <= 4'd8; // only once per detected rising edge
275 end
276
277
278
279 //------------------------------------------------------------------------------------------------------------------------------------------
280 // Prepare 8 Bits to communicate to ARM
281 if (negedge_cnt == 7'd63)
282 begin
283 if (mod_type == `SNIFFER)
284 begin
285 if(deep_modulation) // a reader is sending (or there's no field at all)
286 begin
287 to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis_prev4,1'b0,1'b0,1'b0,1'b0};
288 end
289 else
290 begin
291 to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis_prev4,bit1,bit2,bit3,bit4};
292 end
293 negedge_cnt <= 0;
294 end
295 else
296 begin
297 negedge_cnt <= negedge_cnt + 1;
298 end
299 end
300 else if(negedge_cnt == 7'd127)
301 begin
302 if (mod_type == `TAGSIM_MOD)
303 begin
304 to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]};
305 negedge_cnt <= 0;
306 end
307 else
308 begin
309 to_arm[7:0] <= 8'd0;
310 negedge_cnt <= negedge_cnt + 1;
311 end
312 end
313 else
314 begin
315 negedge_cnt <= negedge_cnt + 1;
316 end
317
318
319 if(negedge_cnt == 7'd1)
320 begin
321 after_hysteresis_prev1 <= after_hysteresis;
322 bit1 <= curbit;
323 end
324 if(negedge_cnt == 7'd17)
325 begin
326 after_hysteresis_prev2 <= after_hysteresis;
327 bit2 <= curbit;
328 end
329 if(negedge_cnt == 7'd33)
330 begin
331 after_hysteresis_prev3 <= after_hysteresis;
332 bit3 <= curbit;
333 end
334 if(negedge_cnt == 7'd49)
335 begin
336 after_hysteresis_prev4 <= after_hysteresis;
337 bit4 <= curbit;
338 end
339
340 //--------------------------------------------------------------------------------------------------------------------------------------------------------------
341 // Relevant in TAGSIM_MOD only. Delay-Line to buffer data and send it at the correct time
342 if(negedge_cnt[3:0] == 4'd0) // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
343 begin
344 mod_sig_buf[31:0] <= {mod_sig_buf[30:1], ssp_dout, 1'b0}; // shift in new data starting at mod_sig_buf[1]. mod_sig_buf[0] = 0 always.
345 // asign the delayed signal to mod_sig, but don't modulate with the correction bit (which is sent as 00010000, all other bits will come with at least 2 consecutive 1s)
346 // side effect: when ptr = 1 it will cancel the first 1 of every block of ones. Note: this would only be the case if we received a 1 just before fdt_elapsed.
347 if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed) // buffer a 1 (and all subsequent data) until fdt_counter = 1148 adc_clk ticks.
348 //if(mod_sig_ptr == 6'b101110) // buffer overflow at 46 - this would mean data loss
349 //begin
350 // mod_sig_ptr <= 6'b000000;
351 //end
352 if (mod_sig_ptr == 5'd30) mod_sig_ptr <= 5'd0;
353 else mod_sig_ptr <= mod_sig_ptr + 1; // increase buffer (= increase delay by 16 adc_clk ticks). ptr always points to first 1.
354 else if(fdt_elapsed && ~temp_buffer_reset)
355 // fdt_elapsed. If we didn't receive a 1 yet, ptr will be at 9 and not yet fixed. Otherwise temp_buffer_reset will be 1 already.
356 begin
357 // wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
358 // at intervals of 8 * 16 = 128 adc_clk ticks intervals (as defined in ISO14443-3)
359 if(ssp_dout) temp_buffer_reset = 1'b1;
360 if(mod_sig_ptr == 5'd2) mod_sig_ptr <= 5'd9; // still nothing received, need to go for the next interval
361 else mod_sig_ptr <= mod_sig_ptr - 1; // decrease buffer.
362 end
363 else
364 begin
365 if(~mod_sig_buf[mod_sig_ptr-1] && ~mod_sig_buf[mod_sig_ptr+1]) mod_sig = 1'b0;
366 // finally, assign the delayed signal:
367 else mod_sig = mod_sig_buf[mod_sig_ptr];
368 end
369 end
370
371 //-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
372 // Communication to ARM (SSP Clock and data)
373 // SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
374 if(mod_type == `SNIFFER)
375 begin
376 if(negedge_cnt[2:0] == 3'b100)
377 ssp_clk <= 1'b0;
378
379 if(negedge_cnt[2:0] == 3'b000)
380 begin
381 ssp_clk <= 1'b1;
382 // Don't shift if we just loaded new data, obviously.
383 if(negedge_cnt[5:0] != 6'd0)
384 begin
385 to_arm[7:1] <= to_arm[6:0];
386 end
387 end
388
389 if(negedge_cnt[5:4] == 2'b00)
390 ssp_frame = 1'b1;
391 else
392 ssp_frame = 1'b0;
393
394 bit_to_arm = to_arm[7];
395 end
396 else
397 //-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
398 // Communication to ARM (SSP Clock and data)
399 // all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
400 begin
401 if(negedge_cnt[3:0] == 4'b1000) ssp_clk <= 1'b0;
402
403 if(negedge_cnt[3:0] == 4'b0111)
404 begin
405 // if(ssp_frame_counter == 3'd7) ssp_frame_counter <= 3'd0;
406 // else ssp_frame_counter <= ssp_frame_counter + 1;
407 if (negedge_cnt[6:4] == 3'b000) ssp_frame = 1'b1;
408 else ssp_frame = 1'b0;
409 end
410 // ssp_frame = (ssp_frame_counter == 3'd7);
411
412 if(negedge_cnt[3:0] == 4'b0000)
413 begin
414 ssp_clk <= 1'b1;
415 // Don't shift if we just loaded new data, obviously.
416 if(negedge_cnt[6:0] != 7'd0)
417 begin
418 to_arm[7:1] <= to_arm[6:0];
419 end
420 end
421
422 if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
423 // transmit timing information
424 bit_to_arm = to_arm[7];
425 else
426 // transmit data or fdt_indicator
427 bit_to_arm = sendbit;
428 end
429
430 end //always @(negedge adc_clk)
431
432 assign ssp_din = bit_to_arm;
433
434
435 // Subcarrier (adc_clk/16, for TAGSIM_MOD only).
436 wire sub_carrier;
437 assign sub_carrier = ~sub_carrier_cnt[3];
438
439 // in READER_MOD: drop carrier for mod_sig_coil==1 (pause); in READER_LISTEN: carrier always on; in other modes: carrier always off
440 assign pwr_hi = (ck_1356megb & (((mod_type == `READER_MOD) & ~mod_sig_coil) || (mod_type == `READER_LISTEN)));
441
442
443 // Enable HF antenna drivers:
444 assign pwr_oe1 = 1'b0;
445 assign pwr_oe3 = 1'b0;
446
447 // TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
448 // for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
449 // for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
450 assign pwr_oe4 = ~(mod_sig_coil & sub_carrier & (mod_type == `TAGSIM_MOD));
451
452 // This is all LF, so doesn't matter.
453 assign pwr_oe2 = 1'b0;
454 assign pwr_lo = 1'b0;
455
456
457 assign dbg = negedge_cnt[3];
458
459 endmodule
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