First try att merging with head
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18 // split into two routines so we can avoid timing issues after sending commands //
19 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
20 {
21 uint8_t *dest = (uint8_t *)BigBuf;
22 int n = sizeof(BigBuf);
23 int i;
24
25 memset(dest, 0, n);
26 i = 0;
27 for(;;) {
28 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
29 AT91C_BASE_SSC->SSC_THR = 0x43;
30 LED_D_ON();
31 }
32 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
33 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
34 LED_D_OFF();
35 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
36 continue;
37 else
38 trigger_threshold = -1;
39 if (++i >= n) break;
40 }
41 }
42 if(!silent)
43 {
44 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
45 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
46
47 }
48 }
49 void DoAcquisition125k(int trigger_threshold)
50 {
51 DoAcquisition125k_internal(trigger_threshold, false);
52 }
53
54 //void SetupToAcquireRawAdcSamples(int divisor)
55 void LFSetupFPGAForADC(int divisor, bool lf_field)
56 {
57 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
58 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
59 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
60 else if (divisor == 0)
61 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
62 else
63 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
64
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
66
67 // Connect the A/D to the peak-detected low-frequency path.
68 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
69 // Give it a bit of time for the resonant antenna to settle.
70 SpinDelay(50);
71 // Now set up the SSC to get the ADC samples that are now streaming at us.
72 FpgaSetupSsc();
73 }
74
75 void AcquireRawAdcSamples125k(int divisor)
76 {
77 LFSetupFPGAForADC(divisor, true);
78 // Now call the acquisition routine
79 DoAcquisition125k_internal(-1,false);
80 }
81 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
82 {
83 LFSetupFPGAForADC(divisor, false);
84 DoAcquisition125k(trigger_threshold, false);
85 }
86
87
88 }
89
90 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
91 {
92 int at134khz;
93
94 /* Make sure the tag is reset */
95 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
96 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
97 SpinDelay(2500);
98
99 // see if 'h' was specified
100 if (command[strlen((char *) command) - 1] == 'h')
101 at134khz = TRUE;
102 else
103 at134khz = FALSE;
104
105 if (at134khz)
106 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
107 else
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
109
110 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
111
112 // Give it a bit of time for the resonant antenna to settle.
113 SpinDelay(50);
114 // And a little more time for the tag to fully power up
115 SpinDelay(2000);
116
117 // Now set up the SSC to get the ADC samples that are now streaming at us.
118 FpgaSetupSsc();
119
120 // now modulate the reader field
121 while(*command != '\0' && *command != ' ') {
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
123 LED_D_OFF();
124 SpinDelayUs(delay_off);
125 if (at134khz)
126 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
127 else
128 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
129
130 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
131 LED_D_ON();
132 if(*(command++) == '0')
133 SpinDelayUs(period_0);
134 else
135 SpinDelayUs(period_1);
136 }
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
138 LED_D_OFF();
139 SpinDelayUs(delay_off);
140 if (at134khz)
141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
142 else
143 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
144
145 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
146
147 // now do the read
148 DoAcquisition125k(-1);
149 }
150
151 /* blank r/w tag data stream
152 ...0000000000000000 01111111
153 1010101010101010101010101010101010101010101010101010101010101010
154 0011010010100001
155 01111111
156 101010101010101[0]000...
157
158 [5555fe852c5555555555555555fe0000]
159 */
160 void ReadTItag(void)
161 {
162 // some hardcoded initial params
163 // when we read a TI tag we sample the zerocross line at 2Mhz
164 // TI tags modulate a 1 as 16 cycles of 123.2Khz
165 // TI tags modulate a 0 as 16 cycles of 134.2Khz
166 #define FSAMPLE 2000000
167 #define FREQLO 123200
168 #define FREQHI 134200
169
170 signed char *dest = (signed char *)BigBuf;
171 int n = sizeof(BigBuf);
172 // int *dest = GraphBuffer;
173 // int n = GraphTraceLen;
174
175 // 128 bit shift register [shift3:shift2:shift1:shift0]
176 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
177
178 int i, cycles=0, samples=0;
179 // how many sample points fit in 16 cycles of each frequency
180 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
181 // when to tell if we're close enough to one freq or another
182 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
183
184 // TI tags charge at 134.2Khz
185 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
186 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
187
188 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
189 // connects to SSP_DIN and the SSP_DOUT logic level controls
190 // whether we're modulating the antenna (high)
191 // or listening to the antenna (low)
192 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
193
194 // get TI tag data into the buffer
195 AcquireTiType();
196
197 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
198
199 for (i=0; i<n-1; i++) {
200 // count cycles by looking for lo to hi zero crossings
201 if ( (dest[i]<0) && (dest[i+1]>0) ) {
202 cycles++;
203 // after 16 cycles, measure the frequency
204 if (cycles>15) {
205 cycles=0;
206 samples=i-samples; // number of samples in these 16 cycles
207
208 // TI bits are coming to us lsb first so shift them
209 // right through our 128 bit right shift register
210 shift0 = (shift0>>1) | (shift1 << 31);
211 shift1 = (shift1>>1) | (shift2 << 31);
212 shift2 = (shift2>>1) | (shift3 << 31);
213 shift3 >>= 1;
214
215 // check if the cycles fall close to the number
216 // expected for either the low or high frequency
217 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
218 // low frequency represents a 1
219 shift3 |= (1<<31);
220 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
221 // high frequency represents a 0
222 } else {
223 // probably detected a gay waveform or noise
224 // use this as gaydar or discard shift register and start again
225 shift3 = shift2 = shift1 = shift0 = 0;
226 }
227 samples = i;
228
229 // for each bit we receive, test if we've detected a valid tag
230
231 // if we see 17 zeroes followed by 6 ones, we might have a tag
232 // remember the bits are backwards
233 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
234 // if start and end bytes match, we have a tag so break out of the loop
235 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
236 cycles = 0xF0B; //use this as a flag (ugly but whatever)
237 break;
238 }
239 }
240 }
241 }
242 }
243
244 // if flag is set we have a tag
245 if (cycles!=0xF0B) {
246 DbpString("Info: No valid tag detected.");
247 } else {
248 // put 64 bit data into shift1 and shift0
249 shift0 = (shift0>>24) | (shift1 << 8);
250 shift1 = (shift1>>24) | (shift2 << 8);
251
252 // align 16 bit crc into lower half of shift2
253 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
254
255 // if r/w tag, check ident match
256 if ( shift3&(1<<15) ) {
257 DbpString("Info: TI tag is rewriteable");
258 // only 15 bits compare, last bit of ident is not valid
259 if ( ((shift3>>16)^shift0)&0x7fff ) {
260 DbpString("Error: Ident mismatch!");
261 } else {
262 DbpString("Info: TI tag ident is valid");
263 }
264 } else {
265 DbpString("Info: TI tag is readonly");
266 }
267
268 // WARNING the order of the bytes in which we calc crc below needs checking
269 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
270 // bytes in reverse or something
271 // calculate CRC
272 uint32_t crc=0;
273
274 crc = update_crc16(crc, (shift0)&0xff);
275 crc = update_crc16(crc, (shift0>>8)&0xff);
276 crc = update_crc16(crc, (shift0>>16)&0xff);
277 crc = update_crc16(crc, (shift0>>24)&0xff);
278 crc = update_crc16(crc, (shift1)&0xff);
279 crc = update_crc16(crc, (shift1>>8)&0xff);
280 crc = update_crc16(crc, (shift1>>16)&0xff);
281 crc = update_crc16(crc, (shift1>>24)&0xff);
282
283 Dbprintf("Info: Tag data: %x%08x, crc=%x",
284 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
285 if (crc != (shift2&0xffff)) {
286 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
287 } else {
288 DbpString("Info: CRC is good");
289 }
290 }
291 }
292
293 void WriteTIbyte(uint8_t b)
294 {
295 int i = 0;
296
297 // modulate 8 bits out to the antenna
298 for (i=0; i<8; i++)
299 {
300 if (b&(1<<i)) {
301 // stop modulating antenna
302 LOW(GPIO_SSC_DOUT);
303 SpinDelayUs(1000);
304 // modulate antenna
305 HIGH(GPIO_SSC_DOUT);
306 SpinDelayUs(1000);
307 } else {
308 // stop modulating antenna
309 LOW(GPIO_SSC_DOUT);
310 SpinDelayUs(300);
311 // modulate antenna
312 HIGH(GPIO_SSC_DOUT);
313 SpinDelayUs(1700);
314 }
315 }
316 }
317
318 void AcquireTiType(void)
319 {
320 int i, j, n;
321 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
322 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
323 #define TIBUFLEN 1250
324
325 // clear buffer
326 memset(BigBuf,0,sizeof(BigBuf));
327
328 // Set up the synchronous serial port
329 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
330 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
331
332 // steal this pin from the SSP and use it to control the modulation
333 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
334 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
335
336 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
337 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
338
339 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
340 // 48/2 = 24 MHz clock must be divided by 12
341 AT91C_BASE_SSC->SSC_CMR = 12;
342
343 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
344 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
345 AT91C_BASE_SSC->SSC_TCMR = 0;
346 AT91C_BASE_SSC->SSC_TFMR = 0;
347
348 LED_D_ON();
349
350 // modulate antenna
351 HIGH(GPIO_SSC_DOUT);
352
353 // Charge TI tag for 50ms.
354 SpinDelay(50);
355
356 // stop modulating antenna and listen
357 LOW(GPIO_SSC_DOUT);
358
359 LED_D_OFF();
360
361 i = 0;
362 for(;;) {
363 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
364 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
365 i++; if(i >= TIBUFLEN) break;
366 }
367 WDT_HIT();
368 }
369
370 // return stolen pin to SSP
371 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
372 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
373
374 char *dest = (char *)BigBuf;
375 n = TIBUFLEN*32;
376 // unpack buffer
377 for (i=TIBUFLEN-1; i>=0; i--) {
378 for (j=0; j<32; j++) {
379 if(BigBuf[i] & (1 << j)) {
380 dest[--n] = 1;
381 } else {
382 dest[--n] = -1;
383 }
384 }
385 }
386 }
387
388 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
389 // if crc provided, it will be written with the data verbatim (even if bogus)
390 // if not provided a valid crc will be computed from the data and written.
391 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
392 {
393 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
394 if(crc == 0) {
395 crc = update_crc16(crc, (idlo)&0xff);
396 crc = update_crc16(crc, (idlo>>8)&0xff);
397 crc = update_crc16(crc, (idlo>>16)&0xff);
398 crc = update_crc16(crc, (idlo>>24)&0xff);
399 crc = update_crc16(crc, (idhi)&0xff);
400 crc = update_crc16(crc, (idhi>>8)&0xff);
401 crc = update_crc16(crc, (idhi>>16)&0xff);
402 crc = update_crc16(crc, (idhi>>24)&0xff);
403 }
404 Dbprintf("Writing to tag: %x%08x, crc=%x",
405 (unsigned int) idhi, (unsigned int) idlo, crc);
406
407 // TI tags charge at 134.2Khz
408 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
409 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
410 // connects to SSP_DIN and the SSP_DOUT logic level controls
411 // whether we're modulating the antenna (high)
412 // or listening to the antenna (low)
413 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
414 LED_A_ON();
415
416 // steal this pin from the SSP and use it to control the modulation
417 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
418 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
419
420 // writing algorithm:
421 // a high bit consists of a field off for 1ms and field on for 1ms
422 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
423 // initiate a charge time of 50ms (field on) then immediately start writing bits
424 // start by writing 0xBB (keyword) and 0xEB (password)
425 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
426 // finally end with 0x0300 (write frame)
427 // all data is sent lsb firts
428 // finish with 15ms programming time
429
430 // modulate antenna
431 HIGH(GPIO_SSC_DOUT);
432 SpinDelay(50); // charge time
433
434 WriteTIbyte(0xbb); // keyword
435 WriteTIbyte(0xeb); // password
436 WriteTIbyte( (idlo )&0xff );
437 WriteTIbyte( (idlo>>8 )&0xff );
438 WriteTIbyte( (idlo>>16)&0xff );
439 WriteTIbyte( (idlo>>24)&0xff );
440 WriteTIbyte( (idhi )&0xff );
441 WriteTIbyte( (idhi>>8 )&0xff );
442 WriteTIbyte( (idhi>>16)&0xff );
443 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
444 WriteTIbyte( (crc )&0xff ); // crc lo
445 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
446 WriteTIbyte(0x00); // write frame lo
447 WriteTIbyte(0x03); // write frame hi
448 HIGH(GPIO_SSC_DOUT);
449 SpinDelay(50); // programming time
450
451 LED_A_OFF();
452
453 // get TI tag data into the buffer
454 AcquireTiType();
455
456 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
457 DbpString("Now use tiread to check");
458 }
459
460 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
461 {
462 int i;
463 uint8_t *tab = (uint8_t *)BigBuf;
464
465 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
466 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
467
468 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
469
470 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
471 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
472
473 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
474 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
475
476 i = 0;
477 for(;;) {
478 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
479 if(BUTTON_PRESS()) {
480 DbpString("Stopped");
481 return;
482 }
483 WDT_HIT();
484 }
485
486 if (ledcontrol)
487 LED_D_ON();
488
489 if(tab[i])
490 OPEN_COIL();
491 else
492 SHORT_COIL();
493
494 if (ledcontrol)
495 LED_D_OFF();
496
497 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
498 if(BUTTON_PRESS()) {
499 DbpString("Stopped");
500 return;
501 }
502 WDT_HIT();
503 }
504
505 i++;
506 if(i == period) {
507 i = 0;
508 if (gap) {
509 SHORT_COIL();
510 SpinDelayUs(gap);
511 }
512 }
513 }
514 }
515
516 #define DEBUG_FRAME_CONTENTS 1
517 void SimulateTagLowFrequencyBidir(int divisor, int t0)
518 {
519 }
520
521 // compose fc/8 fc/10 waveform
522 static void fc(int c, int *n) {
523 uint8_t *dest = (uint8_t *)BigBuf;
524 int idx;
525
526 // for when we want an fc8 pattern every 4 logical bits
527 if(c==0) {
528 dest[((*n)++)]=1;
529 dest[((*n)++)]=1;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 dest[((*n)++)]=0;
533 dest[((*n)++)]=0;
534 dest[((*n)++)]=0;
535 dest[((*n)++)]=0;
536 }
537 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
538 if(c==8) {
539 for (idx=0; idx<6; idx++) {
540 dest[((*n)++)]=1;
541 dest[((*n)++)]=1;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 dest[((*n)++)]=0;
546 dest[((*n)++)]=0;
547 dest[((*n)++)]=0;
548 }
549 }
550
551 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
552 if(c==10) {
553 for (idx=0; idx<5; idx++) {
554 dest[((*n)++)]=1;
555 dest[((*n)++)]=1;
556 dest[((*n)++)]=1;
557 dest[((*n)++)]=0;
558 dest[((*n)++)]=0;
559 dest[((*n)++)]=0;
560 dest[((*n)++)]=0;
561 dest[((*n)++)]=0;
562 dest[((*n)++)]=0;
563 dest[((*n)++)]=0;
564 }
565 }
566 }
567
568 // prepare a waveform pattern in the buffer based on the ID given then
569 // simulate a HID tag until the button is pressed
570 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
571 {
572 int n=0, i=0;
573 /*
574 HID tag bitstream format
575 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
576 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
577 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
578 A fc8 is inserted before every 4 bits
579 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
580 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
581 */
582
583 if (hi>0xFFF) {
584 DbpString("Tags can only have 44 bits.");
585 return;
586 }
587 fc(0,&n);
588 // special start of frame marker containing invalid bit sequences
589 fc(8, &n); fc(8, &n); // invalid
590 fc(8, &n); fc(10, &n); // logical 0
591 fc(10, &n); fc(10, &n); // invalid
592 fc(8, &n); fc(10, &n); // logical 0
593
594 WDT_HIT();
595 // manchester encode bits 43 to 32
596 for (i=11; i>=0; i--) {
597 if ((i%4)==3) fc(0,&n);
598 if ((hi>>i)&1) {
599 fc(10, &n); fc(8, &n); // low-high transition
600 } else {
601 fc(8, &n); fc(10, &n); // high-low transition
602 }
603 }
604
605 WDT_HIT();
606 // manchester encode bits 31 to 0
607 for (i=31; i>=0; i--) {
608 if ((i%4)==3) fc(0,&n);
609 if ((lo>>i)&1) {
610 fc(10, &n); fc(8, &n); // low-high transition
611 } else {
612 fc(8, &n); fc(10, &n); // high-low transition
613 }
614 }
615
616 if (ledcontrol)
617 LED_A_ON();
618 SimulateTagLowFrequency(n, 0, ledcontrol);
619
620 if (ledcontrol)
621 LED_A_OFF();
622 }
623
624 size_t fsk_demod(uint8_t * dest, size_t size)
625 {
626 uint32_t last_transition = 0;
627 uint32_t idx = 1;
628
629 // we don't care about actual value, only if it's more or less than a
630 // threshold essentially we capture zero crossings for later analysis
631 uint8_t threshold_value = 127;
632
633 // sync to first lo-hi transition, and threshold
634
635 //Need to threshold first sample
636 if(dest[0] < threshold_value) dest[0] = 0;
637 else dest[0] = 1;
638
639 size_t numBits = 0;
640 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
641 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
642 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
643 for(idx = 1; idx < size; idx++) {
644 // threshold current value
645 if (dest[idx] < threshold_value) dest[idx] = 0;
646 else dest[idx] = 1;
647
648 // Check for 0->1 transition
649 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
650
651 if (idx-last_transition < 9) {
652 dest[numBits]=1;
653 } else {
654 dest[numBits]=0;
655 }
656 last_transition = idx;
657 numBits++;
658 }
659 }
660 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
661 }
662
663
664 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
665 {
666 uint8_t lastval=dest[0];
667 uint32_t idx=0;
668 size_t numBits=0;
669 uint32_t n=1;
670
671 for( idx=1; idx < size; idx++) {
672
673 if (dest[idx]==lastval) {
674 n++;
675 continue;
676 }
677 //if lastval was 1, we have a 1->0 crossing
678 if ( dest[idx-1] ) {
679 n=(n+1) / h2l_crossing_value;
680 } else {// 0->1 crossing
681 n=(n+1) / l2h_crossing_value;
682 }
683 if (n == 0) n = 1;
684
685 if(n < maxConsequtiveBits)
686 {
687 memset(dest+numBits, dest[idx-1] , n);
688 numBits += n;
689 }
690 n=0;
691 lastval=dest[idx];
692 }//end for
693
694 return numBits;
695
696 }
697 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
698 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
699 {
700 uint8_t *dest = (uint8_t *)BigBuf;
701
702 size_t size=0,idx=0; //, found=0;
703 uint32_t hi2=0, hi=0, lo=0;
704
705
706 while(!BUTTON_PRESS()) {
707
708 // Configure to go in 125Khz listen mode
709 LFSetupFPGAForADC(0, true)
710
711 WDT_HIT();
712 if (ledcontrol) LED_A_ON();
713
714 DoAcquisition125k_internal(true);
715 size = sizeof(BigBuf);
716
717 // FSK demodulator
718 size = fsk_demod(dest, size);
719 WDT_HIT();
720
721 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
722 // 1->0 : fc/8 in sets of 6
723 // 0->1 : fc/10 in sets of 5
724 size = aggregate_bits(dest,size, 6,5,5);
725
726 WDT_HIT();
727
728 // final loop, go over previously decoded manchester data and decode into usable tag ID
729 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
730 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
731 int numshifts = 0;
732 idx = 0;
733 while( idx + sizeof(frame_marker_mask) < size) {
734 // search for a start of frame marker
735 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
736 { // frame marker found
737 idx+=sizeof(frame_marker_mask);
738
739 while(dest[idx] != dest[idx+1] && idx < size-2)
740 { // Keep going until next frame marker (or error)
741 // Shift in a bit. Start by shifting high registers
742 hi2 = (hi2<<1)|(hi>>31);
743 hi = (hi<<1)|(lo>>31);
744 //Then, shift in a 0 or one into low
745 if (dest[idx] && !dest[idx+1]) // 1 0
746 lo=(lo<<1)|0;
747 else // 0 1
748 lo=(lo<<1)|
749 1;
750 numshifts ++;
751 idx += 2;
752 }
753 //Dbprintf("Num shifts: %d ", numshifts);
754 // Hopefully, we read a tag and hit upon the next frame marker
755 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
756 {
757 if (hi2 != 0){
758 Dbprintf("TAG ID: %x%08x%08x (%d)",
759 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
760 }
761 else {
762 Dbprintf("TAG ID: %x%08x (%d)",
763 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
764 }
765 }
766
767 // reset
768 hi2 = hi = lo = 0;
769 numshifts = 0;
770 }else
771 {
772 idx++;
773 }
774 }
775 WDT_HIT();
776
777 }
778 DbpString("Stopped");
779 if (ledcontrol) LED_A_OFF();
780 }
781
782 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
783 {
784 uint32_t num = 0;
785 for(int i = 0 ; i < numbits ; i++)
786 {
787 num = (num << 1) | (*src);
788 src++;
789 }
790 return num;
791 }
792
793
794 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
795 {
796 uint8_t *dest = (uint8_t *)BigBuf;
797
798 size_t size=0, idx=0;
799 uint32_t code=0, code2=0;
800
801
802 while(!BUTTON_PRESS()) {
803
804 // Configure to go in 125Khz listen mode
805 LFSetupFPGAForADC(0, true);
806
807 WDT_HIT();
808 if (ledcontrol) LED_A_ON();
809
810 DoAcquisition125k_internal(true);
811 size = sizeof(BigBuf);
812
813 // FSK demodulator
814 size = fsk_demod(dest, size);
815 WDT_HIT();
816
817 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
818 // 1->0 : fc/8 in sets of 7
819 // 0->1 : fc/10 in sets of 6
820 size = aggregate_bits(dest, size, 7,6,13);
821
822 WDT_HIT();
823
824 //Handle the data
825 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
826 for( idx=0; idx < size - 64; idx++) {
827
828 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
829
830 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
831 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
832 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
833 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
834 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
835 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
836 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
837 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
838
839 code = bytebits_to_byte(dest+idx,32);
840 code2 = bytebits_to_byte(dest+idx+32,32);
841
842 short version = bytebits_to_byte(dest+idx+14,4);
843 char unknown = bytebits_to_byte(dest+idx+19,8) ;
844 uint16_t number = bytebits_to_byte(dest+idx+36,9);
845
846 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
847 if (ledcontrol) LED_D_OFF();
848
849 // if we're only looking for one tag
850 if (findone){
851 LED_A_OFF();
852 return;
853 }
854 }
855 WDT_HIT();
856 }
857 DbpString("Stopped");
858 if (ledcontrol) LED_A_OFF();
859 }
860
861 /*------------------------------
862 * T5555/T5557/T5567 routines
863 *------------------------------
864 */
865
866 /* T55x7 configuration register definitions */
867 #define T55x7_POR_DELAY 0x00000001
868 #define T55x7_ST_TERMINATOR 0x00000008
869 #define T55x7_PWD 0x00000010
870 #define T55x7_MAXBLOCK_SHIFT 5
871 #define T55x7_AOR 0x00000200
872 #define T55x7_PSKCF_RF_2 0
873 #define T55x7_PSKCF_RF_4 0x00000400
874 #define T55x7_PSKCF_RF_8 0x00000800
875 #define T55x7_MODULATION_DIRECT 0
876 #define T55x7_MODULATION_PSK1 0x00001000
877 #define T55x7_MODULATION_PSK2 0x00002000
878 #define T55x7_MODULATION_PSK3 0x00003000
879 #define T55x7_MODULATION_FSK1 0x00004000
880 #define T55x7_MODULATION_FSK2 0x00005000
881 #define T55x7_MODULATION_FSK1a 0x00006000
882 #define T55x7_MODULATION_FSK2a 0x00007000
883 #define T55x7_MODULATION_MANCHESTER 0x00008000
884 #define T55x7_MODULATION_BIPHASE 0x00010000
885 #define T55x7_BITRATE_RF_8 0
886 #define T55x7_BITRATE_RF_16 0x00040000
887 #define T55x7_BITRATE_RF_32 0x00080000
888 #define T55x7_BITRATE_RF_40 0x000C0000
889 #define T55x7_BITRATE_RF_50 0x00100000
890 #define T55x7_BITRATE_RF_64 0x00140000
891 #define T55x7_BITRATE_RF_100 0x00180000
892 #define T55x7_BITRATE_RF_128 0x001C0000
893
894 /* T5555 (Q5) configuration register definitions */
895 #define T5555_ST_TERMINATOR 0x00000001
896 #define T5555_MAXBLOCK_SHIFT 0x00000001
897 #define T5555_MODULATION_MANCHESTER 0
898 #define T5555_MODULATION_PSK1 0x00000010
899 #define T5555_MODULATION_PSK2 0x00000020
900 #define T5555_MODULATION_PSK3 0x00000030
901 #define T5555_MODULATION_FSK1 0x00000040
902 #define T5555_MODULATION_FSK2 0x00000050
903 #define T5555_MODULATION_BIPHASE 0x00000060
904 #define T5555_MODULATION_DIRECT 0x00000070
905 #define T5555_INVERT_OUTPUT 0x00000080
906 #define T5555_PSK_RF_2 0
907 #define T5555_PSK_RF_4 0x00000100
908 #define T5555_PSK_RF_8 0x00000200
909 #define T5555_USE_PWD 0x00000400
910 #define T5555_USE_AOR 0x00000800
911 #define T5555_BITRATE_SHIFT 12
912 #define T5555_FAST_WRITE 0x00004000
913 #define T5555_PAGE_SELECT 0x00008000
914
915 /*
916 * Relevant times in microsecond
917 * To compensate antenna falling times shorten the write times
918 * and enlarge the gap ones.
919 */
920 #define START_GAP 250
921 #define WRITE_GAP 160
922 #define WRITE_0 144 // 192
923 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
924
925 // Write one bit to card
926 void T55xxWriteBit(int bit)
927 {
928 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
929 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
930 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
931 if (bit == 0)
932 SpinDelayUs(WRITE_0);
933 else
934 SpinDelayUs(WRITE_1);
935 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
936 SpinDelayUs(WRITE_GAP);
937 }
938
939 // Write one card block in page 0, no lock
940 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
941 {
942 unsigned int i;
943
944 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
945 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
946 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
947
948 // Give it a bit of time for the resonant antenna to settle.
949 // And for the tag to fully power up
950 SpinDelay(150);
951
952 // Now start writting
953 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
954 SpinDelayUs(START_GAP);
955
956 // Opcode
957 T55xxWriteBit(1);
958 T55xxWriteBit(0); //Page 0
959 if (PwdMode == 1){
960 // Pwd
961 for (i = 0x80000000; i != 0; i >>= 1)
962 T55xxWriteBit(Pwd & i);
963 }
964 // Lock bit
965 T55xxWriteBit(0);
966
967 // Data
968 for (i = 0x80000000; i != 0; i >>= 1)
969 T55xxWriteBit(Data & i);
970
971 // Block
972 for (i = 0x04; i != 0; i >>= 1)
973 T55xxWriteBit(Block & i);
974
975 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
976 // so wait a little more)
977 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
978 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
979 SpinDelay(20);
980 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
981 }
982
983 // Read one card block in page 0
984 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
985 {
986 uint8_t *dest = (uint8_t *)BigBuf;
987 int m=0, i=0;
988
989 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
990 m = sizeof(BigBuf);
991 // Clear destination buffer before sending the command
992 memset(dest, 128, m);
993 // Connect the A/D to the peak-detected low-frequency path.
994 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
995 // Now set up the SSC to get the ADC samples that are now streaming at us.
996 FpgaSetupSsc();
997
998 LED_D_ON();
999 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1000 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1001
1002 // Give it a bit of time for the resonant antenna to settle.
1003 // And for the tag to fully power up
1004 SpinDelay(150);
1005
1006 // Now start writting
1007 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1008 SpinDelayUs(START_GAP);
1009
1010 // Opcode
1011 T55xxWriteBit(1);
1012 T55xxWriteBit(0); //Page 0
1013 if (PwdMode == 1){
1014 // Pwd
1015 for (i = 0x80000000; i != 0; i >>= 1)
1016 T55xxWriteBit(Pwd & i);
1017 }
1018 // Lock bit
1019 T55xxWriteBit(0);
1020 // Block
1021 for (i = 0x04; i != 0; i >>= 1)
1022 T55xxWriteBit(Block & i);
1023
1024 // Turn field on to read the response
1025 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1026 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1027
1028 // Now do the acquisition
1029 i = 0;
1030 for(;;) {
1031 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1032 AT91C_BASE_SSC->SSC_THR = 0x43;
1033 }
1034 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1035 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1036 // we don't care about actual value, only if it's more or less than a
1037 // threshold essentially we capture zero crossings for later analysis
1038 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1039 i++;
1040 if (i >= m) break;
1041 }
1042 }
1043
1044 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1045 LED_D_OFF();
1046 DbpString("DONE!");
1047 }
1048
1049 // Read card traceability data (page 1)
1050 void T55xxReadTrace(void){
1051 uint8_t *dest = (uint8_t *)BigBuf;
1052 int m=0, i=0;
1053
1054 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1055 m = sizeof(BigBuf);
1056 // Clear destination buffer before sending the command
1057 memset(dest, 128, m);
1058 // Connect the A/D to the peak-detected low-frequency path.
1059 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1060 // Now set up the SSC to get the ADC samples that are now streaming at us.
1061 FpgaSetupSsc();
1062
1063 LED_D_ON();
1064 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1065 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1066
1067 // Give it a bit of time for the resonant antenna to settle.
1068 // And for the tag to fully power up
1069 SpinDelay(150);
1070
1071 // Now start writting
1072 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1073 SpinDelayUs(START_GAP);
1074
1075 // Opcode
1076 T55xxWriteBit(1);
1077 T55xxWriteBit(1); //Page 1
1078
1079 // Turn field on to read the response
1080 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1081 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1082
1083 // Now do the acquisition
1084 i = 0;
1085 for(;;) {
1086 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1087 AT91C_BASE_SSC->SSC_THR = 0x43;
1088 }
1089 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1090 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1091 i++;
1092 if (i >= m) break;
1093 }
1094 }
1095
1096 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1097 LED_D_OFF();
1098 DbpString("DONE!");
1099 }
1100
1101 /*-------------- Cloning routines -----------*/
1102 // Copy HID id to card and setup block 0 config
1103 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1104 {
1105 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1106 int last_block = 0;
1107
1108 if (longFMT){
1109 // Ensure no more than 84 bits supplied
1110 if (hi2>0xFFFFF) {
1111 DbpString("Tags can only have 84 bits.");
1112 return;
1113 }
1114 // Build the 6 data blocks for supplied 84bit ID
1115 last_block = 6;
1116 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1117 for (int i=0;i<4;i++) {
1118 if (hi2 & (1<<(19-i)))
1119 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1120 else
1121 data1 |= (1<<((3-i)*2)); // 0 -> 01
1122 }
1123
1124 data2 = 0;
1125 for (int i=0;i<16;i++) {
1126 if (hi2 & (1<<(15-i)))
1127 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1128 else
1129 data2 |= (1<<((15-i)*2)); // 0 -> 01
1130 }
1131
1132 data3 = 0;
1133 for (int i=0;i<16;i++) {
1134 if (hi & (1<<(31-i)))
1135 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1136 else
1137 data3 |= (1<<((15-i)*2)); // 0 -> 01
1138 }
1139
1140 data4 = 0;
1141 for (int i=0;i<16;i++) {
1142 if (hi & (1<<(15-i)))
1143 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1144 else
1145 data4 |= (1<<((15-i)*2)); // 0 -> 01
1146 }
1147
1148 data5 = 0;
1149 for (int i=0;i<16;i++) {
1150 if (lo & (1<<(31-i)))
1151 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1152 else
1153 data5 |= (1<<((15-i)*2)); // 0 -> 01
1154 }
1155
1156 data6 = 0;
1157 for (int i=0;i<16;i++) {
1158 if (lo & (1<<(15-i)))
1159 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1160 else
1161 data6 |= (1<<((15-i)*2)); // 0 -> 01
1162 }
1163 }
1164 else {
1165 // Ensure no more than 44 bits supplied
1166 if (hi>0xFFF) {
1167 DbpString("Tags can only have 44 bits.");
1168 return;
1169 }
1170
1171 // Build the 3 data blocks for supplied 44bit ID
1172 last_block = 3;
1173
1174 data1 = 0x1D000000; // load preamble
1175
1176 for (int i=0;i<12;i++) {
1177 if (hi & (1<<(11-i)))
1178 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1179 else
1180 data1 |= (1<<((11-i)*2)); // 0 -> 01
1181 }
1182
1183 data2 = 0;
1184 for (int i=0;i<16;i++) {
1185 if (lo & (1<<(31-i)))
1186 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1187 else
1188 data2 |= (1<<((15-i)*2)); // 0 -> 01
1189 }
1190
1191 data3 = 0;
1192 for (int i=0;i<16;i++) {
1193 if (lo & (1<<(15-i)))
1194 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1195 else
1196 data3 |= (1<<((15-i)*2)); // 0 -> 01
1197 }
1198 }
1199
1200 LED_D_ON();
1201 // Program the data blocks for supplied ID
1202 // and the block 0 for HID format
1203 T55xxWriteBlock(data1,1,0,0);
1204 T55xxWriteBlock(data2,2,0,0);
1205 T55xxWriteBlock(data3,3,0,0);
1206
1207 if (longFMT) { // if long format there are 6 blocks
1208 T55xxWriteBlock(data4,4,0,0);
1209 T55xxWriteBlock(data5,5,0,0);
1210 T55xxWriteBlock(data6,6,0,0);
1211 }
1212
1213 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1214 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1215 T55x7_MODULATION_FSK2a |
1216 last_block << T55x7_MAXBLOCK_SHIFT,
1217 0,0,0);
1218
1219 LED_D_OFF();
1220
1221 DbpString("DONE!");
1222 }
1223
1224 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1225 {
1226 int data1=0, data2=0; //up to six blocks for long format
1227
1228 data1 = hi; // load preamble
1229 data2 = lo;
1230
1231 LED_D_ON();
1232 // Program the data blocks for supplied ID
1233 // and the block 0 for HID format
1234 T55xxWriteBlock(data1,1,0,0);
1235 T55xxWriteBlock(data2,2,0,0);
1236
1237 //Config Block
1238 T55xxWriteBlock(0x00147040,0,0,0);
1239 LED_D_OFF();
1240
1241 DbpString("DONE!");
1242 }
1243
1244 // Define 9bit header for EM410x tags
1245 #define EM410X_HEADER 0x1FF
1246 #define EM410X_ID_LENGTH 40
1247
1248 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1249 {
1250 int i, id_bit;
1251 uint64_t id = EM410X_HEADER;
1252 uint64_t rev_id = 0; // reversed ID
1253 int c_parity[4]; // column parity
1254 int r_parity = 0; // row parity
1255 uint32_t clock = 0;
1256
1257 // Reverse ID bits given as parameter (for simpler operations)
1258 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1259 if (i < 32) {
1260 rev_id = (rev_id << 1) | (id_lo & 1);
1261 id_lo >>= 1;
1262 } else {
1263 rev_id = (rev_id << 1) | (id_hi & 1);
1264 id_hi >>= 1;
1265 }
1266 }
1267
1268 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1269 id_bit = rev_id & 1;
1270
1271 if (i % 4 == 0) {
1272 // Don't write row parity bit at start of parsing
1273 if (i)
1274 id = (id << 1) | r_parity;
1275 // Start counting parity for new row
1276 r_parity = id_bit;
1277 } else {
1278 // Count row parity
1279 r_parity ^= id_bit;
1280 }
1281
1282 // First elements in column?
1283 if (i < 4)
1284 // Fill out first elements
1285 c_parity[i] = id_bit;
1286 else
1287 // Count column parity
1288 c_parity[i % 4] ^= id_bit;
1289
1290 // Insert ID bit
1291 id = (id << 1) | id_bit;
1292 rev_id >>= 1;
1293 }
1294
1295 // Insert parity bit of last row
1296 id = (id << 1) | r_parity;
1297
1298 // Fill out column parity at the end of tag
1299 for (i = 0; i < 4; ++i)
1300 id = (id << 1) | c_parity[i];
1301
1302 // Add stop bit
1303 id <<= 1;
1304
1305 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1306 LED_D_ON();
1307
1308 // Write EM410x ID
1309 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1310 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1311
1312 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1313 if (card) {
1314 // Clock rate is stored in bits 8-15 of the card value
1315 clock = (card & 0xFF00) >> 8;
1316 Dbprintf("Clock rate: %d", clock);
1317 switch (clock)
1318 {
1319 case 32:
1320 clock = T55x7_BITRATE_RF_32;
1321 break;
1322 case 16:
1323 clock = T55x7_BITRATE_RF_16;
1324 break;
1325 case 0:
1326 // A value of 0 is assumed to be 64 for backwards-compatibility
1327 // Fall through...
1328 case 64:
1329 clock = T55x7_BITRATE_RF_64;
1330 break;
1331 default:
1332 Dbprintf("Invalid clock rate: %d", clock);
1333 return;
1334 }
1335
1336 // Writing configuration for T55x7 tag
1337 T55xxWriteBlock(clock |
1338 T55x7_MODULATION_MANCHESTER |
1339 2 << T55x7_MAXBLOCK_SHIFT,
1340 0, 0, 0);
1341 }
1342 else
1343 // Writing configuration for T5555(Q5) tag
1344 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1345 T5555_MODULATION_MANCHESTER |
1346 2 << T5555_MAXBLOCK_SHIFT,
1347 0, 0, 0);
1348
1349 LED_D_OFF();
1350 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1351 (uint32_t)(id >> 32), (uint32_t)id);
1352 }
1353
1354 // Clone Indala 64-bit tag by UID to T55x7
1355 void CopyIndala64toT55x7(int hi, int lo)
1356 {
1357
1358 //Program the 2 data blocks for supplied 64bit UID
1359 // and the block 0 for Indala64 format
1360 T55xxWriteBlock(hi,1,0,0);
1361 T55xxWriteBlock(lo,2,0,0);
1362 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1363 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1364 T55x7_MODULATION_PSK1 |
1365 2 << T55x7_MAXBLOCK_SHIFT,
1366 0, 0, 0);
1367 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1368 // T5567WriteBlock(0x603E1042,0);
1369
1370 DbpString("DONE!");
1371
1372 }
1373
1374 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1375 {
1376
1377 //Program the 7 data blocks for supplied 224bit UID
1378 // and the block 0 for Indala224 format
1379 T55xxWriteBlock(uid1,1,0,0);
1380 T55xxWriteBlock(uid2,2,0,0);
1381 T55xxWriteBlock(uid3,3,0,0);
1382 T55xxWriteBlock(uid4,4,0,0);
1383 T55xxWriteBlock(uid5,5,0,0);
1384 T55xxWriteBlock(uid6,6,0,0);
1385 T55xxWriteBlock(uid7,7,0,0);
1386 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1387 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1388 T55x7_MODULATION_PSK1 |
1389 7 << T55x7_MAXBLOCK_SHIFT,
1390 0,0,0);
1391 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1392 // T5567WriteBlock(0x603E10E2,0);
1393
1394 DbpString("DONE!");
1395
1396 }
1397
1398
1399 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1400 #define max(x,y) ( x<y ? y:x)
1401
1402 int DemodPCF7931(uint8_t **outBlocks) {
1403 uint8_t BitStream[256];
1404 uint8_t Blocks[8][16];
1405 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1406 int GraphTraceLen = sizeof(BigBuf);
1407 int i, j, lastval, bitidx, half_switch;
1408 int clock = 64;
1409 int tolerance = clock / 8;
1410 int pmc, block_done;
1411 int lc, warnings = 0;
1412 int num_blocks = 0;
1413 int lmin=128, lmax=128;
1414 uint8_t dir;
1415
1416 AcquireRawAdcSamples125k(0);
1417
1418 lmin = 64;
1419 lmax = 192;
1420
1421 i = 2;
1422
1423 /* Find first local max/min */
1424 if(GraphBuffer[1] > GraphBuffer[0]) {
1425 while(i < GraphTraceLen) {
1426 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1427 break;
1428 i++;
1429 }
1430 dir = 0;
1431 }
1432 else {
1433 while(i < GraphTraceLen) {
1434 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1435 break;
1436 i++;
1437 }
1438 dir = 1;
1439 }
1440
1441 lastval = i++;
1442 half_switch = 0;
1443 pmc = 0;
1444 block_done = 0;
1445
1446 for (bitidx = 0; i < GraphTraceLen; i++)
1447 {
1448 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1449 {
1450 lc = i - lastval;
1451 lastval = i;
1452
1453 // Switch depending on lc length:
1454 // Tolerance is 1/8 of clock rate (arbitrary)
1455 if (abs(lc-clock/4) < tolerance) {
1456 // 16T0
1457 if((i - pmc) == lc) { /* 16T0 was previous one */
1458 /* It's a PMC ! */
1459 i += (128+127+16+32+33+16)-1;
1460 lastval = i;
1461 pmc = 0;
1462 block_done = 1;
1463 }
1464 else {
1465 pmc = i;
1466 }
1467 } else if (abs(lc-clock/2) < tolerance) {
1468 // 32TO
1469 if((i - pmc) == lc) { /* 16T0 was previous one */
1470 /* It's a PMC ! */
1471 i += (128+127+16+32+33)-1;
1472 lastval = i;
1473 pmc = 0;
1474 block_done = 1;
1475 }
1476 else if(half_switch == 1) {
1477 BitStream[bitidx++] = 0;
1478 half_switch = 0;
1479 }
1480 else
1481 half_switch++;
1482 } else if (abs(lc-clock) < tolerance) {
1483 // 64TO
1484 BitStream[bitidx++] = 1;
1485 } else {
1486 // Error
1487 warnings++;
1488 if (warnings > 10)
1489 {
1490 Dbprintf("Error: too many detection errors, aborting.");
1491 return 0;
1492 }
1493 }
1494
1495 if(block_done == 1) {
1496 if(bitidx == 128) {
1497 for(j=0; j<16; j++) {
1498 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1499 64*BitStream[j*8+6]+
1500 32*BitStream[j*8+5]+
1501 16*BitStream[j*8+4]+
1502 8*BitStream[j*8+3]+
1503 4*BitStream[j*8+2]+
1504 2*BitStream[j*8+1]+
1505 BitStream[j*8];
1506 }
1507 num_blocks++;
1508 }
1509 bitidx = 0;
1510 block_done = 0;
1511 half_switch = 0;
1512 }
1513 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1514 else dir = 1;
1515 }
1516 if(bitidx==255)
1517 bitidx=0;
1518 warnings = 0;
1519 if(num_blocks == 4) break;
1520 }
1521 memcpy(outBlocks, Blocks, 16*num_blocks);
1522 return num_blocks;
1523 }
1524
1525 int IsBlock0PCF7931(uint8_t *Block) {
1526 // Assume RFU means 0 :)
1527 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1528 return 1;
1529 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1530 return 1;
1531 return 0;
1532 }
1533
1534 int IsBlock1PCF7931(uint8_t *Block) {
1535 // Assume RFU means 0 :)
1536 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1537 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1538 return 1;
1539
1540 return 0;
1541 }
1542
1543 #define ALLOC 16
1544
1545 void ReadPCF7931() {
1546 uint8_t Blocks[8][17];
1547 uint8_t tmpBlocks[4][16];
1548 int i, j, ind, ind2, n;
1549 int num_blocks = 0;
1550 int max_blocks = 8;
1551 int ident = 0;
1552 int error = 0;
1553 int tries = 0;
1554
1555 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1556
1557 do {
1558 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1559 n = DemodPCF7931((uint8_t**)tmpBlocks);
1560 if(!n)
1561 error++;
1562 if(error==10 && num_blocks == 0) {
1563 Dbprintf("Error, no tag or bad tag");
1564 return;
1565 }
1566 else if (tries==20 || error==10) {
1567 Dbprintf("Error reading the tag");
1568 Dbprintf("Here is the partial content");
1569 goto end;
1570 }
1571
1572 for(i=0; i<n; i++)
1573 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1574 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1575 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1576 if(!ident) {
1577 for(i=0; i<n; i++) {
1578 if(IsBlock0PCF7931(tmpBlocks[i])) {
1579 // Found block 0 ?
1580 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1581 // Found block 1!
1582 // \o/
1583 ident = 1;
1584 memcpy(Blocks[0], tmpBlocks[i], 16);
1585 Blocks[0][ALLOC] = 1;
1586 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1587 Blocks[1][ALLOC] = 1;
1588 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1589 // Debug print
1590 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1591 num_blocks = 2;
1592 // Handle following blocks
1593 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1594 if(j==n) j=0;
1595 if(j==i) break;
1596 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1597 Blocks[ind2][ALLOC] = 1;
1598 }
1599 break;
1600 }
1601 }
1602 }
1603 }
1604 else {
1605 for(i=0; i<n; i++) { // Look for identical block in known blocks
1606 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1607 for(j=0; j<max_blocks; j++) {
1608 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1609 // Found an identical block
1610 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1611 if(ind2 < 0)
1612 ind2 = max_blocks;
1613 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1614 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1615 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1616 Blocks[ind2][ALLOC] = 1;
1617 num_blocks++;
1618 if(num_blocks == max_blocks) goto end;
1619 }
1620 }
1621 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1622 if(ind2 > max_blocks)
1623 ind2 = 0;
1624 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1625 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1626 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1627 Blocks[ind2][ALLOC] = 1;
1628 num_blocks++;
1629 if(num_blocks == max_blocks) goto end;
1630 }
1631 }
1632 }
1633 }
1634 }
1635 }
1636 }
1637 tries++;
1638 if (BUTTON_PRESS()) return;
1639 } while (num_blocks != max_blocks);
1640 end:
1641 Dbprintf("-----------------------------------------");
1642 Dbprintf("Memory content:");
1643 Dbprintf("-----------------------------------------");
1644 for(i=0; i<max_blocks; i++) {
1645 if(Blocks[i][ALLOC]==1)
1646 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1647 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1648 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1649 else
1650 Dbprintf("<missing block %d>", i);
1651 }
1652 Dbprintf("-----------------------------------------");
1653
1654 return ;
1655 }
1656
1657
1658 //-----------------------------------
1659 // EM4469 / EM4305 routines
1660 //-----------------------------------
1661 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1662 #define FWD_CMD_WRITE 0xA
1663 #define FWD_CMD_READ 0x9
1664 #define FWD_CMD_DISABLE 0x5
1665
1666
1667 uint8_t forwardLink_data[64]; //array of forwarded bits
1668 uint8_t * forward_ptr; //ptr for forward message preparation
1669 uint8_t fwd_bit_sz; //forwardlink bit counter
1670 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1671
1672 //====================================================================
1673 // prepares command bits
1674 // see EM4469 spec
1675 //====================================================================
1676 //--------------------------------------------------------------------
1677 uint8_t Prepare_Cmd( uint8_t cmd ) {
1678 //--------------------------------------------------------------------
1679
1680 *forward_ptr++ = 0; //start bit
1681 *forward_ptr++ = 0; //second pause for 4050 code
1682
1683 *forward_ptr++ = cmd;
1684 cmd >>= 1;
1685 *forward_ptr++ = cmd;
1686 cmd >>= 1;
1687 *forward_ptr++ = cmd;
1688 cmd >>= 1;
1689 *forward_ptr++ = cmd;
1690
1691 return 6; //return number of emited bits
1692 }
1693
1694 //====================================================================
1695 // prepares address bits
1696 // see EM4469 spec
1697 //====================================================================
1698
1699 //--------------------------------------------------------------------
1700 uint8_t Prepare_Addr( uint8_t addr ) {
1701 //--------------------------------------------------------------------
1702
1703 register uint8_t line_parity;
1704
1705 uint8_t i;
1706 line_parity = 0;
1707 for(i=0;i<6;i++) {
1708 *forward_ptr++ = addr;
1709 line_parity ^= addr;
1710 addr >>= 1;
1711 }
1712
1713 *forward_ptr++ = (line_parity & 1);
1714
1715 return 7; //return number of emited bits
1716 }
1717
1718 //====================================================================
1719 // prepares data bits intreleaved with parity bits
1720 // see EM4469 spec
1721 //====================================================================
1722
1723 //--------------------------------------------------------------------
1724 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1725 //--------------------------------------------------------------------
1726
1727 register uint8_t line_parity;
1728 register uint8_t column_parity;
1729 register uint8_t i, j;
1730 register uint16_t data;
1731
1732 data = data_low;
1733 column_parity = 0;
1734
1735 for(i=0; i<4; i++) {
1736 line_parity = 0;
1737 for(j=0; j<8; j++) {
1738 line_parity ^= data;
1739 column_parity ^= (data & 1) << j;
1740 *forward_ptr++ = data;
1741 data >>= 1;
1742 }
1743 *forward_ptr++ = line_parity;
1744 if(i == 1)
1745 data = data_hi;
1746 }
1747
1748 for(j=0; j<8; j++) {
1749 *forward_ptr++ = column_parity;
1750 column_parity >>= 1;
1751 }
1752 *forward_ptr = 0;
1753
1754 return 45; //return number of emited bits
1755 }
1756
1757 //====================================================================
1758 // Forward Link send function
1759 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1760 // fwd_bit_count set with number of bits to be sent
1761 //====================================================================
1762 void SendForward(uint8_t fwd_bit_count) {
1763
1764 fwd_write_ptr = forwardLink_data;
1765 fwd_bit_sz = fwd_bit_count;
1766
1767 LED_D_ON();
1768
1769 //Field on
1770 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1771 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1772 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1773
1774 // Give it a bit of time for the resonant antenna to settle.
1775 // And for the tag to fully power up
1776 SpinDelay(150);
1777
1778 // force 1st mod pulse (start gap must be longer for 4305)
1779 fwd_bit_sz--; //prepare next bit modulation
1780 fwd_write_ptr++;
1781 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1782 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1783 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1784 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1785 SpinDelayUs(16*8); //16 cycles on (8us each)
1786
1787 // now start writting
1788 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1789 if(((*fwd_write_ptr++) & 1) == 1)
1790 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1791 else {
1792 //These timings work for 4469/4269/4305 (with the 55*8 above)
1793 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1794 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1795 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1796 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1797 SpinDelayUs(9*8); //16 cycles on (8us each)
1798 }
1799 }
1800 }
1801
1802 void EM4xLogin(uint32_t Password) {
1803
1804 uint8_t fwd_bit_count;
1805
1806 forward_ptr = forwardLink_data;
1807 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1808 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1809
1810 SendForward(fwd_bit_count);
1811
1812 //Wait for command to complete
1813 SpinDelay(20);
1814
1815 }
1816
1817 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1818
1819 uint8_t fwd_bit_count;
1820 uint8_t *dest = (uint8_t *)BigBuf;
1821 int m=0, i=0;
1822
1823 //If password mode do login
1824 if (PwdMode == 1) EM4xLogin(Pwd);
1825
1826 forward_ptr = forwardLink_data;
1827 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1828 fwd_bit_count += Prepare_Addr( Address );
1829
1830 m = sizeof(BigBuf);
1831 // Clear destination buffer before sending the command
1832 memset(dest, 128, m);
1833 // Connect the A/D to the peak-detected low-frequency path.
1834 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1835 // Now set up the SSC to get the ADC samples that are now streaming at us.
1836 FpgaSetupSsc();
1837
1838 SendForward(fwd_bit_count);
1839
1840 // Now do the acquisition
1841 i = 0;
1842 for(;;) {
1843 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1844 AT91C_BASE_SSC->SSC_THR = 0x43;
1845 }
1846 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1847 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1848 i++;
1849 if (i >= m) break;
1850 }
1851 }
1852 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1853 LED_D_OFF();
1854 }
1855
1856 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1857
1858 uint8_t fwd_bit_count;
1859
1860 //If password mode do login
1861 if (PwdMode == 1) EM4xLogin(Pwd);
1862
1863 forward_ptr = forwardLink_data;
1864 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1865 fwd_bit_count += Prepare_Addr( Address );
1866 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1867
1868 SendForward(fwd_bit_count);
1869
1870 //Wait for write to complete
1871 SpinDelay(20);
1872 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1873 LED_D_OFF();
1874 }
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