1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, Sept 2005
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
7 //-----------------------------------------------------------------------------
8 // Utility functions used in many places, not specific to any piece of code.
9 //-----------------------------------------------------------------------------
11 #include "proxmark3.h"
19 void print_result(char *name
, uint8_t *buf
, size_t len
) {
22 if ( len
% 16 == 0 ) {
23 for(; p
-buf
< len
; p
+= 16)
24 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
28 p
[0], p
[1], p
[2], p
[3], p
[4], p
[5], p
[6], p
[7],p
[8], p
[9], p
[10], p
[11], p
[12], p
[13], p
[14], p
[15]
32 for(; p
-buf
< len
; p
+= 8)
33 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name
, p
-buf
, len
, p
[0], p
[1], p
[2], p
[3], p
[4], p
[5], p
[6], p
[7]);
37 size_t nbytes(size_t nbits
) {
38 return (nbits
>> 3)+((nbits
% 8) > 0);
41 uint32_t SwapBits(uint32_t value
, int nrbits
) {
43 uint32_t newvalue
= 0;
44 for(i
= 0; i
< nrbits
; i
++) {
45 newvalue
^= ((value
>> i
) & 1) << (nrbits
- 1 - i
);
50 void num_to_bytes(uint64_t n
, size_t len
, uint8_t* dest
)
53 dest
[len
] = (uint8_t) n
;
58 uint64_t bytes_to_num(uint8_t* src
, size_t len
)
63 num
= (num
<< 8) | (*src
);
69 // RotateLeft - Ultralight, Desfire
70 void rol(uint8_t *data
, const size_t len
){
71 uint8_t first
= data
[0];
72 for (size_t i
= 0; i
< len
-1; i
++) {
77 void lsl (uint8_t *data
, size_t len
) {
78 for (size_t n
= 0; n
< len
- 1; n
++) {
79 data
[n
] = (data
[n
] << 1) | (data
[n
+1] >> 7);
84 int32_t le24toh (uint8_t data
[3])
86 return (data
[2] << 16) | (data
[1] << 8) | data
[0];
97 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
98 void LED(int led
, int ms
)
102 if (led
& LED_ORANGE
)
116 if (led
& LED_ORANGE
)
125 // Determine if a button is double clicked, single clicked,
126 // not clicked, or held down (for ms || 1sec)
127 // In general, don't use this function unless you expect a
128 // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
129 int BUTTON_CLICKED(int ms
)
131 // Up to 500ms in between clicks to mean a double click
132 int ticks
= (48000 * (ms
? ms
: 1000)) >> 10;
134 // If we're not even pressed, forget about it!
136 return BUTTON_NO_CLICK
;
138 // Borrow a PWM unit for my real-time clock
139 AT91C_BASE_PWMC
->PWMC_ENA
= PWM_CHANNEL(0);
140 // 48 MHz / 1024 gives 46.875 kHz
141 AT91C_BASE_PWMC_CH0
->PWMC_CMR
= PWM_CH_MODE_PRESCALER(10);
142 AT91C_BASE_PWMC_CH0
->PWMC_CDTYR
= 0;
143 AT91C_BASE_PWMC_CH0
->PWMC_CPRDR
= 0xffff;
145 uint16_t start
= AT91C_BASE_PWMC_CH0
->PWMC_CCNTR
;
150 uint16_t now
= AT91C_BASE_PWMC_CH0
->PWMC_CCNTR
;
152 // We haven't let off the button yet
155 // We just let it off!
160 // reset our timer for 500ms
161 start
= AT91C_BASE_PWMC_CH0
->PWMC_CCNTR
;
162 ticks
= (48000 * (500)) >> 10;
165 // Still haven't let it off
167 // Have we held down a full second?
168 if (now
== (uint16_t)(start
+ ticks
))
172 // We already let off, did we click again?
174 // Sweet, double click!
176 return BUTTON_DOUBLE_CLICK
;
178 // Have we ran out of time to double click?
180 if (now
== (uint16_t)(start
+ ticks
))
181 // At least we did a single click
182 return BUTTON_SINGLE_CLICK
;
187 // We should never get here
191 // Determine if a button is held down
192 int BUTTON_HELD(int ms
)
194 // If button is held for one second
195 int ticks
= (48000 * (ms
? ms
: 1000)) >> 10;
197 // If we're not even pressed, forget about it!
199 return BUTTON_NO_CLICK
;
201 // Borrow a PWM unit for my real-time clock
202 AT91C_BASE_PWMC
->PWMC_ENA
= PWM_CHANNEL(0);
203 // 48 MHz / 1024 gives 46.875 kHz
204 AT91C_BASE_PWMC_CH0
->PWMC_CMR
= PWM_CH_MODE_PRESCALER(10);
205 AT91C_BASE_PWMC_CH0
->PWMC_CDTYR
= 0;
206 AT91C_BASE_PWMC_CH0
->PWMC_CPRDR
= 0xffff;
208 uint16_t start
= AT91C_BASE_PWMC_CH0
->PWMC_CCNTR
;
212 uint16_t now
= AT91C_BASE_PWMC_CH0
->PWMC_CCNTR
;
214 // As soon as our button let go, we didn't hold long enough
216 return BUTTON_SINGLE_CLICK
;
218 // Have we waited the full second?
220 if (now
== (uint16_t)(start
+ ticks
))
226 // We should never get here
230 // attempt at high resolution microsecond timer
231 // beware: timer counts in 21.3uS increments (1024/48Mhz)
232 void SpinDelayUs(int us
)
234 int ticks
= (48*us
) >> 10;
236 // Borrow a PWM unit for my real-time clock
237 AT91C_BASE_PWMC
->PWMC_ENA
= PWM_CHANNEL(0);
238 // 48 MHz / 1024 gives 46.875 kHz
239 AT91C_BASE_PWMC_CH0
->PWMC_CMR
= PWM_CH_MODE_PRESCALER(10);
240 AT91C_BASE_PWMC_CH0
->PWMC_CDTYR
= 0;
241 AT91C_BASE_PWMC_CH0
->PWMC_CPRDR
= 0xffff;
243 uint16_t start
= AT91C_BASE_PWMC_CH0
->PWMC_CCNTR
;
246 uint16_t now
= AT91C_BASE_PWMC_CH0
->PWMC_CCNTR
;
247 if (now
== (uint16_t)(start
+ ticks
))
254 void SpinDelay(int ms
)
256 // convert to uS and call microsecond delay function
257 SpinDelayUs(ms
*1000);
260 /* Similar to FpgaGatherVersion this formats stored version information
261 * into a string representation. It takes a pointer to the struct version_information,
262 * verifies the magic properties, then stores a formatted string, prefixed by
265 void FormatVersionInformation(char *dst
, int len
, const char *prefix
, void *version_information
)
267 struct version_information
*v
= (struct version_information
*)version_information
;
269 strncat(dst
, prefix
, len
-1);
270 if(v
->magic
!= VERSION_INFORMATION_MAGIC
) {
271 strncat(dst
, "Missing/Invalid version information\n", len
- strlen(dst
) - 1);
274 if(v
->versionversion
!= 1) {
275 strncat(dst
, "Version information not understood\n", len
- strlen(dst
) - 1);
279 strncat(dst
, "Version information not available\n", len
- strlen(dst
) - 1);
283 strncat(dst
, v
->gitversion
, len
- strlen(dst
) - 1);
285 strncat(dst
, "-unclean", len
- strlen(dst
) - 1);
286 } else if(v
->clean
== 2) {
287 strncat(dst
, "-suspect", len
- strlen(dst
) - 1);
290 strncat(dst
, " ", len
- strlen(dst
) - 1);
291 strncat(dst
, v
->buildtime
, len
- strlen(dst
) - 1);
292 strncat(dst
, "\n", len
- strlen(dst
) - 1);
296 // -------------------------------------------------------------------------
298 // -------------------------------------------------------------------------
301 // ti = GetTickCount();
303 // ti = GetTickCount() - ti;
304 // Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
306 void StartTickCount()
308 // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
309 // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
310 uint16_t mainf
= AT91C_BASE_PMC
->PMC_MCFR
& 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
311 // set RealTimeCounter divider to count at 1kHz:
312 AT91C_BASE_RTTC
->RTTC_RTMR
= AT91C_RTTC_RTTRST
| ((256000 + (mainf
/2)) / mainf
);
313 // note: worst case precision is approx 2.5%
318 * Get the current count.
320 uint32_t RAMFUNC
GetTickCount(){
321 return AT91C_BASE_RTTC
->RTTC_RTVR
;// was * 2;
325 // -------------------------------------------------------------------------
326 // microseconds timer
327 // -------------------------------------------------------------------------
330 AT91C_BASE_PMC
->PMC_PCER
|= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
331 // AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
332 AT91C_BASE_TCB
->TCB_BMR
= AT91C_TCB_TC0XC0S_NONE
| AT91C_TCB_TC1XC1S_TIOA0
| AT91C_TCB_TC2XC2S_NONE
;
335 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
; // timer disable
336 AT91C_BASE_TC0
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV3_CLOCK
| // MCK(48MHz)/32 -- tick=1.5mks
337 AT91C_TC_WAVE
| AT91C_TC_WAVESEL_UP_AUTO
| AT91C_TC_ACPA_CLEAR
|
338 AT91C_TC_ACPC_SET
| AT91C_TC_ASWTRG_SET
;
339 AT91C_BASE_TC0
->TC_RA
= 1;
340 AT91C_BASE_TC0
->TC_RC
= 0xBFFF + 1; // 0xC000
342 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
; // timer disable
343 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_XC1
; // from timer 0
345 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
;
346 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
;
347 AT91C_BASE_TCB
->TCB_BCR
= 1;
351 uint32_t RAMFUNC
GetCountUS(){
352 return (AT91C_BASE_TC1
->TC_CV
* 0x8000) + ((AT91C_BASE_TC0
->TC_CV
* 2) / 3); //was /15) * 10);
356 static uint32_t GlobalUsCounter
= 0;
358 uint32_t RAMFUNC
GetDeltaCountUS(){
359 uint32_t g_cnt
= GetCountUS();
360 uint32_t g_res
= g_cnt
- GlobalUsCounter
;
361 GlobalUsCounter
= g_cnt
;
366 // -------------------------------------------------------------------------
367 // Timer for iso14443 commands. Uses ssp_clk from FPGA
368 // -------------------------------------------------------------------------
369 void StartCountSspClk()
371 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
) | (1 << AT91C_ID_TC1
) | (1 << AT91C_ID_TC2
); // Enable Clock to all timers
372 AT91C_BASE_TCB
->TCB_BMR
= AT91C_TCB_TC0XC0S_TIOA1
// XC0 Clock = TIOA1
373 | AT91C_TCB_TC1XC1S_NONE
// XC1 Clock = none
374 | AT91C_TCB_TC2XC2S_TIOA0
; // XC2 Clock = TIOA0
376 // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
377 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
; // disable TC1
378 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
// TC1 Clock = MCK(48MHz)/2 = 24MHz
379 | AT91C_TC_CPCSTOP
// Stop clock on RC compare
380 | AT91C_TC_EEVTEDG_RISING
// Trigger on rising edge of Event
381 | AT91C_TC_EEVT_TIOB
// Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
382 | AT91C_TC_ENETRG
// Enable external trigger event
383 | AT91C_TC_WAVESEL_UP
// Upmode without automatic trigger on RC compare
384 | AT91C_TC_WAVE
// Waveform Mode
385 | AT91C_TC_AEEVT_SET
// Set TIOA1 on external event
386 | AT91C_TC_ACPC_CLEAR
; // Clear TIOA1 on RC Compare
387 AT91C_BASE_TC1
->TC_RC
= 0x04; // RC Compare value = 0x04
389 // use TC0 to count TIOA1 pulses
390 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
; // disable TC0
391 AT91C_BASE_TC0
->TC_CMR
= AT91C_TC_CLKS_XC0
// TC0 clock = XC0 clock = TIOA1
392 | AT91C_TC_WAVE
// Waveform Mode
393 | AT91C_TC_WAVESEL_UP
// just count
394 | AT91C_TC_ACPA_CLEAR
// Clear TIOA0 on RA Compare
395 | AT91C_TC_ACPC_SET
; // Set TIOA0 on RC Compare
396 AT91C_BASE_TC0
->TC_RA
= 1; // RA Compare value = 1; pulse width to TC2
397 AT91C_BASE_TC0
->TC_RC
= 0; // RC Compare value = 0; increment TC2 on overflow
399 // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
400 AT91C_BASE_TC2
->TC_CCR
= AT91C_TC_CLKDIS
; // disable TC2
401 AT91C_BASE_TC2
->TC_CMR
= AT91C_TC_CLKS_XC2
// TC2 clock = XC2 clock = TIOA0
402 | AT91C_TC_WAVE
// Waveform Mode
403 | AT91C_TC_WAVESEL_UP
; // just count
405 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
; // enable TC0
406 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
; // enable TC1
407 AT91C_BASE_TC2
->TC_CCR
= AT91C_TC_CLKEN
; // enable TC2
410 // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14443 mode, otherwise SSC_FRAME and SSC_CLK signals would not be present
412 while(!(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_FRAME
)); // wait for ssp_frame to go high (start of frame)
413 while(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_FRAME
); // wait for ssp_frame to be low
414 while(!(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
)); // wait for ssp_clk to go high
415 // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
416 // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
417 AT91C_BASE_TCB
->TCB_BCR
= 1; // assert Sync (set all timers to 0 on next active clock edge)
418 // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
419 // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
420 // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
421 // (just started with the transfer of the 4th Bit).
422 // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
423 // we can use the counter.
424 while (AT91C_BASE_TC0
->TC_CV
< 0xFFFF);
425 // Note: needs one more SSP_CLK cycle (1.18 us) until TC2 resets. Don't call GetCountSspClk() that soon.
429 void ResetSspClk(void) {
430 //enable clock of timer and software trigger
431 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
432 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
433 AT91C_BASE_TC2
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
434 while (AT91C_BASE_TC2
->TC_CV
> 0);
438 uint32_t RAMFUNC
GetCountSspClk(){
440 tmp_count
= (AT91C_BASE_TC2
->TC_CV
<< 16) | AT91C_BASE_TC0
->TC_CV
;
441 if ((tmp_count
& 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
442 return (AT91C_BASE_TC2
->TC_CV
<< 16);
450 // -------------------------------------------------------------------------
451 // Timer for bitbanging, or LF stuff when you need a very precis timer
453 // -------------------------------------------------------------------------
454 void StartTicks(void){
455 //initialization of the timer
456 // tc1 is higher 0xFFFF0000
457 // tc0 is lower 0x0000FFFF
458 AT91C_BASE_PMC
->PMC_PCER
|= (1 << AT91C_ID_TC0
) | (1 << AT91C_ID_TC1
);
459 AT91C_BASE_TCB
->TCB_BMR
= AT91C_TCB_TC0XC0S_NONE
| AT91C_TCB_TC1XC1S_TIOA0
| AT91C_TCB_TC2XC2S_NONE
;
460 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
461 AT91C_BASE_TC0
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV3_CLOCK
| // MCK(48MHz) / 32
462 AT91C_TC_WAVE
| AT91C_TC_WAVESEL_UP_AUTO
| AT91C_TC_ACPA_CLEAR
|
463 AT91C_TC_ACPC_SET
| AT91C_TC_ASWTRG_SET
;
464 AT91C_BASE_TC0
->TC_RA
= 1;
465 AT91C_BASE_TC0
->TC_RC
= 0;
467 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
; // timer disable
468 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_XC1
; // from TC0
470 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
471 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
472 AT91C_BASE_TCB
->TCB_BCR
= 1;
474 // wait until timer becomes zero.
475 while (AT91C_BASE_TC1
->TC_CV
> 0);
479 // Wait - Spindelay in ticks.
480 // if called with a high number, this will trigger the WDT...
481 void WaitTicks(uint32_t ticks
){
482 if ( ticks
== 0 ) return;
484 while (GET_TICKS
< ticks
);
488 // Wait / Spindelay in us (microseconds)
490 void WaitUS(uint16_t us
){
491 if ( us
== 0 ) return;
492 WaitTicks( (uint32_t)(us
* 1.5) );
496 void WaitMS(uint16_t ms
){
498 WaitTicks( (uint32_t)(ms
* 1500) );
502 // Starts Clock and waits until its reset
503 void ResetTicks(void){
504 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
505 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
506 while (AT91C_BASE_TC1
->TC_CV
> 0);
510 void ResetTimer(AT91PS_TC timer
){
511 timer
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
512 while(timer
->TC_CV
> 0) ;
517 void StopTicks(void){
518 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
519 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
523 static uint64_t next_random
= 1;
525 /* Generates a (non-cryptographically secure) 32-bit random number.
527 * We don't have an implementation of the "rand" function or a clock to seed it
528 * with, so we just call GetTickCount the first time to seed ourselves.
531 if (next_random
== 1) {
532 next_random
= GetTickCount();
535 next_random
= next_random
* 6364136223846793005 + 1;
536 return (uint32_t)(next_random
>> 32) % 0xffffffff;