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1 `include "lo_read.v"

2 /*

3 pck0 - input main 24Mhz clock (PLL / 4)

4 [7:0] adc_d - input data from A/D converter

5 lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)

7 pwr_lo - output to coil drivers (ssp_clk / 8)

8 adc_clk - output A/D clock signal

9 ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)

10 ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)

11 ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )

13 ck_1356meg - input unused

14 ck_1356megb - input unused

15 ssp_dout - input unused

16 cross_hi - input unused

17 cross_lo - input unused

19 pwr_hi - output unused, tied low

20 pwr_oe1 - output unused, undefined

21 pwr_oe2 - output unused, undefined

22 pwr_oe3 - output unused, undefined

23 pwr_oe4 - output unused, undefined

24 dbg - output alias for adc_clk

25 */

27 module testbed_lo_read;

28 reg pck0;

29 reg [7:0] adc_d;

30 reg lo_is_125khz;

31 reg [15:0] divisor;

33 wire pwr_lo;

34 wire adc_clk;

35 wire ck_1356meg;

36 wire ck_1356megb;

37 wire ssp_frame;

38 wire ssp_din;

39 wire ssp_clk;

40 reg ssp_dout;

41 wire pwr_hi;

42 wire pwr_oe1;

43 wire pwr_oe2;

44 wire pwr_oe3;

45 wire pwr_oe4;

46 wire cross_lo;

47 wire cross_hi;

48 wire dbg;

50 lo_read #(5,10) dut(

51 .pck0(pck0),

52 .ck_1356meg(ck_1356meg),

53 .ck_1356megb(ck_1356megb),

54 .pwr_lo(pwr_lo),

55 .pwr_hi(pwr_hi),

56 .pwr_oe1(pwr_oe1),

57 .pwr_oe2(pwr_oe2),

58 .pwr_oe3(pwr_oe3),

59 .pwr_oe4(pwr_oe4),

60 .adc_d(adc_d),

61 .adc_clk(adc_clk),

62 .ssp_frame(ssp_frame),

63 .ssp_din(ssp_din),

64 .ssp_dout(ssp_dout),

65 .ssp_clk(ssp_clk),

66 .cross_hi(cross_hi),

67 .cross_lo(cross_lo),

68 .dbg(dbg),

69 .lo_is_125khz(lo_is_125khz),

70 .divisor(divisor)

71 );

73 integer idx, i, adc_val=8;

75 // main clock

76 always #5 pck0 = !pck0;

78 task crank_dut;

79 begin

80 @(posedge adc_clk) ;

81 adc_d = adc_val;

82 adc_val = (adc_val *2) + 53;

83 end

84 endtask

86 initial begin

88 // init inputs

89 pck0 = 0;

90 adc_d = 0;

91 ssp_dout = 0;

92 lo_is_125khz = 1;

93 divisor = 255; //min 16, 95=125Khz, max 255

95 // simulate 4 A/D cycles at 125Khz

96 for (i = 0 ; i < 8 ; i = i + 1) begin

97 crank_dut;

98 end

99 $finish;

100 end

101 endmodule // main