+++ /dev/null
-//-----------------------------------------------------------------------------\r
-// Routines to load the FPGA image, and then to configure the FPGA's major\r
-// mode once it is configured.\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-#include <proxmark3.h>\r
-#include "apps.h"\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the Serial Peripheral Interface as master\r
-// Used to write the FPGA config word\r
-// May also be used to write to other SPI attached devices like an LCD\r
-//-----------------------------------------------------------------------------\r
-void SetupSpi(int mode)\r
-{\r
- // PA10 -> SPI_NCS2 chip select (LCD)\r
- // PA11 -> SPI_NCS0 chip select (FPGA)\r
- // PA12 -> SPI_MISO Master-In Slave-Out\r
- // PA13 -> SPI_MOSI Master-Out Slave-In\r
- // PA14 -> SPI_SPCK Serial Clock\r
-\r
- // Disable PIO control of the following pins, allows use by the SPI peripheral\r
- PIO_DISABLE = (1 << GPIO_NCS0) |\r
- (1 << GPIO_NCS2) |\r
- (1 << GPIO_MISO) |\r
- (1 << GPIO_MOSI) |\r
- (1 << GPIO_SPCK);\r
-\r
- PIO_PERIPHERAL_A_SEL = (1 << GPIO_NCS0) |\r
- (1 << GPIO_MISO) |\r
- (1 << GPIO_MOSI) |\r
- (1 << GPIO_SPCK);\r
-\r
- PIO_PERIPHERAL_B_SEL = (1 << GPIO_NCS2);\r
-\r
- //enable the SPI Peripheral clock\r
- PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
- // Enable SPI\r
- SPI_CONTROL = SPI_CONTROL_ENABLE;\r
-\r
- switch (mode) {\r
- case SPI_FPGA_MODE:\r
- SPI_MODE =\r
- ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)\r
- (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
- ( 0 << 7) | // Local Loopback Disabled\r
- ( 1 << 4) | // Mode Fault Detection disabled\r
- ( 0 << 2) | // Chip selects connected directly to peripheral\r
- ( 0 << 1) | // Fixed Peripheral Select\r
- ( 1 << 0); // Master Mode\r
- SPI_FOR_CHIPSEL_0 =\r
- ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)\r
- ( 1 << 16) | // Delay Before SPCK (1 MCK period)\r
- ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
- ( 8 << 4) | // Bits per Transfer (16 bits)\r
- ( 0 << 3) | // Chip Select inactive after transfer\r
- ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge\r
- ( 0 << 0); // Clock Polarity inactive state is logic 0\r
- break;\r
- case SPI_LCD_MODE:\r
- SPI_MODE =\r
- ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)\r
- (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
- ( 0 << 7) | // Local Loopback Disabled\r
- ( 1 << 4) | // Mode Fault Detection disabled\r
- ( 0 << 2) | // Chip selects connected directly to peripheral\r
- ( 0 << 1) | // Fixed Peripheral Select\r
- ( 1 << 0); // Master Mode\r
- SPI_FOR_CHIPSEL_2 =\r
- ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)\r
- ( 1 << 16) | // Delay Before SPCK (1 MCK period)\r
- ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
- ( 1 << 4) | // Bits per Transfer (9 bits)\r
- ( 0 << 3) | // Chip Select inactive after transfer\r
- ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge\r
- ( 0 << 0); // Clock Polarity inactive state is logic 0\r
- break;\r
- default: // Disable SPI\r
- SPI_CONTROL = SPI_CONTROL_DISABLE;\r
- break;\r
- }\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the synchronous serial port, with the one set of options that we\r
-// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
-//-----------------------------------------------------------------------------\r
-void FpgaSetupSsc(void)\r
-{\r
- // First configure the GPIOs, and get ourselves a clock.\r
- PIO_PERIPHERAL_A_SEL = (1 << GPIO_SSC_FRAME) |\r
- (1 << GPIO_SSC_DIN) |\r
- (1 << GPIO_SSC_DOUT) |\r
- (1 << GPIO_SSC_CLK);\r
- PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
-\r
- PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
-\r
- // Now set up the SSC proper, starting from a known state.\r
- SSC_CONTROL = SSC_CONTROL_RESET;\r
-\r
- // RX clock comes from TX clock, RX starts when TX starts, data changes\r
- // on RX clock rising edge, sampled on falling edge\r
- SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
-\r
- // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
- // pulse, no output sync, start on positive-going edge of sync\r
- SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
- SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
-\r
- // clock comes from TK pin, no clock output, outputs change on falling\r
- // edge of TK, start on rising edge of TF\r
- SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |\r
- SSC_CLOCK_MODE_START(5);\r
-\r
- // tx framing is the same as the rx framing\r
- SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
-\r
- SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
-// a single buffer as a circular buffer (so that we just chain back to\r
-// ourselves, not to another buffer). The stuff to manipulate those buffers\r
-// is in apps.h, because it should be inlined, for speed.\r
-//-----------------------------------------------------------------------------\r
-void FpgaSetupSscDma(BYTE *buf, int len)\r
-{\r
- PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
- PDC_RX_COUNTER(SSC_BASE) = len;\r
- PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
- PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
- PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Download the FPGA image stored in flash (slave serial).\r
-//-----------------------------------------------------------------------------\r
-void FpgaDownloadAndGo(void)\r
-{\r
- // FPGA image lives in FLASH at base address 0x2000\r
- // The current board design can not accomodate anything bigger than a XC2S30\r
- // FPGA and the config file size is fixed at 336,768 bits = 10,524 DWORDs\r
- const DWORD *FpgaImage=((DWORD *)0x2000);\r
- const DWORD FpgaImageLen=10524;\r
-\r
- int i, j;\r
-\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
- PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
- PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);\r
-\r
- SpinDelay(50);\r
-\r
- LED_D_ON();\r
-\r
- HIGH(GPIO_FPGA_NPROGRAM);\r
- LOW(GPIO_FPGA_CCLK);\r
- LOW(GPIO_FPGA_DIN);\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM) |\r
- (1 << GPIO_FPGA_CCLK) |\r
- (1 << GPIO_FPGA_DIN);\r
- SpinDelay(1);\r
-\r
- LOW(GPIO_FPGA_NPROGRAM);\r
- SpinDelay(50);\r
- HIGH(GPIO_FPGA_NPROGRAM);\r
-\r
- for(i = 0; i < FpgaImageLen; i++) {\r
- DWORD v = FpgaImage[i];\r
- for(j = 0; j < 32; j++) {\r
- if(v & 0x80000000) {\r
- HIGH(GPIO_FPGA_DIN);\r
- } else {\r
- LOW(GPIO_FPGA_DIN);\r
- }\r
- HIGH(GPIO_FPGA_CCLK);\r
- LOW(GPIO_FPGA_CCLK);\r
- v <<= 1;\r
- }\r
- }\r
-\r
- LED_D_OFF();\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Send a 16 bit command/data pair to the FPGA.\r
-// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
-// where C is the 4 bit command and D is the 12 bit data\r
-//-----------------------------------------------------------------------------\r
-void FpgaSendCommand(WORD cmd, WORD v)\r
-{\r
- SetupSpi(SPI_FPGA_MODE);\r
- while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete\r
- SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v; // send the data\r
-}\r
-//-----------------------------------------------------------------------------\r
-// Write the FPGA setup word (that determines what mode the logic is in, read\r
-// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
-// avoid changing this function's occurence everywhere in the source code.\r
-//-----------------------------------------------------------------------------\r
-void FpgaWriteConfWord(BYTE v)\r
-{\r
- FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the CMOS switches that mux the ADC: four switches, independently\r
-// closable, but should only close one at a time. Not an FPGA thing, but\r
-// the samples from the ADC always flow through the FPGA.\r
-//-----------------------------------------------------------------------------\r
-void SetAdcMuxFor(int whichGpio)\r
-{\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
- (1 << GPIO_MUXSEL_LOPKD) |\r
- (1 << GPIO_MUXSEL_LORAW) |\r
- (1 << GPIO_MUXSEL_HIRAW);\r
-\r
- PIO_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
- (1 << GPIO_MUXSEL_LOPKD) |\r
- (1 << GPIO_MUXSEL_LORAW) |\r
- (1 << GPIO_MUXSEL_HIRAW);\r
-\r
- LOW(GPIO_MUXSEL_HIPKD);\r
- LOW(GPIO_MUXSEL_HIRAW);\r
- LOW(GPIO_MUXSEL_LORAW);\r
- LOW(GPIO_MUXSEL_LOPKD);\r
-\r
- HIGH(whichGpio);\r
-}\r
projects / proxmark3-svn / blobdiff