Add Makefile for fpga directory (Windows codepath is untested, in any case, go.bat...
authorhenryk@ploetzli.ch <henryk@ploetzli.ch@ef4ab9da-24cd-11de-8aaa-f3a34680c41f>
Thu, 27 Aug 2009 23:29:49 +0000 (23:29 +0000)
committerhenryk@ploetzli.ch <henryk@ploetzli.ch@ef4ab9da-24cd-11de-8aaa-f3a34680c41f>
Thu, 27 Aug 2009 23:29:49 +0000 (23:29 +0000)
Retire rbt2c.pl, instead use objcopy to directly convert the .bit file into an .o that can be linked with the flash image
Rename armsrc/fpga.c to armsrc/fpgaloader.c (since there is now a new fpga.o, created from fpga.bit)
Remove fpgaimg.c from subversion, add fpga.bit
Instead of creating fpgaimage.elf and osimage.elf separately, now create a joined fullimage.elf
  first (obsoleting ldscript-full), then extract only the fpga and os sections with objcopy
  (This creates unspecific warnings about an empty segment, need to investigate)
Implement a rudimentary .bit parser in the firmware, use that to locate the bitstream in the new
  fpgaimage (which is just a plain copy of the fpga.bit file) and send it to the FPGA
  The code will check the format that's in flash and fall back to the legacy format

13 files changed:
armsrc/Makefile
armsrc/fpga.c [deleted file]
armsrc/fpgaimg.c [deleted file]
armsrc/fpgaloader.c [new file with mode: 0644]
armsrc/ldscript
armsrc/ldscript-fpga [deleted file]
armsrc/ldscript-full [deleted file]
armsrc/start.c
bootrom/Makefile
common/Makefile.common
fpga/Makefile [new file with mode: 0644]
fpga/fpga.bit [new file with mode: 0644]
tools/rbt2c.pl [deleted file]

index 567c8d1232fe97670ebb0499422b458babce203e..5ed76ccc36f7a73c9f104d806a211a43b0ce25b6 100644 (file)
@@ -3,41 +3,40 @@
 APP_INCLUDES = apps.h\r
 \r
 # Add the "-DWITH_LCD" flag in APP_CLFAGS to add support for LCD\r
-# and add SRC_LCD to SRC_MAIN\r
+# and add SRC_LCD to THUMBSRC\r
 APP_CFLAGS     = -O6\r
 \r
 SRC_LCD = fonts.c LCD.c\r
 \r
-SRC_MAIN = start.c \\r
+THUMBSRC = start.c \\r
        appmain.c \\r
-       fpga.c \\r
        lfops.c \\r
        iso15693.c \\r
        util.c \\r
        usb.c\r
 \r
 # These are to be compiled in ARM mode\r
-SRC_MAIN_FAST =  iso14443.c \\r
-       iso14443a.c\r
+ARMSRC =  iso14443.c \\r
+       iso14443a.c \\r
+       fpgaloader.c\r
 \r
-SRC_FPGA = fpgaimg.c\r
-\r
-THUMBSRC = $(SRC_MAIN) $(SRC_FPGA)\r
-ARMSRC = $(SRC_MAIN_FAST)\r
-\r
-MAIN_OBJ = $(patsubst %.c,$(OBJDIR)/%.o,$(SRC_MAIN) $(SRC_MAIN_FAST))\r
-\r
-# Do not move this inclusion before the definition of {THUMB,ASM,ARM}{OBJ,SRC}\r
+# Do not move this inclusion before the definition of {THUMB,ASM,ARM}SRC\r
 include ../common/Makefile.common\r
 \r
 all: $(OBJDIR)/osimage.s19 $(OBJDIR)/fpgaimage.s19\r
 \r
-$(OBJDIR)/fpgaimage.elf: $(OBJDIR)/fpgaimg.o\r
-       $(LD) -g -Tldscript-fpga -Map=$(patsubst %.elf,%.map,$@) -o $@ $^\r
+$(OBJDIR)/fpga.o: fpga.bit\r
+       $(OBJCOPY) -O elf32-littlearm -I binary -B arm --redefine-sym _binary____fpga_fpga_bit_start=_binary_fpga_bit_start --redefine-sym _binary____fpga_fpga_bit_end=_binary_fpga_bit_end --prefix-sections=fpga_bit  $^ $@\r
 \r
-$(OBJDIR)/osimage.elf: $(MAIN_OBJ) $(ARMLIB)/libgcc.a\r
+$(OBJDIR)/fullimage.elf: $(OBJDIR)/fpga.o $(THUMBOBJ) $(ARMOBJ) $(ARMLIB)/libgcc.a\r
        $(LD) -g -Tldscript -Map=$(patsubst %.elf,%.map,$@) -o $@ $^\r
 \r
+$(OBJDIR)/fpgaimage.elf: $(OBJDIR)/fullimage.elf\r
+       $(OBJCOPY) -F elf32-littlearm --only-section fpgaimage $^ $@  \r
+\r
+$(OBJDIR)/osimage.elf: $(OBJDIR)/fullimage.elf\r
+       $(OBJCOPY) -F elf32-littlearm --remove-section fpgaimage $^ $@\r
+\r
 clean:\r
        $(DELETE) $(OBJDIR)$(PATHSEP)*.o\r
        $(DELETE) $(OBJDIR)$(PATHSEP)*.elf\r
diff --git a/armsrc/fpga.c b/armsrc/fpga.c
deleted file mode 100644 (file)
index 059fc82..0000000
+++ /dev/null
@@ -1,232 +0,0 @@
-//-----------------------------------------------------------------------------\r
-// Routines to load the FPGA image, and then to configure the FPGA's major\r
-// mode once it is configured.\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-#include <proxmark3.h>\r
-#include "apps.h"\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the Serial Peripheral Interface as master\r
-// Used to write the FPGA config word\r
-// May also be used to write to other SPI attached devices like an LCD\r
-//-----------------------------------------------------------------------------\r
-void SetupSpi(int mode)\r
-{\r
-       // PA10 -> SPI_NCS2 chip select (LCD)\r
-       // PA11 -> SPI_NCS0 chip select (FPGA)\r
-       // PA12 -> SPI_MISO Master-In Slave-Out\r
-       // PA13 -> SPI_MOSI Master-Out Slave-In\r
-       // PA14 -> SPI_SPCK Serial Clock\r
-\r
-       // Disable PIO control of the following pins, allows use by the SPI peripheral\r
-       PIO_DISABLE                      =      (1 << GPIO_NCS0)        |\r
-                                                       (1 << GPIO_NCS2)        |\r
-                                                       (1 << GPIO_MISO)        |\r
-                                                       (1 << GPIO_MOSI)        |\r
-                                                       (1 << GPIO_SPCK);\r
-\r
-       PIO_PERIPHERAL_A_SEL =  (1 << GPIO_NCS0)        |\r
-                                                       (1 << GPIO_MISO)        |\r
-                                                       (1 << GPIO_MOSI)        |\r
-                                                       (1 << GPIO_SPCK);\r
-\r
-       PIO_PERIPHERAL_B_SEL =  (1 << GPIO_NCS2);\r
-\r
-       //enable the SPI Peripheral clock\r
-       PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
-       // Enable SPI\r
-       SPI_CONTROL = SPI_CONTROL_ENABLE;\r
-\r
-       switch (mode) {\r
-               case SPI_FPGA_MODE:\r
-                       SPI_MODE =\r
-                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)\r
-                               (14 << 16)      |       // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
-                               ( 0 << 7)       |       // Local Loopback Disabled\r
-                               ( 1 << 4)       |       // Mode Fault Detection disabled\r
-                               ( 0 << 2)       |       // Chip selects connected directly to peripheral\r
-                               ( 0 << 1)       |       // Fixed Peripheral Select\r
-                               ( 1 << 0);              // Master Mode\r
-                       SPI_FOR_CHIPSEL_0 =\r
-                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)\r
-                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)\r
-                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
-                               ( 8 << 4)       |       // Bits per Transfer (16 bits)\r
-                               ( 0 << 3)       |       // Chip Select inactive after transfer\r
-                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge\r
-                               ( 0 << 0);              // Clock Polarity inactive state is logic 0\r
-                       break;\r
-               case SPI_LCD_MODE:\r
-                       SPI_MODE =\r
-                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)\r
-                               (11 << 16)      |       // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
-                               ( 0 << 7)       |       // Local Loopback Disabled\r
-                               ( 1 << 4)       |       // Mode Fault Detection disabled\r
-                               ( 0 << 2)       |       // Chip selects connected directly to peripheral\r
-                               ( 0 << 1)       |       // Fixed Peripheral Select\r
-                               ( 1 << 0);              // Master Mode\r
-                       SPI_FOR_CHIPSEL_2 =\r
-                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)\r
-                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)\r
-                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
-                               ( 1 << 4)       |       // Bits per Transfer (9 bits)\r
-                               ( 0 << 3)       |       // Chip Select inactive after transfer\r
-                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge\r
-                               ( 0 << 0);              // Clock Polarity inactive state is logic 0\r
-                       break;\r
-               default:                                // Disable SPI\r
-                       SPI_CONTROL = SPI_CONTROL_DISABLE;\r
-                       break;\r
-       }\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the synchronous serial port, with the one set of options that we\r
-// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
-//-----------------------------------------------------------------------------\r
-void FpgaSetupSsc(void)\r
-{\r
-       // First configure the GPIOs, and get ourselves a clock.\r
-       PIO_PERIPHERAL_A_SEL =  (1 << GPIO_SSC_FRAME)   |\r
-                                                       (1 << GPIO_SSC_DIN)             |\r
-                                                       (1 << GPIO_SSC_DOUT)    |\r
-                                                       (1 << GPIO_SSC_CLK);\r
-       PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
-\r
-       PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
-\r
-       // Now set up the SSC proper, starting from a known state.\r
-       SSC_CONTROL = SSC_CONTROL_RESET;\r
-\r
-       // RX clock comes from TX clock, RX starts when TX starts, data changes\r
-       // on RX clock rising edge, sampled on falling edge\r
-       SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
-\r
-       // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
-       // pulse, no output sync, start on positive-going edge of sync\r
-       SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
-               SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
-\r
-       // clock comes from TK pin, no clock output, outputs change on falling\r
-       // edge of TK, start on rising edge of TF\r
-       SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |\r
-               SSC_CLOCK_MODE_START(5);\r
-\r
-       // tx framing is the same as the rx framing\r
-       SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
-\r
-       SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
-// a single buffer as a circular buffer (so that we just chain back to\r
-// ourselves, not to another buffer). The stuff to manipulate those buffers\r
-// is in apps.h, because it should be inlined, for speed.\r
-//-----------------------------------------------------------------------------\r
-void FpgaSetupSscDma(BYTE *buf, int len)\r
-{\r
-       PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
-       PDC_RX_COUNTER(SSC_BASE) = len;\r
-       PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
-       PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
-       PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Download the FPGA image stored in flash (slave serial).\r
-//-----------------------------------------------------------------------------\r
-void FpgaDownloadAndGo(void)\r
-{\r
-       // FPGA image lives in FLASH at base address 0x2000\r
-       // The current board design can not accomodate anything bigger than a XC2S30\r
-       // FPGA and the config file size is fixed at 336,768 bits = 10,524 DWORDs\r
-       const DWORD *FpgaImage=((DWORD *)0x2000);\r
-       const DWORD FpgaImageLen=10524;\r
-\r
-       int i, j;\r
-\r
-       PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
-       PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
-       PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);\r
-\r
-       SpinDelay(50);\r
-\r
-       LED_D_ON();\r
-\r
-       HIGH(GPIO_FPGA_NPROGRAM);\r
-       LOW(GPIO_FPGA_CCLK);\r
-       LOW(GPIO_FPGA_DIN);\r
-       PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM)   |\r
-                                               (1 << GPIO_FPGA_CCLK)           |\r
-                                               (1 << GPIO_FPGA_DIN);\r
-       SpinDelay(1);\r
-\r
-       LOW(GPIO_FPGA_NPROGRAM);\r
-       SpinDelay(50);\r
-       HIGH(GPIO_FPGA_NPROGRAM);\r
-\r
-       for(i = 0; i < FpgaImageLen; i++) {\r
-               DWORD v = FpgaImage[i];\r
-               for(j = 0; j < 32; j++) {\r
-                       if(v & 0x80000000) {\r
-                               HIGH(GPIO_FPGA_DIN);\r
-                       } else {\r
-                               LOW(GPIO_FPGA_DIN);\r
-                       }\r
-                       HIGH(GPIO_FPGA_CCLK);\r
-                       LOW(GPIO_FPGA_CCLK);\r
-                       v <<= 1;\r
-               }\r
-       }\r
-\r
-       LED_D_OFF();\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Send a 16 bit command/data pair to the FPGA.\r
-// The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
-// where C is the 4 bit command and D is the 12 bit data\r
-//-----------------------------------------------------------------------------\r
-void FpgaSendCommand(WORD cmd, WORD v)\r
-{\r
-       SetupSpi(SPI_FPGA_MODE);\r
-       while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0);                // wait for the transfer to complete\r
-       SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v;              // send the data\r
-}\r
-//-----------------------------------------------------------------------------\r
-// Write the FPGA setup word (that determines what mode the logic is in, read\r
-// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
-// avoid changing this function's occurence everywhere in the source code.\r
-//-----------------------------------------------------------------------------\r
-void FpgaWriteConfWord(BYTE v)\r
-{\r
-       FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
-}\r
-\r
-//-----------------------------------------------------------------------------\r
-// Set up the CMOS switches that mux the ADC: four switches, independently\r
-// closable, but should only close one at a time. Not an FPGA thing, but\r
-// the samples from the ADC always flow through the FPGA.\r
-//-----------------------------------------------------------------------------\r
-void SetAdcMuxFor(int whichGpio)\r
-{\r
-       PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
-                                               (1 << GPIO_MUXSEL_LOPKD) |\r
-                                               (1 << GPIO_MUXSEL_LORAW) |\r
-                                               (1 << GPIO_MUXSEL_HIRAW);\r
-\r
-       PIO_ENABLE              =       (1 << GPIO_MUXSEL_HIPKD) |\r
-                                               (1 << GPIO_MUXSEL_LOPKD) |\r
-                                               (1 << GPIO_MUXSEL_LORAW) |\r
-                                               (1 << GPIO_MUXSEL_HIRAW);\r
-\r
-       LOW(GPIO_MUXSEL_HIPKD);\r
-       LOW(GPIO_MUXSEL_HIRAW);\r
-       LOW(GPIO_MUXSEL_LORAW);\r
-       LOW(GPIO_MUXSEL_LOPKD);\r
-\r
-       HIGH(whichGpio);\r
-}\r
diff --git a/armsrc/fpgaimg.c b/armsrc/fpgaimg.c
deleted file mode 100644 (file)
index f8a0c65..0000000
+++ /dev/null
@@ -1,10541 +0,0 @@
-// Generated by rbt2c.pl, do not edit!
-
-//// Xilinx ASCII Bitstream
-//// Created by Bitstream K.31
-//// Design name:      fpga-placed.ncd
-//// Architecture:     spartan2
-//// Part:             2s30vq100
-//// Date:             Mon Jul 20 21:46:13 2009
-//// Bits:             336768
-
-#include <proxmark3.h>
-
-const DWORD FpgaImage[] = {
-       0xffffffff,
-       0xaa995566,
-       0x30008001,
-       0x00000007,
-       0x30016001,
-       0x00000008,
-       0x30012001,
-       0x00803f2d,
-       0x3000c001,
-       0x00000000,
-       0x30008001,
-       0x00000009,
-       0x30002001,
-       0x00000000,
-       0x30008001,
-       0x00000001,
-       0x30004000,
-       0x50002463,
-       0x00121000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000480,
-       0x00000000,
-       0x00121000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000480,
-       0x00000000,
-       0x10020000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x000100c0,
-       0x00000000,
-       0x00030000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000080,
-       0x00000000,
-       0x00120000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000680,
-       0x00000000,
-       0x00120000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000480,
-       0x00000000,
-       0x00124000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000680,
-       0x00000000,
-       0xef100060,
-       0x00180006,
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-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x30000001,
-       0x00002513,
-       0x30008001,
-       0x00000003,
-       0x30004009,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x30008001,
-       0x00000005,
-       0x3000a001,
-       0x00000000,
-       0x30000001,
-       0x0000c17d,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-};
-
-const DWORD FpgaImageLen = sizeof(FpgaImage) / sizeof(FpgaImage[0]);
-
diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c
new file mode 100644 (file)
index 0000000..e07c254
--- /dev/null
@@ -0,0 +1,332 @@
+//-----------------------------------------------------------------------------\r
+// Routines to load the FPGA image, and then to configure the FPGA's major\r
+// mode once it is configured.\r
+//\r
+// Jonathan Westhues, April 2006\r
+//-----------------------------------------------------------------------------\r
+#include <proxmark3.h>\r
+#include "apps.h"\r
+\r
+//-----------------------------------------------------------------------------\r
+// Set up the Serial Peripheral Interface as master\r
+// Used to write the FPGA config word\r
+// May also be used to write to other SPI attached devices like an LCD\r
+//-----------------------------------------------------------------------------\r
+void SetupSpi(int mode)\r
+{\r
+       // PA10 -> SPI_NCS2 chip select (LCD)\r
+       // PA11 -> SPI_NCS0 chip select (FPGA)\r
+       // PA12 -> SPI_MISO Master-In Slave-Out\r
+       // PA13 -> SPI_MOSI Master-Out Slave-In\r
+       // PA14 -> SPI_SPCK Serial Clock\r
+\r
+       // Disable PIO control of the following pins, allows use by the SPI peripheral\r
+       PIO_DISABLE                      =      (1 << GPIO_NCS0)        |\r
+                                                       (1 << GPIO_NCS2)        |\r
+                                                       (1 << GPIO_MISO)        |\r
+                                                       (1 << GPIO_MOSI)        |\r
+                                                       (1 << GPIO_SPCK);\r
+\r
+       PIO_PERIPHERAL_A_SEL =  (1 << GPIO_NCS0)        |\r
+                                                       (1 << GPIO_MISO)        |\r
+                                                       (1 << GPIO_MOSI)        |\r
+                                                       (1 << GPIO_SPCK);\r
+\r
+       PIO_PERIPHERAL_B_SEL =  (1 << GPIO_NCS2);\r
+\r
+       //enable the SPI Peripheral clock\r
+       PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
+       // Enable SPI\r
+       SPI_CONTROL = SPI_CONTROL_ENABLE;\r
+\r
+       switch (mode) {\r
+               case SPI_FPGA_MODE:\r
+                       SPI_MODE =\r
+                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)\r
+                               (14 << 16)      |       // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
+                               ( 0 << 7)       |       // Local Loopback Disabled\r
+                               ( 1 << 4)       |       // Mode Fault Detection disabled\r
+                               ( 0 << 2)       |       // Chip selects connected directly to peripheral\r
+                               ( 0 << 1)       |       // Fixed Peripheral Select\r
+                               ( 1 << 0);              // Master Mode\r
+                       SPI_FOR_CHIPSEL_0 =\r
+                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)\r
+                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)\r
+                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
+                               ( 8 << 4)       |       // Bits per Transfer (16 bits)\r
+                               ( 0 << 3)       |       // Chip Select inactive after transfer\r
+                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge\r
+                               ( 0 << 0);              // Clock Polarity inactive state is logic 0\r
+                       break;\r
+               case SPI_LCD_MODE:\r
+                       SPI_MODE =\r
+                               ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)\r
+                               (11 << 16)      |       // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
+                               ( 0 << 7)       |       // Local Loopback Disabled\r
+                               ( 1 << 4)       |       // Mode Fault Detection disabled\r
+                               ( 0 << 2)       |       // Chip selects connected directly to peripheral\r
+                               ( 0 << 1)       |       // Fixed Peripheral Select\r
+                               ( 1 << 0);              // Master Mode\r
+                       SPI_FOR_CHIPSEL_2 =\r
+                               ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)\r
+                               ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)\r
+                               ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
+                               ( 1 << 4)       |       // Bits per Transfer (9 bits)\r
+                               ( 0 << 3)       |       // Chip Select inactive after transfer\r
+                               ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge\r
+                               ( 0 << 0);              // Clock Polarity inactive state is logic 0\r
+                       break;\r
+               default:                                // Disable SPI\r
+                       SPI_CONTROL = SPI_CONTROL_DISABLE;\r
+                       break;\r
+       }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Set up the synchronous serial port, with the one set of options that we\r
+// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
+//-----------------------------------------------------------------------------\r
+void FpgaSetupSsc(void)\r
+{\r
+       // First configure the GPIOs, and get ourselves a clock.\r
+       PIO_PERIPHERAL_A_SEL =  (1 << GPIO_SSC_FRAME)   |\r
+                                                       (1 << GPIO_SSC_DIN)             |\r
+                                                       (1 << GPIO_SSC_DOUT)    |\r
+                                                       (1 << GPIO_SSC_CLK);\r
+       PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
+\r
+       PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
+\r
+       // Now set up the SSC proper, starting from a known state.\r
+       SSC_CONTROL = SSC_CONTROL_RESET;\r
+\r
+       // RX clock comes from TX clock, RX starts when TX starts, data changes\r
+       // on RX clock rising edge, sampled on falling edge\r
+       SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
+\r
+       // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
+       // pulse, no output sync, start on positive-going edge of sync\r
+       SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
+               SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
+\r
+       // clock comes from TK pin, no clock output, outputs change on falling\r
+       // edge of TK, start on rising edge of TF\r
+       SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |\r
+               SSC_CLOCK_MODE_START(5);\r
+\r
+       // tx framing is the same as the rx framing\r
+       SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
+\r
+       SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
+// a single buffer as a circular buffer (so that we just chain back to\r
+// ourselves, not to another buffer). The stuff to manipulate those buffers\r
+// is in apps.h, because it should be inlined, for speed.\r
+//-----------------------------------------------------------------------------\r
+void FpgaSetupSscDma(BYTE *buf, int len)\r
+{\r
+       PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
+       PDC_RX_COUNTER(SSC_BASE) = len;\r
+       PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
+       PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
+       PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
+}\r
+\r
+// Download the fpga image starting at FpgaImage and with length FpgaImageLen DWORDs (e.g. 4 bytes)\r
+// If bytereversal is set: reverse the byte order in each 4-byte word\r
+static void DownloadFPGA(const DWORD *FpgaImage, DWORD FpgaImageLen, int bytereversal)\r
+{\r
+       int i, j;\r
+\r
+       PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
+       PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
+       PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);\r
+\r
+       SpinDelay(50);\r
+\r
+       LED_D_ON();\r
+\r
+       HIGH(GPIO_FPGA_NPROGRAM);\r
+       LOW(GPIO_FPGA_CCLK);\r
+       LOW(GPIO_FPGA_DIN);\r
+       PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM)   |\r
+                                               (1 << GPIO_FPGA_CCLK)           |\r
+                                               (1 << GPIO_FPGA_DIN);\r
+       SpinDelay(1);\r
+\r
+       LOW(GPIO_FPGA_NPROGRAM);\r
+       SpinDelay(50);\r
+       HIGH(GPIO_FPGA_NPROGRAM);\r
+\r
+       for(i = 0; i < FpgaImageLen; i++) {\r
+               DWORD v = FpgaImage[i];\r
+               unsigned char w;\r
+               for(j = 0; j < 4; j++) {\r
+                       if(!bytereversal) \r
+                               w = v >>(j*8);\r
+                       else\r
+                               w = v >>((3-j)*8);\r
+#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }\r
+                       SEND_BIT(7);\r
+                       SEND_BIT(6);\r
+                       SEND_BIT(5);\r
+                       SEND_BIT(4);\r
+                       SEND_BIT(3);\r
+                       SEND_BIT(2);\r
+                       SEND_BIT(1);\r
+                       SEND_BIT(0);\r
+               }\r
+       }\r
+\r
+       LED_D_OFF();\r
+}\r
+\r
+static char *bitparse_headers_start;\r
+static char *bitparse_bitstream_end;\r
+static int bitparse_initialized;\r
+/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence\r
+ * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01\r
+ * After that the format is 1 byte section type (ASCII character), 2 byte length\r
+ * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes\r
+ * length.
+ */\r
+static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};\r
+static int bitparse_init(void * start_address, void *end_address)\r
+{\r
+       bitparse_initialized = 0;\r
+       \r
+       if(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) {\r
+               return 0; /* Not matched */\r
+       } else {\r
+               bitparse_headers_start= ((char*)start_address) + sizeof(_bitparse_fixed_header);\r
+               bitparse_bitstream_end= (char*)end_address;\r
+               bitparse_initialized = 1;\r
+               return 1;\r
+       }\r
+}\r
+\r
+int bitparse_find_section(char section_name, void **section_start, unsigned int *section_length)\r
+{\r
+       char *pos = bitparse_headers_start;\r
+       int result = 0;\r
+\r
+       if(!bitparse_initialized) return 0;\r
+\r
+       while(pos < bitparse_bitstream_end) {\r
+               char current_name = *pos++;\r
+               unsigned int current_length = 0;\r
+               if(current_name < 'a' || current_name > 'e') {\r
+                       /* Strange section name, abort */\r
+                       break;\r
+               }\r
+               current_length = 0;\r
+               switch(current_name) {\r
+               case 'e':\r
+                       /* Four byte length field */\r
+                       current_length += (*pos++) << 24;\r
+                       current_length += (*pos++) << 16;\r
+               default: /* Fall through, two byte length field */\r
+                       current_length += (*pos++) << 8;\r
+                       current_length += (*pos++) << 0;\r
+               }\r
+               \r
+               if(current_name != 'e' && current_length > 255) {\r
+                       /* Maybe a parse error */\r
+                       break;\r
+               }\r
+               \r
+               if(current_name == section_name) {\r
+                       /* Found it */\r
+                       *section_start = pos;\r
+                       *section_length = current_length;\r
+                       result = 1;\r
+                       break;\r
+               }\r
+               \r
+               pos += current_length; /* Skip section */\r
+       }\r
+       \r
+       return result;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Find out which FPGA image format is stored in flash, then call DownloadFPGA\r
+// with the right parameters to download the image\r
+//-----------------------------------------------------------------------------\r
+extern char _binary_fpga_bit_start, _binary_fpga_bit_end;\r
+void FpgaDownloadAndGo(void)\r
+{\r
+       /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
+        */\r
+       if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {\r
+               /* Successfully initialized the .bit parser. Find the 'e' section and\r
+                * send its contents to the FPGA.
+                */\r
+               void *bitstream_start;\r
+               unsigned int bitstream_length;\r
+               if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {\r
+                       DownloadFPGA((DWORD *)bitstream_start, bitstream_length/4, 0);\r
+                       \r
+                       return; /* All done */\r
+               }\r
+       }\r
+       \r
+       /* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF\r
+        * 0xAA995566 at address 0x2000. This is raw bitstream with a size of 336,768 bits \r
+        * = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD\r
+        * is still to be transmitted in MSBit first order. Set the invert flag to indicate\r
+        * that the DownloadFPGA function should invert every 4 byte sequence when doing\r
+        * the bytewise download.
+        */\r
+       if( *(DWORD*)0x2000 == 0xFFFFFFFF && *(DWORD*)0x2004 == 0xAA995566 )\r
+               DownloadFPGA((DWORD *)0x2000, 10524, 1);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Send a 16 bit command/data pair to the FPGA.\r
+// The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
+// where C is the 4 bit command and D is the 12 bit data\r
+//-----------------------------------------------------------------------------\r
+void FpgaSendCommand(WORD cmd, WORD v)\r
+{\r
+       SetupSpi(SPI_FPGA_MODE);\r
+       while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0);                // wait for the transfer to complete\r
+       SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v;              // send the data\r
+}\r
+//-----------------------------------------------------------------------------\r
+// Write the FPGA setup word (that determines what mode the logic is in, read\r
+// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
+// avoid changing this function's occurence everywhere in the source code.\r
+//-----------------------------------------------------------------------------\r
+void FpgaWriteConfWord(BYTE v)\r
+{\r
+       FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Set up the CMOS switches that mux the ADC: four switches, independently\r
+// closable, but should only close one at a time. Not an FPGA thing, but\r
+// the samples from the ADC always flow through the FPGA.\r
+//-----------------------------------------------------------------------------\r
+void SetAdcMuxFor(int whichGpio)\r
+{\r
+       PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
+                                               (1 << GPIO_MUXSEL_LOPKD) |\r
+                                               (1 << GPIO_MUXSEL_LORAW) |\r
+                                               (1 << GPIO_MUXSEL_HIRAW);\r
+\r
+       PIO_ENABLE              =       (1 << GPIO_MUXSEL_HIPKD) |\r
+                                               (1 << GPIO_MUXSEL_LOPKD) |\r
+                                               (1 << GPIO_MUXSEL_LORAW) |\r
+                                               (1 << GPIO_MUXSEL_HIRAW);\r
+\r
+       LOW(GPIO_MUXSEL_HIPKD);\r
+       LOW(GPIO_MUXSEL_HIRAW);\r
+       LOW(GPIO_MUXSEL_LORAW);\r
+       LOW(GPIO_MUXSEL_LOPKD);\r
+\r
+       HIGH(whichGpio);\r
+}\r
index 81ed4edf3962201383b0f47bc8977d9a69084ee7..3219a041de6fecf656fb27cc6ff8cc8183bd7eaf 100644 (file)
@@ -3,7 +3,10 @@ INCLUDE ../common/ldscript.common
 ENTRY(Vector)\r
 SECTIONS\r
 {\r
-       .start : { obj/start.o(.text) } >osimage\r
+       fpgaimage : {\r
+               *(fpga_bit.data)\r
+       } >fpgaimage\r
+       .start : { *(.startos) } >osimage\r
        .text : { \r
                *(.text)\r
                *(.text.*)\r
diff --git a/armsrc/ldscript-fpga b/armsrc/ldscript-fpga
deleted file mode 100644 (file)
index b49677a..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-INCLUDE ../common/ldscript.common\r
-\r
-SECTIONS\r
-{\r
-       fpgaimage : { \r
-               obj/fpgaimg.o(.text) *(.text) \r
-               *(.rodata) \r
-               *(.glue_7)\r
-               *(.glue_7t)\r
-       } >fpgaimage\r
-       .data : { *(.data) } >ram\r
-       __bss_start__ = .;\r
-       .bss : { *(.bss) } >ram\r
-       __bss_end__ = .;\r
-}\r
diff --git a/armsrc/ldscript-full b/armsrc/ldscript-full
deleted file mode 100644 (file)
index 712b485..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-SECTIONS\r
-{\r
-       . = 0x00002000;\r
-       .fpga : { obj/fpgaimg.o(.rodata) }\r
-       . = 0x00010000;\r
-       .start : { obj/start.o(.text) }\r
-       .text : { *(.text) }\r
-       .rodata : { *(.rodata) }\r
-       . = 0x00200000;\r
-       .data : { *(.data) }\r
-       __bss_start__ = .;\r
-       .bss : { *(.bss) }\r
-       __bss_end__ = .;\r
-}\r
index 52296fc206323178d8fb48c18e14c5c20be1e903..de2dd2f639c3e0d8c8cf86c963f6a9583c3729d8 100644 (file)
@@ -6,7 +6,7 @@
 #include <proxmark3.h>\r
 #include "apps.h"\r
 \r
-void Vector(void)\r
+void __attribute__((section(".startos"))) Vector(void)\r
 {\r
        AppMain();\r
 }\r
index 43e2533fd0b674250302d61a9fea9dcb647dc0d9..2b7671c7fc12762a8dd17c6e58c08a54e50f960b 100644 (file)
@@ -5,7 +5,7 @@ ARMSRC = fromflash.c
 THUMBSRC = usb.c bootrom.c\r
 ASMSRC = ram-reset.s flash-reset.s\r
 \r
-# Do not move this inclusion before the definition of {THUMB,ASM,ARM}{OBJ,SRC}\r
+# Do not move this inclusion before the definition of {THUMB,ASM,ARM}SRC\r
 include ../common/Makefile.common\r
 \r
 all: $(OBJDIR)/bootrom.s19\r
index 1c4738a16516967b86331b24c2e4eaa049449f03..a17b8a1bb2bd650be3b30937addb4adee345212e 100644 (file)
@@ -46,8 +46,8 @@ OBJDIR        = obj
 
 INCLUDE = -I../include
 
-# Also search prerequisites in the common directory (for usb.c)
-VPATH = . ../common/
+# Also search prerequisites in the common directory (for usb.c), and the fpga directory (for fpga.bit)
+VPATH = . ../common/ ../fpga/
 
 INCLUDES = ../include/proxmark3.h ../include/at91sam7s128.h ../include/config_gpio.h ../include/usb_cmd.h $(APP_INCLUDES)
 
diff --git a/fpga/Makefile b/fpga/Makefile
new file mode 100644 (file)
index 0000000..84155b4
--- /dev/null
@@ -0,0 +1,36 @@
+include ../common/Makefile.common
+
+all: fpga.ngc fpga.ngd fpga.ncd fpga-placed.ncd fpga.bit
+clean:
+       $(DELETE) fpga.bgn  fpga.drc  fpga.ncd           fpga.ngd            fpga_par.xrpt    fpga-placed.pad      fpga-placed.par       fpga-placed.xpi   fpga_usage.xml  xlnx_auto_0.ise  xst.srp
+       $(DELETE) fpga.bit  fpga.map  fpga.ngc           fpga_ngdbuild.xrpt  fpga.pcf         fpga-placed_pad.csv  fpga-placed.ptwx      fpga.rbt          xlnx_auto_0_xdb
+       $(DELETE) fpga.bld  fpga.mrp  fpga.ngc_xst.xrpt  fpga.ngm            fpga-placed.ncd  fpga-placed_pad.txt  fpga-placed.unroutes  fpga_summary.xml  netlist.lst     xst
+
+fpga.ngc: fpga.v fpga.ucf xst.scr util.v lo_simulate.v lo_read.v lo_passthru.v hi_simulate.v hi_read_tx.v hi_read_rx_xcorr.v hi_iso14443a.v
+       $(DELETE) fpga.ngc
+       $(XILINX_TOOLS_PREFIX)xst -ifn xst.scr
+
+fpga.ngd: fpga.ngc
+       $(DELETE) fpga.ngd
+       $(XILINX_TOOLS_PREFIX)ngdbuild -aul -p xc2s30-6vq100 -nt timestamp -uc fpga.ucf fpga.ngc fpga.ngd
+
+fpga.ncd: fpga.ngd
+       $(DELETE) fpga.ncd
+       $(XILINX_TOOLS_PREFIX)map -p xc2s30-6vq100 fpga.ngd
+
+fpga-placed.ncd: fpga.ncd
+       $(DELETE) fpga-placed.ncd
+       $(XILINX_TOOLS_PREFIX)par fpga.ncd fpga-placed.ncd
+
+fpga.bit: fpga-placed.ncd
+       $(DELETE) fpga.bit fpga.drc fpga.rbt
+       $(XILINX_TOOLS_PREFIX)bitgen fpga-placed.ncd fpga.bit
+
+
+.PHONY: all clean help
+help:
+       @echo Multi-OS Makefile, you are running on $(DETECTED_OS)
+       @echo Possible targets:
+       @echo + all   - Make fpga.bti, the FPGA bitstream 
+       @echo + clean - Clean intermediate files
+       
\ No newline at end of file
diff --git a/fpga/fpga.bit b/fpga/fpga.bit
new file mode 100644 (file)
index 0000000..d3a4180
Binary files /dev/null and b/fpga/fpga.bit differ
diff --git a/tools/rbt2c.pl b/tools/rbt2c.pl
deleted file mode 100644 (file)
index 3e1e1fc..0000000
+++ /dev/null
@@ -1,41 +0,0 @@
-#!/usr/bin/perl\r
-\r
-# This tool converts a Xilinx xxx.rbt FPGA bitstream to a table that will\r
-# compile as C source code. The output format is DWORDs, MSB first.\r
-\r
-local $/ = "\r\n";\r
-\r
-print "// Generated by rbt2c.pl, do not edit!\n\n";\r
-\r
-for(1..7) {\r
-       chomp($_ = <>);\r
-       print "//// $_\n";\r
-}\r
-\r
-print <<EOT;\r
-\r
-#include <proxmark3.h>\r
-\r
-const DWORD FpgaImage[] = {\r
-EOT\r
-\r
-while(<>) {\r
-       chomp;\r
-       $v = 0;\r
-       for $b (split(//, $_)) {\r
-               $v <<= 1;\r
-               if($b eq '1') {\r
-                       $v |= 1;\r
-               } elsif($b ne '0') {\r
-                       die;\r
-               }\r
-       }\r
-       printf("\t0x%08x,\n", $v);\r
-}\r
-\r
-print <<EOT;\r
-};\r
-\r
-const DWORD FpgaImageLen = sizeof(FpgaImage) / sizeof(FpgaImage[0]);\r
-\r
-EOT\r
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