// the license.
//-----------------------------------------------------------------------------
// Miscellaneous routines for low frequency tag operations.
-// Tags supported here so far are Texas Instruments (TI), HID
+// Tags supported here so far are Texas Instruments (TI), HID, EM4x05, EM410x
// Also routines for raw mode reading/simulating of LF waveform
//-----------------------------------------------------------------------------
*/
void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
{
-
+ // start timer
StartTicks();
- int divisor_used = 95; // 125 KHz
- // see if 'h' was specified
- if (command[strlen((char *) command) - 1] == 'h')
- divisor_used = 88; // 134.8 KHz
+ // use lf config settings
+ sample_config *sc = getSamplingConfig();
- sample_config sc = { 0,0,1, divisor_used, 0};
- setSamplingConfig(&sc);
- //clear read buffer
- BigBuf_Clear_keep_EM();
-
- /* Make sure the tag is reset */
+ // Make sure the tag is reset
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
WaitMS(2500);
- //power on
- LFSetupFPGAForADC(sc.divisor, 1);
+ // clear read buffer (after fpga bitstream loaded...)
+ BigBuf_Clear_keep_EM();
+
+ // power on
+ LFSetupFPGAForADC(sc->divisor, 1);
// And a little more time for the tag to fully power up
WaitMS(2000);
// now modulate the reader field
if (bitbang) {
- //HACK it appears my loop and if statements take up about 7 us so adjust waits accordingly...
+ // HACK it appears the loop and if statements take up about 7us so adjust waits accordingly...
uint8_t hack_cnt = 7;
if (period_0 < hack_cnt || period_1 < hack_cnt) {
- DbpString("Warning periods cannot be less than 7 in bit bang mode");
+ DbpString("Warning periods cannot be less than 7us in bit bang mode");
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_D_OFF();
return;
}
- //prime cmd_len to save time comparing strings while modulating
+
+ // hack2 needed--- it appears to take about 8-16us to turn the antenna back on
+ // leading to ~ 1 to 2 125khz samples extra in every off period
+ // so we should test for last 0 before next 1 and reduce period_0 by this extra amount...
+ // but is this time different for every antenna or other hw builds??? more testing needed
+
+ // prime cmd_len to save time comparing strings while modulating
int cmd_len = 0;
while(command[cmd_len] != '\0' && command[cmd_len] != ' ')
cmd_len++;
int counter = 0;
bool off = false;
for (counter = 0; counter < cmd_len; counter++) {
- //while(*command != '\0' && *command != ' ') {
// if cmd = 0 then turn field off
if (command[counter] == '0') {
// if field already off leave alone (affects timing otherwise)
LED_D_OFF();
off = true;
}
- // note we appear to take about 6us to switch over (or run the if statements/loop...)
+ // note we appear to take about 7us to switch over (or run the if statements/loop...)
WaitUS(period_0-hack_cnt);
// else if cmd = 1 then turn field on
} else {
// if field already on leave alone (affects timing otherwise)
if (off) {
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
LED_D_ON();
off = false;
}
- // note we appear to take about 6us to switch over (or run the if statements/loop...)
+ // note we appear to take about 7us to switch over (or run the if statements/loop...)
WaitUS(period_1-hack_cnt);
}
}
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_D_OFF();
WaitUS(delay_off);
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
LED_D_ON();
if(*(command++) == '0') {
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_D_OFF();
WaitUS(delay_off);
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
}
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
// now do the read
DoAcquisition_config(false, 0);
- // note leaves field on... (for future commands?)
+
+ // Turn off antenna
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ // tell client we are done
+ cmd_send(CMD_ACK,0,0,0,0,0);
}
/* blank r/w tag data stream
uint8_t wavesPerClock = clock/fc;
uint8_t mod = clock % fc; //modifier
uint8_t modAdj = fc/mod; //how often to apply modifier
- bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
+ bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=true;
// loop through clock - step field clock
for (uint8_t idx=0; idx < wavesPerClock; idx++){
// put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
// prepare a waveform pattern in the buffer based on the ID given then
// simulate a HID tag until the button is pressed
-void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
+void CmdHIDsimTAG(int hi2, int hi, int lo, int ledcontrol)
{
int n=0, i=0;
/*
nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
*/
- if (hi>0xFFF) {
- DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
+ if (hi2>0x0FFFFFFF) {
+ DbpString("Tags can only have 44 or 84 bits. - USE lf simfsk for larger tags");
return;
}
// set LF so we don't kill the bigbuf we are setting with simulation data.
fc(8, &n); fc(10, &n); // logical 0
WDT_HIT();
- // manchester encode bits 43 to 32
- for (i=11; i>=0; i--) {
- if ((i%4)==3) fc(0,&n);
- if ((hi>>i)&1) {
- fc(10, &n); fc(8, &n); // low-high transition
- } else {
- fc(8, &n); fc(10, &n); // high-low transition
+ if (hi2 > 0 || hi > 0xFFF){
+ // manchester encode bits 91 to 64 (91-84 are part of the header)
+ for (i=27; i>=0; i--) {
+ if ((i%4)==3) fc(0,&n);
+ if ((hi2>>i)&1) {
+ fc(10, &n); fc(8, &n); // low-high transition
+ } else {
+ fc(8, &n); fc(10, &n); // high-low transition
+ }
+ }
+ WDT_HIT();
+ // manchester encode bits 63 to 32
+ for (i=31; i>=0; i--) {
+ if ((i%4)==3) fc(0,&n);
+ if ((hi>>i)&1) {
+ fc(10, &n); fc(8, &n); // low-high transition
+ } else {
+ fc(8, &n); fc(10, &n); // high-low transition
+ }
+ }
+ } else {
+ // manchester encode bits 43 to 32
+ for (i=11; i>=0; i--) {
+ if ((i%4)==3) fc(0,&n);
+ if ((hi>>i)&1) {
+ fc(10, &n); fc(8, &n); // low-high transition
+ } else {
+ fc(8, &n); fc(10, &n); // high-low transition
+ }
}
}
for (i=0; i<size; i++){
if (BitStream[i] == curPhase){
- pskSimBit(carrier, &n, clk, &curPhase, FALSE);
+ pskSimBit(carrier, &n, clk, &curPhase, false);
} else {
- pskSimBit(carrier, &n, clk, &curPhase, TRUE);
+ pskSimBit(carrier, &n, clk, &curPhase, true);
}
}
Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
}
// loop to get raw HID waveform then FSK demodulate the TAG ID from it
-void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
+void CmdHIDdemodFSK(int findone, int *high2, int *high, int *low, int ledcontrol)
{
uint8_t *dest = BigBuf_get_addr();
//const size_t sizeOfBigBuff = BigBuf_max_traceLen();
BigBuf_Clear_keep_EM();
while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
-
WDT_HIT();
if (ledcontrol) LED_A_ON();
idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo, &dummyIdx);
if (idx>0 && lo>0 && (size==96 || size==192)){
+ uint8_t bitlen = 0;
+ uint32_t fc = 0;
+ uint32_t cardnum = 0;
+ bool decoded = false;
+
// go over previously decoded manchester data and decode into usable tag ID
- if (hi2 != 0){ //extra large HID tags 88/192 bits
- Dbprintf("TAG ID: %x%08x%08x (%d)",
- (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
- }else { //standard HID tags 44/96 bits
- //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
- uint8_t bitlen = 0;
- uint32_t fc = 0;
- uint32_t cardnum = 0;
- if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
- uint32_t lo2=0;
- lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
- uint8_t idx3 = 1;
- while(lo2 > 1){ //find last bit set to 1 (format len bit)
- lo2=lo2 >> 1;
- idx3++;
- }
- bitlen = idx3+19;
- fc =0;
- cardnum=0;
- if(bitlen == 26){
- cardnum = (lo>>1)&0xFFFF;
- fc = (lo>>17)&0xFF;
- }
- if(bitlen == 37){
- cardnum = (lo>>1)&0x7FFFF;
- fc = ((hi&0xF)<<12)|(lo>>20);
- }
- if(bitlen == 34){
- cardnum = (lo>>1)&0xFFFF;
- fc= ((hi&1)<<15)|(lo>>17);
- }
- if(bitlen == 35){
- cardnum = (lo>>1)&0xFFFFF;
- fc = ((hi&1)<<11)|(lo>>21);
- }
+ if ((hi2 & 0x000FFFF) != 0){ //extra large HID tags 88/192 bits
+ uint32_t bp = hi2 & 0x000FFFFF;
+ bitlen = 63;
+ while (bp > 0) {
+ bp = bp >> 1;
+ bitlen++;
}
- else { //if bit 38 is not set then 37 bit format is used
- bitlen= 37;
- fc =0;
- cardnum=0;
- if(bitlen==37){
- cardnum = (lo>>1)&0x7FFFF;
- fc = ((hi&0xF)<<12)|(lo>>20);
- }
+ } else if ((hi >> 6) > 0) {
+ uint32_t bp = hi;
+ bitlen = 31;
+ while (bp > 0) {
+ bp = bp >> 1;
+ bitlen++;
+ }
+ } else if (((hi >> 5) & 1) == 0) {
+ bitlen = 37;
+ } else if ((hi & 0x0000001F) > 0 ) {
+ uint32_t bp = (hi & 0x0000001F);
+ bitlen = 31;
+ while (bp > 0) {
+ bp = bp >> 1;
+ bitlen++;
}
- //Dbprintf("TAG ID: %x%08x (%d)",
- // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
- Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
- (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
- (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
+ } else {
+ uint32_t bp = lo;
+ bitlen = 0;
+ while (bp > 0) {
+ bp = bp >> 1;
+ bitlen++;
+ }
+ }
+ switch (bitlen){
+ case 26:
+ cardnum = (lo>>1)&0xFFFF;
+ fc = (lo>>17)&0xFF;
+ decoded = true;
+ break;
+ case 35:
+ cardnum = (lo>>1)&0xFFFFF;
+ fc = ((hi&1)<<11)|(lo>>21);
+ decoded = true;
+ break;
}
+
+ if (hi2 != 0) //extra large HID tags 88/192 bits
+ Dbprintf("TAG ID: %x%08x%08x (%d)",
+ (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+ else
+ Dbprintf("TAG ID: %x%08x (%d)",
+ (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+
+ if (decoded)
+ Dbprintf("Format Len: %dbits - FC: %d - Card: %d",
+ (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
+
if (findone){
if (ledcontrol) LED_A_OFF();
+ *high2 = hi2;
*high = hi;
*low = lo;
break;
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Now set up the SSC to get the ADC samples that are now streaming at us.
- FpgaSetupSsc();
+ FpgaSetupSsc(FPGA_MAJOR_MODE_LF_ADC);
// start clock - 1.5ticks is 1us
StartTicks();
projects / proxmark3-svn / blobdiff